Semiconductor device and method for manufacturing the same

Abstract

The embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor body, comprising a substrate, a buried layer and an epitaxial layer, the substrate having a first doping type, the buried layer having a second doping type; a first trench extending from a top surface of the epitaxial layer into the substrate; a second trench extending from a top surface of the epitaxial layer into the substrate; and a third trench extending from a top surface of the epitaxial layer into the buried layer or into a position in the epitaxial layer close to the buried layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Bipolar CMOSDMOS (BCD) technology is able to integrate analog components, digital components, and high voltage (HV) devices into a single chip or integrated circuit (IC) to form an embedded device. Such chips or ICs can be widely used in automotive and industrial applications. However, it is difficult to integrate these different types of devices on a single die or chip because interference is prone to occur between different devices. For example, high voltage devices may have latch-up problems, which may adversely affect the reliability of the entire product during integration. Therefore, it is necessary to properly isolate different types of devices from each other during the integration process. However, traditional junction isolation technology for isolating different types of devices consumes a large layout area and requires additional mask steps, which complicates the manufacturing process and increases manufacturing costs. In addition, HV devices integrated with analog and digital components that are isolated using traditional isolation schemes may not have a high breakdown voltage (BV).

[0003] Therefore, it is desirable to provide a reliable, high-performance, simple and cost-effective solution to integrate various suitable isolation structures. Summary of the invention

[0004] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing the same to solve the above problems existing in the prior art, for example, to integrate various suitable isolation structures with a reliable, high-performance, simple and cost-effective solution to effectively isolate the HV device from other devices in the same IC.

[0005] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench, a second trench, and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing undoped polysilicon so that undoped polysilicon is formed on the sidewalls and bottom of the first trench, the second trench, and the third trench; depositing a diffusion material so that the diffusion material is formed on the sidewalls and bottom of the first trench, the second trench, and the third trench; Completely fill the third trench with a filling material; remove the diffusion material and the filling material from the first trench and the second trench; form a first doped region with the second doping type in the epitaxial layer near the sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer, and configured to electrically connect the buried layer to the top surface of the epitaxial layer; form a trench oxide layer on the sidewalls and bottom of the first trench, the second trench and the third trench; deposit a dielectric layer so that a dielectric layer is formed on the oxide layer on the sidewalls and bottom of the first trench, the second trench and the third trench, and etch the dielectric layer and the oxide layer at the bottom of the first trench; deposit a conductive material so that the conductive material fills at least the first trench; remove the conductive material on the hard mask layer; form a plurality of device regions in the epitaxial layer.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing undoped polysilicon so that undoped polysilicon is formed on the sidewalls and bottom of the first trench and the third trench; depositing a diffusion material so that the diffusion material is formed on the sidewalls and bottom of the first trench and the third trench; Completely fill the third trench with a filling material; remove the diffusion material and the filling material from the first trench; form a first doped region with the second doping type in the epitaxial layer near the sidewall of the third trench, the first doped region extending from the top surface of the epitaxial layer to the buried layer, and configured to electrically connect the buried layer to the top surface of the epitaxial layer; form a trench oxide layer on the sidewalls and bottom of the first and third trenches; deposit a dielectric layer so that a dielectric layer is formed on the oxide layer on the sidewalls and bottom of the first and third trenches, and etch the dielectric layer and oxide layer at the bottom of the first trench; deposit a conductive material so that the conductive material fills at least the first trench; remove the conductive material on the hard mask layer; and form a plurality of device regions in the epitaxial layer.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench, a second trench, and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing a conductive material layer to fill the first trench, the second trench, and the third trench; removing the conductive material layer in the first trench and the second trench, and retaining the conductive material layer in the third trench; forming a deposited oxide layer to fill the second trench, while the first trench remains open; etching to open the bottom of the first trench to form an opening; depositing a conductive material so that the conductive material fills at least the first trench; removing the conductive material on the hard mask layer; and forming a plurality of device regions in the epitaxial layer.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing a conductive material layer to fill the first trench and the third trench; removing the conductive material layer in the first trench and retaining the conductive material layer in the third trench; etching to open the bottom of the first trench to form an opening; depositing a conductive material so that the conductive material fills at least the first trench; removing the conductive material on the hard mask layer; and forming a plurality of device regions in the epitaxial layer.

[0009] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench, a second trench, and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing a conductive material layer to fill the first trench, the second trench, and the third trench; removing the conductive material layer in the first trench and the second trench, and retaining the conductive material layer in the third trench; forming a deposited oxide layer to fill the second trench, while the first trench remains open; etching to open the bottom of the first trench to form an opening; depositing a conductive material so that the conductive material fills at least the first trench; removing the conductive material on the hard mask layer; and forming a plurality of device regions in the epitaxial layer.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a substrate, a buried layer arranged on the substrate, and an epitaxial layer arranged on the buried layer, the substrate having a first doping type, and the buried layer having a second doping type opposite to the first doping type; forming a hard mask layer on the top surface of the epitaxial layer; etching the hard mask layer and the semiconductor body using a soft mask layer to form a first trench and a third trench in the semiconductor body; stripping the soft mask layer from the top surface of the hard mask layer; depositing a conductive material layer to fill the first trench and the third trench; removing the conductive material layer in the first trench and retaining the conductive material layer in the third trench; etching to open the bottom of the first trench to form an opening; depositing a conductive material so that the conductive material fills at least the first trench; removing the conductive material on the hard mask layer; and forming a plurality of device regions in the epitaxial layer.

[0011] This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other purposes, features and advantages of the embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation, in which:

[0013] Figures 1A to 1Q A process for manufacturing a semiconductor device according to a first embodiment of the present disclosure is shown;

[0014] FIG. 2A to FIG. 2N shows a process for manufacturing a semiconductor device according to a third embodiment of the present disclosure;

[0015] FIG. 3A to FIG. 3N A process for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0016] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0017] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0018] Furthermore, the terms "top", "bottom", "above", "below", "over", "below", etc., as used herein, are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that embodiments of the present disclosure are capable of operation in other orientations than described or illustrated herein.

[0019] Embodiments of the present disclosure generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to semiconductor devices or integrated circuits having high-power devices and other devices such as logic and memory devices integrated on the same substrate. For example, the high-power device includes a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Other suitable high-power devices are also available. The high-power device can be used as a switching regulator for power management applications. Embodiments in the present disclosure provide various types of deep trench isolation (DTI) structures or regions that, together with a buried layer (e.g., an N+ buried layer (NBL)), effectively isolate the high-power device from other devices in the same IC.

[0020] For example, a plurality of groove openings can be formed in the hard mask layer by a first etching and a plurality of shallow grooves aligned with the plurality of groove openings can be formed. Subsequently, a thin protective layer is deposited in the plurality of groove openings and the plurality of shallow grooves and the thin protective layer is anisotropically etched to form sidewalls on the sidewalls of the plurality of groove openings and the plurality of shallow grooves. Afterwards, a second etching is performed on the semiconductor body. Due to the presence of the sidewalls, when the semiconductor body is subjected to the second etching, the portion of the semiconductor body directly below the sidewalls will not be etched away, thereby protecting the portion. However, the width of the portion formed by the second etching of the plurality of grooves is slightly narrower than the width of the corresponding groove openings, so it may not be possible to form uniform grooves that are closely aligned. Moreover, this method requires additional processes, which results in an increase in manufacturing costs.

[0021] The embodiments of the present disclosure can obtain a groove with uniform width through a single etching, and because only one etching is performed to form the groove, the process is simplified, thereby reducing the manufacturing cost.

[0022] Figures 1A to 1Q A process for manufacturing a semiconductor device according to a first embodiment of the present disclosure is shown.

[0023] like Figure 1A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. In some embodiments, the substrate 1 has a first doping type, such as p-type light doping or p-type heavy doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. In some embodiments, the substrate 1 has a first doping type; the buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, and being laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0024] like Figure 1A As shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; and depositing a nitride layer 42 on the first oxide layer 41. In other embodiments, the hard mask layer 4 may have other structures, for example, a structure in which a second oxide layer is further formed on the nitride layer 42. In some embodiments, the substrate 1, the buried layer 2, and the epitaxial layer 3 are formed of silicon material, the first oxide layer 41 is formed of silicon dioxide, and the nitride layer 42 is formed of silicon nitride.

[0025] like Figure 1B As shown, a single soft mask layer 10 can be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the second trench opening 520, and the width of the second trench opening 520 is greater than the width of the third trench opening 530. In some embodiments, the soft mask layer can be a photoresist.

[0026] Continue to refer to Figure 1B, the first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the second trench opening 520 and the width of the second trench opening 520 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the second trench 52, and the etching speed in the second trench 52 is greater than the etching speed in the third trench 53, so the first depth D1 of the first trench 51 is greater than the second depth D2 of the second trench 52, and the second depth D2 of the second trench 52 is greater than the third depth D3 of the third trench 53.

[0027] Before etching the trench opening and the trench, corresponding openings may also be etched on the soft mask layer 10, the first oxide layer 41 and the nitride layer 42 (hard mask layer 4). Optionally, in some embodiments, hot phosphoric acid may be used to etch the nitride layer 42 so that the opening of the nitride layer 42 is enlarged. This step makes the subsequent etching steps easier.

[0028] like Figure 1C As shown, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. Optionally, in some embodiments, before depositing undoped polysilicon, a thin layer of oxidation is performed on the inner sidewalls of the first trench 51, the second trench 52, and the third trench 53 to form a thin oxide layer 40 on the inner sidewalls of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, the thickness of the thin oxide layer formed on the inner sidewalls of each trench is 50-500 Å, preferably 100-300 Å, more preferably 150-250 Å, and most preferably 200 Å. By performing a thin layer of oxidation on the inner sidewalls of the trenches, damage on the sidewalls generated during the etching process can be repaired.

[0029] like Figure 1D As shown, optionally, in some embodiments, a thin oxide layer 40 formed on the inner sidewalls of the first trench 51, the second trench 52, and the third trench 53 is stripped. Through this stripping, damage generated on the sidewalls during the etching process can be removed. In other embodiments, the thin oxide layer may not be stripped in this step.

[0030] like Figure 1EAs shown, undoped polysilicon 80 is deposited so that undoped polysilicon 80 is formed on the sidewalls and bottom of the first trench 51, the second trench 52 and the third trench 53. In the manufacturing process of the semiconductor device, in order to carry out the subsequent process normally, it is necessary to protect the first oxide layer 41 from being over-etched. By depositing a thin thickness of undoped polysilicon, the effect of protecting the first oxide layer 41 and other layers with a simple one-time deposition process is achieved. Moreover, in a preferred embodiment, the materials of each layer of the semiconductor body 11 are silicon materials. The first oxide layer 41 is silicon dioxide. The nitride layer 42 is silicon nitride. The deposited undoped polysilicon is compatible with these materials, and this compatibility is beneficial to the performance of the semiconductor material. In some embodiments, a thin thickness of undoped polysilicon can be deposited. The deposition thickness of the thin thickness of undoped polysilicon can be 200-3000A, preferably 400-2000A, more preferably 600-1500A, and most preferably 800-1000A.

[0031] like Figure 1F As shown, a diffusion material 81 is deposited so that the diffusion material 81 is formed on the sidewalls and the bottom of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, a thin thickness of the diffusion material 81 is deposited. In some embodiments, the diffusion material 81 contains a dopant of a second doping type. In some embodiments, when the first doping type is p-type, the diffusion material 81 includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus. In some embodiments, when the first doping type is n-type, the diffusion material 81 includes borosilicate glass, and the dopant is boron. Other types of diffusion materials and other types of dopants are feasible. In some embodiments, the diffusion material 81 and the first oxide layer 41 both contain silicon dioxide, thereby improving the compatibility between the materials.

[0032] like Figure 1G As shown, optionally, the diffusion material 81 can be anisotropically etched to form a thin spacer. Through this step, a portion of the diffusion material 81 is etched away, so that the height of the diffusion material 81 is reduced to below the nitride layer 42, and the opening formed by the diffusion material 81 can be enlarged. Through this step, the subsequent etching step can be performed more easily.

[0033] In the subsequent step, a filling material is used to completely fill the third trench 53. The main purpose of this step is to completely fill the third trench 53 to facilitate the subsequent diffusion step.

[0034] In some embodiments, completely filling the third trench 53 with a filling material includes completely filling the third trench 53 with a diffusion material 81. That is, the filling material includes the diffusion material 81. Alternatively, the filling material may be the same diffusion material 81. In the case where the filling material is a diffusion material, such as Figure 1G The step of anisotropically etching the diffusion material 81 shown may be omitted, that is, depositing the diffusion material 81 and filling the diffusion material 81 may be performed in one step.

[0035] In some embodiments, completely filling the third trench 53 with the filling material includes completely filling the third trench 53 with the diffusion material 81 and the dielectric material 82. That is, the filling material includes the diffusion material 81 and the dielectric material 82. Figure 1H As shown, a dielectric material 82 of an appropriate thickness is deposited so that the dielectric material 82 completely fills the third trench 53, while the first trench 51 and the second trench 52 are only partially filled. In some embodiments, completely filling the third trench 53 with the diffusion material 81 and the dielectric material 82 includes partially filling the third trench 53 with the diffusion material 81, and continuing to fill the dielectric material 82 in the third trench 53 to seal the diffusion material 81.

[0036] In some embodiments, completely filling the third trench 53 includes forming an air gap in the third trench 53 .

[0037] In some embodiments, dielectric material 82 includes silicon oxide, undoped polysilicon, silicon nitride, etc. In some embodiments, dielectric material 82 includes undoped silica glass. For example, dielectric material 82 may include borosilicate glass. Other types of undoped silica glass are also feasible.

[0038] In the subsequent steps, etching is performed to enlarge the openings formed in the first trench 51 and the second trench 52. This step makes the subsequent etching steps easier. Fig. 1I As shown, for the embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82 , the dielectric material 82 is dry-etched so that the openings formed by the dielectric material 82 in the first trench 51 and the second trench 52 are enlarged.

[0039] In subsequent steps, the diffusion material 81 and the filling material are removed from the first trench 51 and the second trench 52. Figure 1JAs shown, for the embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82, the diffusion material 81 and the dielectric material 82 can be completely removed from the first trench 51 and the second trench 52 using diluted hydrofluoric acid. The top of the dielectric material 82 in the third trench 53 will also be removed by the diluted hydrofluoric acid. The thin layer of undoped polysilicon 80 protects the first oxide layer 41 from being etched by the diluted hydrofluoric acid. In other embodiments, a buffered oxide etchant can also be used instead of the diluted hydrofluoric acid.

[0040] like Figure 1J As shown, the diffusion material is thermally advanced to diffuse the second doping type dopant (e.g., phosphorus) in the diffusion material into the region of the epitaxial layer 3 near the sidewall of the third trench 53 to form the first doping region 83. In some embodiments, forming the first doping region 83 having the second doping type in the epitaxial layer 3 near the sidewall of the third trench 53 includes: depositing the diffusion material 81 (the diffusion material 81 includes the second doping type dopant) in the third trench 53; and thermally annealing the diffusion material 81 to diffuse the dopant into the region of the epitaxial layer 3 near the sidewall of the third trench 53 to form the first doping region 83.

[0041] The first doped region 83 is formed on both sides of the third trench 53 and extends from the top surface of the epitaxial layer 3 to the buried layer 2, so as to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. Since the first doped region 83 and the buried layer 2 have the same second doping type, they can be used as a pick-up structure of the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3 with a low resistivity. In addition, since the dopants in the buried layer 2 may also diffuse upward into the epitaxial layer 3 or diffuse downward into the substrate 1 during the thermal driving process. Therefore, the buried layer 2 can have a higher resistivity than the buried layer 2. Figure 1J The extension range shown in FIG. 1 is larger than that shown in FIG. 2 , for example, extending upward to a certain depth in the epitaxial layer 3 or extending downward to a certain depth in the substrate 1. In this case, in the previous step, the third trench 53 formed in the semiconductor body 11 may not extend into the buried layer 2 (of course, extending into the buried layer 2 is still feasible), but the bottom of the third trench 53 may be moved upward to Figure 1J The epitaxial layer 3 shown in FIG. 1 is located near the buried layer 2 (e.g., at a distance of Figure 1J The top surface of the buried layer 2 shown is in the range of several micrometers. During the thermal advancement, the buried layer 2 extends upward and contacts the first doped region 83. Therefore, with such an arrangement, the first doped region 83 can also reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3.

[0042] like Figure 1KAs shown, optionally, the diffusion material and the filling material in the third trench are completely removed. For example, for an embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82, the diffusion material 81 and the dielectric material 82 are completely removed from the third trench 53. In some embodiments, the diffusion material 81 and the filling material (such as the dielectric material 82) can be completely removed from the third trench 53 using a diluted hydrofluoric acid or buffered oxide etchant. The thin layer of undoped polysilicon 80 can protect the first oxide layer 41 from being etched by the diluted hydrofluoric acid or buffered oxide etchant. In other embodiments, the diffusion material 81 and the filling material (such as the dielectric material 82) may not be removed.

[0043] In some embodiments, the undoped polysilicon 80 is not removed. In other embodiments, the undoped polysilicon 80 in the first trench 51, the second trench 52, and the third trench 53 is optionally isotropically etched to completely remove the undoped polysilicon 80 from the trenches.

[0044] like Figure 1L As shown, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, the trench oxide layer 44 can be a thin oxide layer. In some embodiments, the thickness of the trench oxide layer 44 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000A. In some embodiments, the undoped polysilicon 80 can be completely oxidized (some single crystal silicon may remain) to form the trench oxide layer 44. In some embodiments, after the undoped polysilicon 80 is completely oxidized, a portion of the various layers of the semiconductor body 11 are also oxidized to obtain a thicker trench oxide layer 44. The above-mentioned step of forming the trench oxide layer can repair the damage to the trench sidewalls caused when the semiconductor body 11 is etched to form the first trench 51, the second trench 52, and the third trench 53.

[0045] Continue to refer to Figure 1L, in a subsequent step, a dielectric layer 8 is deposited so that a dielectric layer 8 is formed on the trench oxide layer 44 at the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, the dielectric layer 8 is deposited so that the dielectric layer 8 forms a second opening 54 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51 in the first trench 51, and the dielectric layer 8 completely fills the second trench 52 and the third trench 53. In some embodiments, an air gap may be formed in the dielectric layer 8 in the second trench 52, and an air gap may be formed in the dielectric layer 8 in the third trench 53. In some embodiments, the dielectric layer 8 may partially fill the second trench 52, which may reduce stress on the one hand and reduce parasitic capacitance on the other hand. In some embodiments, the dielectric layer 8 includes tetraethyl orthosilicate (TEOS). In other embodiments, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. The trench oxide layer 44 and the dielectric layer 8 in the first trench 51 form a first deep trench isolation structure 511, the trench oxide layer 44 and the dielectric layer 8 in the second trench 52 form a second deep trench isolation structure 521, and the trench oxide layer 44 and the dielectric layer 8 in the third trench 53 form a third deep trench isolation structure 531, which are used to isolate different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0046] like Figure 1M As shown, the dielectric layer 8 and the trench oxide layer 44 are anisotropically etched to remove the dielectric layer 8 from the top surface of the nitride layer 42, and the second opening 54 is extended to the bottom of the first trench 51, and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51.

[0047] like Figure 1N As shown, optionally, ion implantation (e.g., low energy, high dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has a first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before anisotropic etching of the dielectric layer 8 and the trench oxide layer 44. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 after forming the trench oxide layer 44 and before forming the dielectric layer 8. It is also feasible to form the second doped region 9 in other processes, for example, after thermally advancing the diffusion material 81 and before forming the trench oxide layer 44.

[0048] like Fig.1O As shown, in a subsequent step, a conductive material 84 is deposited so that the conductive material fills at least the first trench 51. In some embodiments, the conductive material 84 is deposited so that the conductive material 84 fills each trench and covers the top surface of the nitride layer 42. In some embodiments, the conductive material 84 includes polysilicon having a first doping type. Other types of conductive materials 84 are also feasible.

[0049] like Figure 1P As shown, the excess conductive material 84 can be removed by a chemical mechanical polishing (CMP) process, for example, the conductive material 84 on the hard mask layer 4 can be removed. Then, an etch-back process can be performed. In some embodiments, the chemical mechanical polishing process can be omitted and an etch-back process can be performed directly. The etch-back process can more effectively remove the excess conductive material 84. In some embodiments, a stripping step of the nitride layer can also be included.

[0050] like Figure 1Q As shown, multiple device regions may be formed in the epitaxial layer 3. For illustrative purposes, Figure 1Q The first device region 111 and the second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is only an exemplary structure, and any other structure different from this can be used.

[0051] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps, and a more robust undoped polysilicon thin layer can be achieved to prevent the first oxide layer from being etched during the etching process.

[0052] As Figures 1A to 1Q According to the variation of the first embodiment of the present disclosure shown, the process for manufacturing a semiconductor device according to the second embodiment of the present disclosure can omit the second trench. That is, Figures 1A to 1Q as well as Figures 1A to 1QThe reference numerals in the figure can still be used as a reference for the second embodiment according to the present disclosure, except that the second embodiment according to the present disclosure does not have the second groove and its related features. Therefore, the description of the second embodiment according to the present disclosure can still refer to Figures 1A to 1Q , and thus adopted Figures 1A to 1Q The reference numerals used in the embodiment are the same, except that there are no reference numerals related to the second groove according to the second embodiment of the present disclosure.

[0053] According to a second embodiment of the present disclosure, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. In some embodiments, the substrate 1 has a first doping type, such as p-type light doping or p-type heavy doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. The epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. In some embodiments, the substrate 1 has a first doping type; the buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0054] According to the second embodiment of the present disclosure, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; and depositing a nitride layer 42 on the first oxide layer 41. In other embodiments, the hard mask layer 4 may have other structures, for example, a structure in which a second oxide layer is further formed on the nitride layer 42. In some embodiments, the substrate 1, the buried layer 2, and the epitaxial layer 3 are formed of silicon material, the first oxide layer 41 is formed of silicon dioxide, and the nitride layer 42 is formed of silicon nitride.

[0055] According to the second embodiment of the present disclosure, a single soft mask layer 10 may be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the third trench opening 530. In some embodiments, the soft mask layer may be a photoresist.

[0056] The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the third trench 53, and thus the first depth D1 of the first trench 51 is greater than the third depth D3 of the third trench 53.

[0057] Before etching the trench opening and the trench, corresponding openings may also be etched on the soft mask layer 10, the first oxide layer 41 and the nitride layer 42 (hard mask layer 4). Optionally, in some embodiments, hot phosphoric acid may be used to etch the nitride layer 42 so that the opening of the nitride layer 42 is enlarged. This step makes the subsequent etching steps easier.

[0058] According to the second embodiment of the present disclosure, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. Optionally, in some embodiments, before depositing undoped polysilicon, a thin layer of oxidation is performed on the inner sidewalls of the first trench 51 and the third trench 53 to form a thin oxide layer 40 on the inner sidewalls of the first trench 51 and the third trench 53. In some embodiments, the thickness of the thin oxide layer formed on the inner sidewalls of each trench is 50-500 Å, preferably 100-300 Å, more preferably 150-250 Å, and most preferably 200 Å. By performing a thin layer of oxidation on the inner sidewalls of the trenches, damage on the sidewalls generated during etching can be repaired.

[0059] According to the second embodiment of the present disclosure, optionally, the thin oxide layer 40 formed on the inner sidewalls of the first trench 51 and the third trench 53 is stripped. Through this stripping, the damage generated on the sidewalls during the etching process can be removed. In other embodiments, the thin oxide layer may not be stripped in this step.

[0060] According to the second embodiment of the present disclosure, undoped polysilicon 80 is deposited so that undoped polysilicon 80 is formed on the sidewalls and bottom of the first trench 51 and the third trench 53. In the manufacturing process of the semiconductor device, in order to carry out the subsequent process normally, it is necessary to protect the first oxide layer 41 from being over-etched. By depositing a thin thickness of undoped polysilicon, the effect of protecting the first oxide layer 41 and other layers with a simple one-time deposition process is achieved. Moreover, in a preferred embodiment, the materials of each layer of the semiconductor body 11 are silicon materials. The first oxide layer 41 is silicon dioxide. The nitride layer 42 is silicon nitride. The deposited undoped polysilicon is compatible with these materials, and this compatibility is beneficial to the performance of the semiconductor material. In some embodiments, a thin thickness of undoped polysilicon can be deposited. The deposition thickness of the thin thickness of undoped polysilicon can be 200-3000A, preferably 400-2000A, more preferably 600-1500A, and most preferably 800-1000A.

[0061] According to a second embodiment of the present disclosure, a diffusion material 81 is deposited so that the diffusion material 81 is formed on the sidewalls and the bottom of the first trench 51 and the third trench 53. In some embodiments, a thin thickness of the diffusion material 81 is deposited. In some embodiments, the diffusion material 81 contains a dopant of a second doping type. In some embodiments, when the first doping type is p-type, the diffusion material 81 includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus. In some embodiments, when the first doping type is n-type, the diffusion material 81 includes borosilicate glass, and the dopant is boron. Other types of diffusion materials and other types of dopants are feasible. In some embodiments, the diffusion material 81 and the first oxide layer 41 both contain silicon dioxide, thereby improving the compatibility between the materials.

[0062] According to the second embodiment of the present disclosure, the diffusion material 81 may be anisotropically etched to form a thin spacer. Through this step, a portion of the diffusion material 81 is etched away, so that the height of the diffusion material 81 is reduced to below the nitride layer 42, and the opening formed by the diffusion material 81 can be enlarged. Through this step, the subsequent etching step can be performed more easily.

[0063] In the subsequent step, a filling material is used to completely fill the third trench 53. The main purpose of this step is to completely fill the third trench 53 to facilitate the subsequent diffusion step.

[0064] In some embodiments, completely filling the third trench 53 with a filling material includes completely filling the third trench 53 with a diffusion material 81. That is, the filling material includes the diffusion material 81. Alternatively, the filling material may be the same diffusion material 81. In the case where the filling material is the diffusion material, the step of anisotropically etching the diffusion material 81 may be omitted, that is, depositing the diffusion material 81 and filling the diffusion material 81 may be performed in one step.

[0065] In some embodiments, completely filling the third trench 53 with the filling material includes completely filling the third trench 53 with the diffusion material 81 and the dielectric material 82. That is, the filling material includes the diffusion material 81 and the dielectric material 82. The dielectric material 82 is deposited to an appropriate thickness so that the dielectric material 82 completely fills the third trench 53, while the first trench 51 is only partially filled. In some embodiments, completely filling the third trench 53 with the diffusion material 81 and the dielectric material 82 includes partially filling the third trench 53 with the diffusion material 81, and continuing to fill the dielectric material 82 in the third trench 53 to seal the diffusion material 81.

[0066] In some embodiments, completely filling the third trench 53 includes forming an air gap in the third trench 53 .

[0067] In some embodiments, dielectric material 82 includes silicon oxide, undoped polysilicon, silicon nitride, etc. In some embodiments, dielectric material 82 includes undoped silica glass. For example, dielectric material 82 may include borosilicate glass. Other types of undoped silica glass are also feasible.

[0068] In the subsequent steps, etching is performed to enlarge the opening formed in the first trench 51. Through this step, the subsequent etching steps can be performed more easily. For example, for an embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82, the dielectric material 82 is dry-etched to enlarge the opening formed by the dielectric material 82 in the first trench 51.

[0069] In a subsequent step, the diffusion material 81 and the filling material are removed from the first trench 51. For example, for an embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82, the diffusion material 81 and the dielectric material 82 can be completely removed from the first trench 51 using diluted hydrofluoric acid. The top of the dielectric material 82 in the third trench 53 will also be removed by the diluted hydrofluoric acid. The thin layer of undoped polysilicon 80 protects the first oxide layer 41 from being etched by the diluted hydrofluoric acid. In other embodiments, a buffered oxide etchant can also be used instead of the diluted hydrofluoric acid.

[0070] According to the second embodiment of the present disclosure, the diffusion material is thermally advanced so that the second doping type dopant (e.g., phosphorus) in the diffusion material is diffused into the region of the epitaxial layer 3 near the sidewall of the third trench 53 to form the first doping region 83. In some embodiments, forming the first doping region 83 having the second doping type in the epitaxial layer 3 near the sidewall of the third trench 53 includes: depositing the diffusion material 81 (the diffusion material 81 includes the second doping type dopant) in the third trench 53; and thermally annealing the diffusion material 81 so that the dopant diffuses into the region of the epitaxial layer 3 near the sidewall of the third trench 53 to form the first doping region 83.

[0071] The first doped region 83 is formed on both sides of the third trench 53 and extends from the top surface of the epitaxial layer 3 to the buried layer 2, so as to electrically connect the buried layer 2 to the top surface of the epitaxial layer 3. Since the first doped region 83 and the buried layer 2 have the same second doping type, they can be used as a pick-up structure of the buried layer 2, thereby connecting the buried layer 2 to the top surface of the epitaxial layer 3 with a low resistivity. In addition, since the dopants in the buried layer 2 may also diffuse upward into the epitaxial layer 3 or diffuse downward into the substrate 1 during the thermal driving process. Therefore, the buried layer 2 can have a higher resistivity than the buried layer 2. Figure 1J The extension range shown in FIG. 1 is larger than that shown in FIG. 2 , for example, extending upward to a certain depth in the epitaxial layer 3 or extending downward to a certain depth in the substrate 1. In this case, in the previous step, the third trench 53 formed in the semiconductor body 11 may not extend into the buried layer 2 (of course, extending into the buried layer 2 is still feasible), but the bottom of the third trench 53 may be moved upward to Figure 1J The epitaxial layer 3 shown in FIG. 1 is located near the buried layer 2 (e.g., at a distance of Figure 1J The top surface of the buried layer 2 shown is in the range of several micrometers. During the thermal advancement, the buried layer 2 extends upward and contacts the first doped region 83. Therefore, with such an arrangement, the first doped region 83 can also reliably electrically connect the buried layer 2 to the top surface of the epitaxial layer 3.

[0072] Optionally, the diffusion material and the filling material in the third trench are completely removed. For example, for an embodiment in which the third trench 53 is completely filled with the diffusion material 81 and the dielectric material 82, the diffusion material 81 and the dielectric material 82 are completely removed from the third trench 53. In some embodiments, the diffusion material 81 and the filling material (such as the dielectric material 82) can be completely removed from the third trench 53 using a diluted hydrofluoric acid or buffered oxide etchant. The thin layer of undoped polysilicon 80 can protect the first oxide layer 41 from being etched by the diluted hydrofluoric acid or buffered oxide etchant. In other embodiments, the diffusion material 81 and the filling material (such as the dielectric material 82) may not be removed.

[0073] In some embodiments, the undoped polysilicon 80 is not removed. In other embodiments, the undoped polysilicon 80 in the first trench 51 and the third trench 53 is optionally isotropically etched to completely remove the undoped polysilicon 80 from the trenches.

[0074] According to the second embodiment of the present disclosure, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51 and the third trench 53. In some embodiments, the trench oxide layer 44 may be a thin oxide layer. In some embodiments, the thickness of the trench oxide layer 44 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000A. In some embodiments, the undoped polysilicon 80 may be completely oxidized (some single crystal silicon may remain) to form the trench oxide layer 44. In some embodiments, after the undoped polysilicon 80 is completely oxidized, a portion of the various layers of the semiconductor body 11 are also oxidized to obtain a thicker trench oxide layer 44. The above-mentioned step of forming the trench oxide layer can repair the damage to the trench sidewalls caused when the semiconductor body 11 is etched to form the first trench 51 and the third trench 53.

[0075] In a subsequent step, a dielectric layer 8 is deposited so that a dielectric layer 8 is formed on the trench oxide layer 44 at the sidewalls and bottom of the first trench 51 and the third trench 53. In some embodiments, the dielectric layer 8 is deposited so that the dielectric layer 8 forms a first opening 54 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51 in the first trench 51, and the dielectric layer 8 completely fills the third trench 53. In some embodiments, an air gap may be formed in the dielectric layer 8 in the third trench 53. In some embodiments, the dielectric layer 8 includes tetraethyl orthosilicate (TEOS). In other embodiments, the dielectric layer 8 includes an oxide, such as silicon oxide. Other types of dielectric layers are also feasible. The trench oxide layer 44 and the dielectric layer 8 in the first trench 51 form a first deep trench isolation structure 511, and the trench oxide layer 44 and the dielectric layer 8 in the third trench 53 form a third deep trench isolation structure 531 for isolating different device regions to be formed in the epitaxial layer 3 in subsequent steps.

[0076] According to a second embodiment of the present disclosure, the dielectric layer 8 and the trench oxide layer 44 are anisotropically etched, the dielectric layer 8 is removed from the top surface of the nitride layer 42, and the second opening 54 is extended to the bottom of the first trench 51, and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51.

[0077] Optionally, ion implantation (e.g., low energy, high dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has the first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before anisotropic etching of the dielectric layer 8 and the trench oxide layer 44. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 after forming the trench oxide layer 44 and before forming the dielectric layer 8. It is also feasible to form the second doped region 9 in other processes, for example, after thermally driving the diffusion material 81 and before forming the trench oxide layer 44.

[0078] In a subsequent step, a conductive material 84 is deposited so that the conductive material fills at least the first trench 51. In some embodiments, the conductive material 84 is deposited so that the conductive material 84 fills each trench and covers the top surface of the nitride layer 42. In some embodiments, the conductive material 84 includes polysilicon having a first doping type. Other types of conductive materials 84 are also feasible.

[0079] Excess conductive material 84 may be removed by a chemical mechanical polishing (CMP) process, for example, conductive material 84 on hard mask layer 4 may be removed. Then an etch-back process may be performed. In some embodiments, the chemical mechanical polishing process may not be performed, but an etch-back process may be performed directly. The etch-back process may more effectively remove excess conductive material 84. In some embodiments, a stripping step of the nitride layer may also be included.

[0080] A plurality of device regions may be formed in the epitaxial layer 3. For illustrative purposes, a first device region 111 and a second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 may be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 may be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, may be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 may be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b may be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, may be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is merely an exemplary structure, and any other structure different from this may be used.

[0081] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps, and a more robust undoped polysilicon thin layer can be achieved to prevent the first oxide layer from being etched during the etching process.

[0082] FIG. 2A to FIG. 2N A process for manufacturing a semiconductor device according to a third embodiment of the present disclosure is shown.

[0083] like Figure 2A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. Figure 2A In the illustrated embodiment, the substrate 1 has a first doping type, such as lightly p-type doping or heavily p-type doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. And the epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0084] In addition, if Figure 2AAs shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures.

[0085] In some embodiments, Figure 2B As shown, a single soft mask layer 10 can be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the second trench opening 520, and the width of the second trench opening 520 is greater than the width of the third trench opening 530.

[0086] Continue to refer to Figure 2B , the first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the second trench opening 520 and the width of the second trench opening 520 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the second trench 52, and the etching speed in the second trench 52 is greater than the etching speed in the third trench 53, so the first depth D1 of the first trench 51 is greater than the second depth D2 of the second trench 52, and the second depth D2 of the second trench 52 is greater than the third depth D3 of the third trench 53.

[0087] like Figure 2C As shown, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. In some embodiments, optionally, before the subsequent steps, a thin layer of oxidation can be performed on the sidewalls of the trench to form a sacrificial oxide layer, and then the sacrificial oxide layer is removed. Through this step, some etching damage can be removed and the sidewalls of the deep trench can be smoother.

[0088] In some embodiments, an additional oxide wet etching and nitride expansion step may be optionally performed to expand the opening of the deep trench, so that the subsequent etching step can be performed more easily and can facilitate the subsequent polysilicon filling and etching steps.

[0089] like Figure 2C As shown, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, a thin layer oxidation step is performed on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53 to form the trench oxide layer 44. In some embodiments, tetraethyl orthosilicate (TEOS) is deposited on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53 to form the trench oxide layer 44. In some embodiments, the trench oxide layer 44 is a thin oxide layer with a thickness of 20-200 Å, preferably 30-160 Å, more preferably 40-120 Å, and most preferably 50-100 Å.

[0090] In other embodiments, alternatively, a thick trench oxide layer 44 may be formed, the thickness of which is 400-5000 Å, preferably 600-4000 Å, more preferably 800-3000 Å, and most preferably 1000-2000 Å. The thick trench oxide layer can reduce the thickness of the subsequent polysilicon deposition. As described above, before forming the thin trench oxide layer or the thick trench oxide layer, the steps of forming and removing the sacrificial oxide layer may be performed, or the steps of forming and removing the sacrificial oxide layer may not be performed.

[0091] like Figure 2C As shown, nitride deposition is performed on the semiconductor material to form a thin nitride layer 45. For example, the thin nitride layer 45 may be formed on the top of the second oxide layer 43, and the thin nitride layer 45 may be formed on the trench oxide layer 44 of the sidewalls of each trench, that is, formed on the inner side of the trench oxide layer 44. The thin nitride layer 42 may also be formed on the trench oxide layer 44 at the bottom of each trench. In some embodiments, the thickness of the formed thin nitride layer 45 is 20-500 Å, preferably 40-400 Å, more preferably 60-300 Å, and most preferably 100-200 Å.

[0092] In some embodiments, alternatively, a single oxide layer may be formed without forming a nitride layer. The so-called single oxide layer refers to only one oxide layer without other layers. In some embodiments, the thickness of the single oxide layer is 50-1500 Å, preferably 100-1000 Å, more preferably 200-800 Å, and most preferably 300-500 Å.

[0093] In some embodiments, an ONO structure of oxide layer-nitride layer-oxide layer may be optionally used. Specifically, a trench oxide layer is formed on the sidewall of the trench. A nitride layer is formed on the trench oxide layer. Another very thin oxide layer is formed on the nitride layer, for example, by performing wet oxidation on the passivated nitride surface to form the very thin oxide layer.

[0094] like Figure 2D As shown, the thin nitride layer and the trench oxide layer are anisotropically etched. This step completely removes the nitride layer and the oxide layer at the bottom of each trench. And this step also removes the nitride layer on the second oxide layer 43.

[0095] If in Figure 2C If only an oxide layer is formed in the step of forming the nitride layer but no nitride layer is formed (ie, a single oxide layer), the oxide layer is anisotropically etched to remove the oxide layer at the bottom of each trench.

[0096] The above steps can protect the first oxide layer 41 from corrosion in the subsequent steps. In addition, the etching step can also enlarge the openings of each groove. Through this step, the subsequent etching step can be carried out more easily.

[0097] like Figure 2E As shown, a conductive material layer 85 is deposited to fill the first trench 51, the second trench 52, and the third trench 53. In some embodiments, the conductive material layer 85 may be n-type doped polysilicon. For example, n-type doped polysilicon deposition is performed to form an n-type doped polysilicon layer to completely fill the third trench 53, while the first trench 51 and the second trench 52 are only partially filled. The conductive material layer 85 also covers the second oxide layer 43. In some embodiments, the thickness of the conductive material layer 85 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000-4500A.

[0098] If in Figure 2C In the step of forming the thick trench oxide layer 44, for example, the thickness of the thick trench oxide layer 44 is 400-5000A, preferably 600-4000A, more preferably 800-3000A, and most preferably 1000-2000A. Then the thickness of the conductive material layer 85 can be reduced, for example, the thickness of the conductive material layer 85 can be 800-6000A, preferably 1500-5000A, more preferably 2000-4000A, and most preferably 2500-3000A.

[0099] like Figure 2FAs shown, optionally, the opening of the first trench 51 and the opening of the second trench 52 can be expanded by dry etching, and the bottoms of the first trench 51 and the second trench 52 can be etched away. Preferably, the step of expanding the opening of the trench can also be completed by widening the hard mask (oxide layer and nitride layer) before the trench oxide layer and / or nitride layer is formed.

[0100] like Figure 2G As shown, the conductive material layer 85 is isotropically etched, for example, using wet etching or dry etching. For example, hydrofluoric acid, nitric acid and acetic acid can be used for wet etching. For example, sulfur hexafluoride, carbon tetrafluoride, xenon difluoride, etc. can be used for dry etching. By etching, the conductive material layer in the first trench 51 and the second trench 52 of the opening will be completely removed, and some overetching into the substrate (for example, silicon material) can be performed. At the same time, the conductive material layer 85 in the third trench 53 is retained. In some embodiments, the thin nitride layer in the first trench 51 and the second trench 52 can be used as an etching barrier to protect the sidewalls of the trench.

[0101] In some embodiments, ion implantation, such as low-energy, high-dose ion implantation, may be optionally performed at the bottom of the first trench 51 and the second trench 52. Such ion implantation will also be implanted into the top of the conductive material layer 85, but this portion of the conductive material layer 85 will be consumed in subsequent processes.

[0102] In some embodiments, a rapid thermal annealing process may be optionally used to seal polysilicon cracks formed near the surface of the third trench, the cracks being damage formed during etching.

[0103] like Figure 2H As shown, the thin nitride layer in the first trench 51 and the second trench 52 is removed. In some embodiments, the thin nitride layer 45 and the trench oxide layer 44 in the first trench 51 and the second trench 52 are removed. In some embodiments, if only an oxide layer is formed without a nitride layer (i.e., a single oxide layer), only the single oxide layer is removed.

[0104] In some embodiments, the trench oxide layer 44 in the first trench 51 and the second trench 52 is removed after the thin nitride layer 45 is removed.

[0105] In some embodiments, if a thick trench oxide layer (e.g., 1000-2000A) is formed in the previous step, there is no need to remove the thick trench oxide layer in this step, as this will reduce the required additional thin layer oxidation process and thereby minimize the loss of the conductive material layer in such a thin layer oxidation step.

[0106] The thin nitride layer in the third trench 53 will remain and serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon). If only an oxide layer is formed in the previous step without forming a nitride layer (i.e., the case of a single oxide layer), the single oxide layer is maintained to serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon).

[0107] like Fig.2I As shown, wet thin-layer oxidation is performed to form another oxide layer on the sidewalls of the first trench 51 and the second trench 52. Since the third trench 53 is completely filled with the conductive material layer 85, the wet thin-layer oxidation will not affect the sidewalls of the third trench 53.

[0108] In some embodiments, if a thick trench oxide layer is formed on the trenches in the previous step and is not removed, the oxidation process in this step can be reduced, which is beneficial for the management of mechanical stress (especially the mechanical stress at the bottom of the first trench and the second trench) because the conductive material layer can be oxidized faster, and the mechanical stress will likely slow down such oxidation.

[0109] In a subsequent step, a deposited oxide layer 86 is formed to fill the second trench 52, while the first trench 51 remains open. In some embodiments, the deposited oxide layer 86 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51. In some embodiments, the deposited oxide layer 86 can be a tetraethyl orthosilicate (TEOS) layer. For example, tetraethyl orthosilicate (TEOS) deposition is performed to form a tetraethyl orthosilicate layer, and the second trench 52 will be closed after this step, while the first trench remains open.

[0110] like Figure 2J As shown, the deposited oxide layer 86 and the trench oxide layer 44 are anisotropically etched to open the bottom of the first trench 51 to form an opening for substrate connection.

[0111] The second opening 54 is extended to the bottom of the first trench 51 , and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51 .

[0112] like Figure 2KAs shown, optionally, ion implantation (e.g., low energy, high dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has a first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed near the bottom of the first trench 51 in the substrate 1 before anisotropic etching of the deposited oxide layer 86 and the trench oxide layer 44 to form the second doped region 9. In addition, in some embodiments, ion implantation may be performed near the bottom of the first trench 51 in the substrate 1 after the trench oxide layer 44 is formed and before the deposited oxide layer 86 is formed to form the second doped region 9. It is also feasible to form the second doped region 9 in other processes.

[0113] During the above ion implantation process, the top portion of the conductive material layer (n-type doped polysilicon) in the third trench 53 will be converted to p-type by this implantation. The subsequent thermal step and n-type implantation will convert it back to n-type polysilicon. This step can also be done before the thin layer oxidation and TEOS deposition, which allows dopants to enter the bottom of the first trench and the second trench.

[0114] like Figure 2L As shown, the conductive material 84 is deposited so that the conductive material 84 fills the first trench 51 and the second trench 52 and covers the top surface of the second oxide layer 43. In some embodiments, the conductive material 84 includes polysilicon with a first doping type. Other types of conductive materials 84 are also feasible.

[0115] like Figure 2M As shown, the excess conductive material 84 can be removed by a chemical mechanical polishing (CMP) process, for example, the conductive material 84 on the hard mask layer 4 can be removed. Then, an etch-back process can be performed. In some embodiments, the chemical mechanical polishing process can be omitted and an etch-back process can be performed directly. The etch-back process can more effectively remove the excess conductive material 84. In some embodiments, a stripping step of the nitride layer can also be included.

[0116] like Figure 2N As shown, multiple device regions may be formed in the epitaxial layer 3. For illustrative purposes, Figure 2NThe first device region 111 and the second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is only an exemplary structure, and any other structure different from this can be used.

[0117] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps. Moreover, a pick-up structure to the buried layer is generated by filling the third trench rather than by diffusion, wherein the oxide layer and / or nitride layer acts as a diffusion barrier. In addition, by adding a second oxide layer, the channel connected to each deep trench is extended due to the heightening of the semiconductor material, so that the amount of n-type doped polysilicon in the trench can be greater, which not only prevents the trench from being etched through, but also improves the conductivity of the semiconductor material.

[0118] As FIG. 2A to FIG. 2N According to a variation of the third embodiment of the present disclosure shown, the process for manufacturing a semiconductor device according to the fourth embodiment of the present disclosure may omit the second trench. That is, FIG. 2A to FIG. 2N as well as FIG. 2A to FIG. 2N The reference numerals in the figure can still be used as a reference for the fourth embodiment according to the present disclosure, except that the fourth embodiment according to the present disclosure does not have the second groove and its related features. Therefore, the description of the fourth embodiment according to the present disclosure can still refer to FIG. 2A to FIG. 2N , and thus adopted FIG. 2A to FIG. 2N The same reference numerals are used in the embodiment except that there are no reference numerals associated with the second groove in the fourth embodiment according to the present disclosure.

[0119] According to a fourth embodiment of the present disclosure, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. In some embodiments, the substrate 1 has a first doping type, such as p-type light doping or p-type heavy doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. And the epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0120] According to the fourth embodiment of the present disclosure, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; depositing a nitride layer 42 on the first oxide layer 41; and depositing a second oxide layer 43 on the nitride layer 42. In other embodiments, the hard mask layer 4 may have other structures.

[0121] In some embodiments, a single soft mask layer 10 may be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the third trench opening 530.

[0122] The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the third trench 53, and thus the first depth D1 of the first trench 51 is greater than the third depth D3 of the third trench 53.

[0123] According to the fourth embodiment of the present disclosure, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. In some embodiments, optionally, before performing subsequent steps, a thin layer of oxidation can be performed on the sidewalls of the trench to form a sacrificial oxide layer, which is then removed. Through this step, some etching damage can be removed and the sidewalls of the deep trench can be made smoother.

[0124] In some embodiments, an additional oxide wet etching and nitride expansion step may be optionally performed to expand the opening of the deep trench, so that the subsequent etching step can be performed more easily and can facilitate the subsequent polysilicon filling and etching steps.

[0125] According to a fourth embodiment of the present disclosure, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51 and the third trench 53. In some embodiments, a thin layer oxidation step is performed on the sidewalls and bottom of the first trench 51 and the third trench 53 to form the trench oxide layer 44. In some embodiments, tetraethyl orthosilicate (TEOS) is deposited on the sidewalls and bottom of the first trench 51 and the third trench 53 to form the trench oxide layer 44. In some embodiments, the trench oxide layer 44 is a thin oxide layer having a thickness of 20-200 Å, preferably 30-160 Å, more preferably 40-120 Å, and most preferably 50-100 Å.

[0126] In other embodiments, alternatively, a thick trench oxide layer 44 may be formed, the thickness of which is 400-5000 Å, preferably 600-4000 Å, more preferably 800-3000 Å, and most preferably 1000-2000 Å. The thick trench oxide layer can reduce the thickness of the subsequent polysilicon deposition. As described above, before forming the thin trench oxide layer or the thick trench oxide layer, the steps of forming and removing the sacrificial oxide layer may be performed, or the steps of forming and removing the sacrificial oxide layer may not be performed.

[0127] According to the fourth embodiment of the present disclosure, nitride deposition is performed on the semiconductor material to form a thin nitride layer 45. For example, the thin nitride layer 45 may be formed on the top of the second oxide layer 43, and the thin nitride layer 45 may be formed on the trench oxide layer 44 of the sidewalls of each trench, that is, formed on the inner side of the trench oxide layer 44. The thin nitride layer 42 may also be formed on the trench oxide layer 44 at the bottom of each trench. In some embodiments, the thickness of the formed thin nitride layer 45 is 20-500A, preferably 40-400A, more preferably 60-300A, and most preferably 100-200A.

[0128] In some embodiments, alternatively, a single oxide layer may be formed without forming a nitride layer. The so-called single oxide layer refers to only one oxide layer without other layers. In some embodiments, the thickness of the single oxide layer is 50-1500 Å, preferably 100-1000 Å, more preferably 200-800 Å, and most preferably 300-500 Å.

[0129] In some embodiments, an ONO structure of oxide layer-nitride layer-oxide layer may be optionally used. Specifically, a trench oxide layer is formed on the sidewall of the trench. A nitride layer is formed on the trench oxide layer. Another very thin oxide layer is formed on the nitride layer, for example, by performing wet oxidation on the passivated nitride surface to form the very thin oxide layer.

[0130] According to the fourth embodiment of the present disclosure, the thin nitride layer and the trench oxide layer are anisotropically etched. This step completely removes the nitride layer and the oxide layer at the bottom of each trench. This step also removes the nitride layer on the second oxide layer 43.

[0131] If in Figure 2C If only an oxide layer is formed in the step of forming the nitride layer but no nitride layer is formed (ie, a single oxide layer), the oxide layer is anisotropically etched to remove the oxide layer at the bottom of each trench.

[0132] The above steps can protect the first oxide layer 41 from corrosion in the subsequent steps. In addition, the etching step can also enlarge the openings of each groove. Through this step, the subsequent etching step can be carried out more easily.

[0133] According to a fourth embodiment of the present disclosure, a conductive material layer 85 is deposited to fill the first trench 51 and the third trench 53. In some embodiments, the conductive material layer 85 may be n-type doped polysilicon. For example, n-type doped polysilicon is deposited to form an n-type doped polysilicon layer to completely fill the third trench 53, while the first trench 51 is only partially filled. The conductive material layer 85 also covers the second oxide layer 43. In some embodiments, the thickness of the conductive material layer 85 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000-4500A.

[0134] If in Figure 2CIn the step of forming the thick trench oxide layer 44, for example, the thickness of the thick trench oxide layer 44 is 400-5000A, preferably 600-4000A, more preferably 800-3000A, and most preferably 1000-2000A. Then the thickness of the conductive material layer 85 can be reduced, for example, the thickness of the conductive material layer 85 can be 800-6000A, preferably 1500-5000A, more preferably 2000-4000A, and most preferably 2500-3000A.

[0135] Optionally, the opening of the first trench 51 can be expanded by dry etching, and the bottom of the first trench 51 can be etched away. Preferably, the step of expanding the opening of the trench can also be completed by widening the hard mask (oxide layer and nitride layer) before the trench oxide layer and / or nitride layer is formed.

[0136] According to a fourth embodiment of the present disclosure, the conductive material layer 85 is isotropically etched, for example, using wet etching or dry etching. For example, hydrofluoric acid, nitric acid and acetic acid can be used for wet etching. For example, sulfur hexafluoride, carbon tetrafluoride, xenon difluoride, etc. can be used for dry etching. By etching, the conductive material layer in the first groove 51 of the opening will be completely removed, and some overetching into the substrate (for example, silicon material) can be performed. At the same time, the conductive material layer 85 in the third groove 53 is retained. In some embodiments, the thin nitride layer in the first groove 51 can be used as an etch barrier to protect the sidewalls of the groove.

[0137] In some embodiments, ion implantation, such as low-energy, high-dose ion implantation, may be optionally performed at the bottom of the first trench 51. Such ion implantation will also be implanted into the top of the conductive material layer 85, but this portion of the conductive material layer 85 will be consumed in subsequent processes.

[0138] In some embodiments, a rapid thermal annealing process may be optionally used to seal polysilicon cracks formed near the surface of the third trench, the cracks being damage formed during etching.

[0139] According to a fourth embodiment of the present disclosure, the thin nitride layer in the first trench 51 is removed. In some embodiments, the thin nitride layer 45 and the trench oxide layer 44 in the first trench 51 are removed. In some embodiments, if only an oxide layer is formed without a nitride layer (i.e., a single oxide layer), only the single oxide layer is removed.

[0140] In some embodiments, the trench oxide layer 44 in the first trench 51 is removed after the thin nitride layer 45 is removed.

[0141] In some embodiments, if a thick trench oxide layer (e.g., 1000-2000A) is formed in the previous step, there is no need to remove the thick trench oxide layer in this step, as this will reduce the required additional thin layer oxidation process and thereby minimize the loss of the conductive material layer in such a thin layer oxidation step.

[0142] The thin nitride layer in the third trench 53 will remain and serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon). If only an oxide layer is formed in the previous step without forming a nitride layer (i.e., the case of a single oxide layer), the single oxide layer is maintained to serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon).

[0143] According to the fourth embodiment of the present disclosure, wet thin-layer oxidation is performed to form another oxide layer on the sidewalls of the first trench 51. Since the third trench 53 is completely filled with the conductive material layer 85, the wet thin-layer oxidation will not affect the sidewalls of the third trench 53.

[0144] In some embodiments, if a thick trench oxide layer is formed on the trench in the previous step and is not removed, the oxidation process in this step can be reduced, which is beneficial for the management of mechanical stress (especially the mechanical stress at the bottom of the first trench) because the conductive material layer can be oxidized faster, while the mechanical stress will likely slow down such oxidation.

[0145] In a subsequent step, a deposited oxide layer 86 is formed. In some embodiments, the deposited oxide layer 86 forms a second opening 54 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51 in the first trench 51. In some embodiments, the deposited oxide layer 86 can be a tetraethyl orthosilicate (TEOS) layer. For example, tetraethyl orthosilicate (TEOS) deposition is performed to form a tetraethyl orthosilicate layer, and the first trench remains open.

[0146] According to the fourth embodiment of the present disclosure, anisotropic oxide etching is performed on the deposited oxide layer 86 and the trench oxide layer 44 to open the bottom of the first trench 51 to form an opening for substrate connection.

[0147] The second opening 54 is extended to the bottom of the first trench 51 , and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51 .

[0148] According to the fourth embodiment of the present disclosure, optionally, ion implantation (e.g., low-energy, high-dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doping region 9 in the substrate 1 near the bottom of the first trench 51. The second doping region 9 has a first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doping region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doping region 9 before anisotropic etching of the deposited oxide layer 86 and the trench oxide layer 44. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doping region 9 after forming the trench oxide layer 44 and before forming the deposited oxide layer 86. It is also feasible to form the second doping region 9 in other processes.

[0149] During the above ion implantation process, the top portion of the conductive material layer (n-type doped polysilicon) in the third trench 53 will be converted to p-type by this implantation. The subsequent thermal step and n-type implantation will convert it back to n-type polysilicon. This step can also be done before the thin layer oxidation and TEOS deposition, which allows dopants to enter the bottom of the first trench.

[0150] According to the fourth embodiment of the present disclosure, the conductive material 84 is deposited so that the conductive material 84 fills the first trench 51 and covers the top surface of the second oxide layer 43. In some embodiments, the conductive material 84 includes polysilicon having a first doping type. Other types of conductive materials 84 are also feasible.

[0151] According to a fourth embodiment of the present disclosure, the excess conductive material 84 may be removed by a chemical mechanical polishing (CMP) process, for example, the conductive material 84 on the hard mask layer 4 may be removed. Then, an etch-back process may be performed. In some embodiments, the chemical mechanical polishing process may not be performed, and an etch-back process may be performed directly. The etch-back process may more effectively remove the excess conductive material 84. In some embodiments, a stripping step of the nitride layer may also be included.

[0152] According to the fourth embodiment of the present disclosure, a plurality of device regions may be formed in the epitaxial layer 3. For illustrative purposes, Figure 2NThe first device region 111 and the second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is only an exemplary structure, and any other structure different from this can be used.

[0153] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps. Moreover, a pick-up structure to the buried layer is generated by filling the third trench rather than by diffusion, wherein the oxide layer and / or nitride layer acts as a diffusion barrier. In addition, by adding a second oxide layer, the channel connected to each deep trench is extended due to the heightening of the semiconductor material, so that the amount of n-type doped polysilicon in the trench can be greater, which not only prevents the trench from being etched through, but also improves the conductivity of the semiconductor material.

[0154] FIG. 3A to FIG. 3N A process for manufacturing a semiconductor device according to a fifth embodiment of the present disclosure is shown.

[0155] like Figure 3A As shown, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. Figure 3A In the illustrated embodiment, the substrate 1 has a first doping type, such as lightly p-type doping or heavily p-type doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. And the epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0156] In addition, if Figure 3A As shown, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; and depositing a nitride layer 42 on the first oxide layer 41. In other embodiments, the hard mask layer 4 may have other structures.

[0157] In some embodiments, Figure 3B As shown, a single soft mask layer 10 can be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510, a second trench opening 520, and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510, a second trench 52 aligned with the second trench opening 520, and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the second trench opening 520, and the width of the second trench opening 520 is greater than the width of the third trench opening 530.

[0158] like Figure 3B As shown, the first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The second trench 52 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a second depth D2. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the second trench opening 520 and the width of the second trench opening 520 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the second trench 52, and the etching speed in the second trench 52 is greater than the etching speed in the third trench 53, so the first depth D1 of the first trench 51 is greater than the second depth D2 of the second trench 52, and the second depth D2 of the second trench 52 is greater than the third depth D3 of the third trench 53.

[0159] like Figure 3C As shown, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. In some embodiments, optionally, before the subsequent steps, a thin layer of oxidation can be performed on the sidewalls of the trench to form a sacrificial oxide layer, and then the sacrificial oxide layer is removed. Through this step, some etching damage can be removed and the sidewalls of the deep trench can be smoother.

[0160] In some embodiments, an additional oxide wet etching and nitride expansion step may be optionally performed to enlarge the opening of the trench, so that the subsequent etching step can be performed more easily and can facilitate the subsequent polysilicon filling and etching steps.

[0161] like Figure 3C As shown, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53. In some embodiments, a thin layer oxidation step is performed on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53 to form the trench oxide layer 44. In some embodiments, tetraethyl orthosilicate (TEOS) is deposited on the sidewalls and bottom of the first trench 51, the second trench 52, and the third trench 53 to form the trench oxide layer 44. In some embodiments, the trench oxide layer 44 is a thin oxide layer with a thickness of 20-200 Å, preferably 30-160 Å, more preferably 40-120 Å, and most preferably 50-100 Å.

[0162] In other embodiments, alternatively, a thick trench oxide layer 44 may be formed, the thickness of which is 400-5000 Å, preferably 600-4000 Å, more preferably 800-3000 Å, and most preferably 1000-2000 Å. The thick trench oxide layer can reduce the thickness of the subsequent polysilicon deposition. As described above, before forming the thin trench oxide layer or the thick trench oxide layer, the steps of forming and removing the sacrificial oxide layer may be performed, or the steps of forming and removing the sacrificial oxide layer may not be performed.

[0163] like Figure 3C As shown, nitride deposition is performed on the semiconductor material to form a thin nitride layer 45. For example, the thin nitride layer 45 can be formed on the trench oxide layer 44. In some embodiments, the thickness of the formed thin nitride layer 45 is 20-500 Å, preferably 40-400 Å, more preferably 60-300 Å, and most preferably 100-200 Å.

[0164] In some embodiments, alternatively, a single oxide layer may be formed without forming a nitride layer. The so-called single oxide layer refers to only one oxide layer without other layers. In some embodiments, the thickness of the single oxide layer is 50-1500 Å, preferably 100-1000 Å, more preferably 200-800 Å, and most preferably 300-500 Å.

[0165] In some embodiments, an ONO structure of oxide layer-nitride layer-oxide layer may be optionally used. Specifically, a trench oxide layer is formed on the sidewall of the trench. A nitride layer is formed on the trench oxide layer. Another very thin oxide layer is formed on the nitride layer, for example, by performing wet oxidation on the passivated nitride surface to form the very thin oxide layer.

[0166] like Figure 3DAs shown, the thin nitride layer and the trench oxide layer are anisotropically etched. This step completely removes the nitride layer and the oxide layer at the bottom of each trench. And this step also removes the nitride layer on the hard mask.

[0167] If in Figure 3C If only an oxide layer is formed in the step of forming the nitride layer but no nitride layer is formed (ie, a single oxide layer), the oxide layer is anisotropically etched to remove the oxide layer at the bottom of each trench.

[0168] The above steps can protect the first oxide layer 41 from corrosion in the subsequent steps. In addition, the etching step can also enlarge the openings of each groove. Through this step, the subsequent etching step can be carried out more easily.

[0169] like Figure 3E As shown, a conductive material layer 85 is deposited to fill the first trench 51, the second trench 52, and the third trench 53. In some embodiments, the conductive material layer 85 may be n-type doped polysilicon. For example, n-type doped polysilicon deposition is performed to form an n-type doped polysilicon layer to completely fill the third trench 53, while the first trench 51 and the second trench 52 are only partially filled. The conductive material layer 85 also covers the hard mask 4. In some embodiments, the thickness of the conductive material layer 85 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000-4500A.

[0170] If in Figure 3C In the step of forming the thick trench oxide layer 44, for example, the thickness of the thick trench oxide layer 44 is 400-5000A, preferably 600-4000A, more preferably 800-3000A, and most preferably 1000-2000A. Then the thickness of the conductive material layer 85 can be reduced, for example, the thickness of the conductive material layer 85 can be 800-6000A, preferably 1500-5000A, more preferably 2000-4000A, and most preferably 2500-3000A.

[0171] like Figure 3F As shown, optionally, the opening of the first trench 51 and the opening of the second trench 52 can be expanded by dry etching, and the bottoms of the first trench 51 and the second trench 52 can be etched away. Preferably, the step of expanding the opening of the trench can also be completed by widening the hard mask (oxide layer and nitride layer) before the trench oxide layer and / or nitride layer is formed.

[0172] like Figure 3GAs shown, the conductive material layer 85 is isotropically etched, for example, using wet etching or dry etching. For example, hydrofluoric acid, nitric acid and acetic acid can be used for wet etching. For example, sulfur hexafluoride, carbon tetrafluoride, xenon difluoride, etc. can be used for dry etching. By etching, the conductive material layer in the first trench 51 and the second trench 52 of the opening will be completely removed, and some overetching into the substrate (for example, silicon material) can be performed. At the same time, the conductive material layer 85 in the third trench 53 is retained. In some embodiments, the thin nitride layer in the first trench 51 and the second trench 52 can be used as an etching barrier to protect the sidewalls of the trench.

[0173] In some embodiments, ion implantation, such as low-energy, high-dose ion implantation, may be optionally performed at the bottom of the first trench 51 and the second trench 52. Such ion implantation will also be implanted into the top of the conductive material layer 85, but this portion of the conductive material layer 85 will be consumed in subsequent processes.

[0174] In some embodiments, a rapid thermal annealing process may be optionally used to seal polysilicon cracks formed near the surface of the third trench, the cracks being damage formed during etching.

[0175] like Figure 3H As shown, the thin nitride layer in the first trench 51 and the second trench 52 is removed. In some embodiments, the thin nitride layer 45 and the trench oxide layer 44 in the first trench 51 and the second trench 52 are removed. In some embodiments, if only an oxide layer is formed without a nitride layer (i.e., a single oxide layer), only the single oxide layer is removed.

[0176] In some embodiments, the trench oxide layer 44 in the first trench 51 and the second trench 52 is removed after the thin nitride layer 45 is removed.

[0177] In some embodiments, if a thick trench oxide layer (e.g., 1000-2000A) is formed in the previous step, there is no need to remove the thick trench oxide layer in this step, as this will reduce the required additional thin layer oxidation process and thereby minimize the loss of the conductive material layer in such a thin layer oxidation step.

[0178] The thin nitride layer in the third trench 53 will remain and serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon). If only an oxide layer is formed in the previous step without forming a nitride layer (i.e., the case of a single oxide layer), the single oxide layer is maintained to serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon).

[0179] like Fig. 3IAs shown, wet thin-layer oxidation is performed to form another oxide layer on the sidewalls of the first trench 51 and the second trench 52. Since the third trench 53 is completely filled with the conductive material layer 85, the wet thin-layer oxidation will not affect the sidewalls of the third trench 53.

[0180] In some embodiments, if a thick trench oxide layer is formed on the trenches in the previous step and is not removed, the oxidation process in this step can be reduced, which is beneficial for the management of mechanical stress (especially the mechanical stress at the bottom of the first trench and the second trench) because the conductive material layer can be oxidized faster, and the mechanical stress will likely slow down such oxidation.

[0181] In a subsequent step, a deposited oxide layer 86 is formed to fill the second trench 52, while the first trench 51 remains open. In some embodiments, the deposited oxide layer 86 forms a second opening 54 in the first trench 51 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51. In some embodiments, the deposited oxide layer 86 can be a tetraethyl orthosilicate (TEOS) layer. For example, tetraethyl orthosilicate (TEOS) deposition is performed to form a tetraethyl orthosilicate layer, and the second trench 52 will be closed after this step, while the first trench remains open.

[0182] like Figure 3J As shown, the deposited oxide layer 86 and the trench oxide layer 44 are anisotropically etched to open the bottom of the first trench 51 to form an opening for substrate connection.

[0183] The second opening 54 is extended to the bottom of the first trench 51 , and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51 .

[0184] like Figure 3K As shown, optionally, ion implantation (e.g., low energy, high dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has a first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed near the bottom of the first trench 51 in the substrate 1 before anisotropic etching of the deposited oxide layer 86 and the trench oxide layer 44 to form the second doped region 9. In addition, in some embodiments, ion implantation may be performed near the bottom of the first trench 51 in the substrate 1 after the trench oxide layer 44 is formed and before the deposited oxide layer 86 is formed to form the second doped region 9. It is also feasible to form the second doped region 9 in other processes.

[0185] During the above ion implantation process, the top portion of the conductive material layer (n-type doped polysilicon) in the third trench 53 will be converted to p-type by this implantation. The subsequent thermal step and n-type implantation will convert it back to n-type polysilicon. This step can also be done before the thin layer oxidation and TEOS deposition, which allows dopants to enter the bottom of the first trench and the second trench.

[0186] like Figure 3L As shown, the conductive material 84 is deposited so that the conductive material 84 fills the first trench 51 and the second trench 52 and covers the top surface of the hard mask 4. In some embodiments, the conductive material 84 includes polysilicon with a first doping type. Other types of conductive materials 84 are also feasible.

[0187] like Figure 3M As shown, the excess conductive material 84 can be removed by a chemical mechanical polishing (CMP) process, for example, the conductive material 84 on the hard mask layer 4 can be removed. Then, an etch-back process can be performed. In some embodiments, the chemical mechanical polishing process can be omitted and an etch-back process can be performed directly. The etch-back process can more effectively remove the excess conductive material 84. In some embodiments, a stripping step of the nitride layer can also be included.

[0188] like Figure 3N As shown, multiple device regions may be formed in the epitaxial layer 3. For illustrative purposes, Figure 3N The first device region 111 and the second device region 112 are shown in the epitaxial layer 3 shown in . For example, the first device region 111 can be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 can be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, can be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 can be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b can be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, can be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is only an exemplary structure, and any other structure different from this can be used.

[0189] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps. In addition, a pick-up structure to the buried layer is generated by filling the third trench rather than by diffusion, wherein the oxide layer and / or nitride layer acts as a diffusion barrier.

[0190] As FIG. 3A to FIG. 3NAccording to a variation of the fifth embodiment of the present disclosure shown, the process for manufacturing a semiconductor device according to the sixth embodiment of the present disclosure may omit the second trench. That is, FIG. 3A to FIG. 3N as well as FIG. 3A to FIG. 3N The reference numerals in the figure can still be used as a reference for the sixth embodiment according to the present disclosure, except that the sixth embodiment according to the present disclosure does not have the second groove and its related features. Therefore, the description of the sixth embodiment according to the present disclosure can still refer to FIG. 3A to FIG. 3N , and thus adopted FIG. 3A to FIG. 3N The same reference numerals are used in the embodiment except that there are no reference numerals associated with the second groove in the sixth embodiment according to the present disclosure.

[0191] According to a sixth embodiment of the present disclosure, a semiconductor body 11 is provided. The semiconductor body 11 includes a substrate 1, a buried layer 2 disposed on the substrate 1, and an epitaxial layer 3 disposed on the buried layer 2. In some embodiments, the substrate 1 has a first doping type, such as p-type light doping or p-type heavy doping. The buried layer 2 can be formed on the substrate 1 by epitaxial growth. And the epitaxial layer 3 can be formed on the buried layer 2 by epitaxial growth. The substrate 1 has a first doping type. The buried layer 2 has a second doping type opposite to the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. In some embodiments, the buried layer 2 may have a blanket structure having substantially the same horizontal extension as the substrate 1, laid flat on the substrate 1. In other embodiments, the buried layer 2 may have a patterned structure. The epitaxial layer 3 may be used to form different device regions.

[0192] According to the sixth embodiment of the present disclosure, a hard mask layer 4 is formed on the top surface of the epitaxial layer 3. Forming the hard mask layer 4 may include: growing a first oxide layer 41 on the top surface of the epitaxial layer 3; and depositing a nitride layer 42 on the first oxide layer 41. In other embodiments, the hard mask layer 4 may have other structures.

[0193] In some embodiments, a single soft mask layer 10 may be used to perform a single etching on the hard mask layer 4 and the semiconductor body 11 to simultaneously form a first trench opening 510 and a third trench opening 530 penetrating the hard mask layer 4 in the hard mask layer 4, and simultaneously form a first trench 51 aligned with the first trench opening 510 and a third trench 53 aligned with the third trench opening 530 in the semiconductor body 11. In some embodiments, the width of the first trench opening 510 is greater than the width of the third trench opening 530.

[0194] The first trench 51 extends from the top surface of the epitaxial layer 3 into the substrate 1 and has a first depth D1. The third trench 53 extends from the top surface of the epitaxial layer 3 into the buried layer 2 and has a third depth D3. Since the width of the first trench opening 510 is greater than the width of the third trench opening 530, the etching speed in the first trench 51 is greater than the etching speed in the third trench 53, and thus the first depth D1 of the first trench 51 is greater than the third depth D3 of the third trench 53.

[0195] According to the sixth embodiment of the present disclosure, a single soft mask layer 10 is stripped from the top surface of the hard mask layer 4. In some embodiments, optionally, before performing subsequent steps, a thin layer of oxidation can be performed on the sidewalls of the trench to form a sacrificial oxide layer, which is then removed. Through this step, some etching damage can be removed and the sidewalls of the deep trench can be made smoother.

[0196] In some embodiments, an additional oxide wet etching and nitride expansion step may be optionally performed to expand the opening of the deep trench, so that the subsequent etching step can be performed more easily and can facilitate the subsequent polysilicon filling and etching steps.

[0197] According to the sixth embodiment of the present disclosure, a trench oxide layer 44 is formed on the sidewalls and bottom of the first trench 51 and the third trench 53. In some embodiments, a thin layer oxidation step is performed on the sidewalls and bottom of the first trench 51 and the third trench 53 to form the trench oxide layer 44. In some embodiments, tetraethyl orthosilicate (TEOS) is deposited on the sidewalls and bottom of the first trench 51 and the third trench 53 to form the trench oxide layer 44. In some embodiments, the trench oxide layer 44 is a thin oxide layer with a thickness of 20-200 Å, preferably 30-160 Å, more preferably 40-120 Å, and most preferably 50-100 Å.

[0198] In other embodiments, alternatively, a thick trench oxide layer 44 may be formed, the thickness of which is 400-5000 Å, preferably 600-4000 Å, more preferably 800-3000 Å, and most preferably 1000-2000 Å. The thick trench oxide layer can reduce the thickness of the subsequent polysilicon deposition. As described above, before forming the thin trench oxide layer or the thick trench oxide layer, the steps of forming and removing the sacrificial oxide layer may be performed, or the steps of forming and removing the sacrificial oxide layer may not be performed.

[0199] According to the sixth embodiment of the present disclosure, nitride deposition is performed on the semiconductor material to form a thin nitride layer 45. For example, the thin nitride layer 45 can be formed on the trench oxide layer 44. In some embodiments, the thickness of the formed thin nitride layer 45 is 20-500 Å, preferably 40-400 Å, more preferably 60-300 Å, and most preferably 100-200 Å.

[0200] In some embodiments, alternatively, a single oxide layer may be formed without forming a nitride layer. The so-called single oxide layer refers to only one oxide layer without other layers. In some embodiments, the thickness of the single oxide layer is 50-1500 Å, preferably 100-1000 Å, more preferably 200-800 Å, and most preferably 300-500 Å.

[0201] In some embodiments, an ONO structure of oxide layer-nitride layer-oxide layer may be optionally used. Specifically, a trench oxide layer is formed on the sidewall of the trench. A nitride layer is formed on the trench oxide layer. Another very thin oxide layer is formed on the nitride layer, for example, by performing wet oxidation on the passivated nitride surface to form the very thin oxide layer.

[0202] According to the sixth embodiment of the present disclosure, the thin nitride layer and the trench oxide layer are anisotropically etched. This step completely removes the nitride layer and the oxide layer at the bottom of each trench. This step also removes the nitride layer on the hard mask layer.

[0203] If in Figure 3C If only an oxide layer is formed in the step of forming the nitride layer but no nitride layer is formed (ie, a single oxide layer), the oxide layer is anisotropically etched to remove the oxide layer at the bottom of each trench.

[0204] The above steps can protect the first oxide layer 41 from corrosion in the subsequent steps. In addition, the etching step can also enlarge the openings of each groove. Through this step, the subsequent etching step can be carried out more easily.

[0205] According to the sixth embodiment of the present disclosure, a conductive material layer 85 is deposited to fill the first trench 51 and the third trench 53. In some embodiments, the conductive material layer 85 may be n-type doped polysilicon. For example, n-type doped polysilicon is deposited to form an n-type doped polysilicon layer to completely fill the third trench 53, while the first trench 51 is only partially filled. The conductive material layer 85 also covers the hard mask layer 4. In some embodiments, the thickness of the conductive material layer 85 is 1000-8000A, preferably 2000-6000A, more preferably 3000-5000A, and most preferably 4000-4500A.

[0206] If in Figure 3C In the step of forming the thick trench oxide layer 44, for example, the thickness of the thick trench oxide layer 44 is 400-5000A, preferably 600-4000A, more preferably 800-3000A, and most preferably 1000-2000A. Then the thickness of the conductive material layer 85 can be reduced, for example, the thickness of the conductive material layer 85 can be 800-6000A, preferably 1500-5000A, more preferably 2000-4000A, and most preferably 2500-3000A.

[0207] Optionally, the opening of the first trench 51 can be expanded by dry etching, and the bottom of the first trench 51 can be etched away. Preferably, the step of expanding the opening of the trench can also be completed by widening the hard mask (oxide layer and nitride layer) before the trench oxide layer and / or nitride layer is formed.

[0208] According to a sixth embodiment of the present disclosure, the conductive material layer 85 is isotropically etched, for example, using wet etching or dry etching. For example, hydrofluoric acid, nitric acid and acetic acid can be used for wet etching. For example, sulfur hexafluoride, carbon tetrafluoride, xenon difluoride, etc. can be used for dry etching. By etching, the conductive material layer in the first groove 51 of the opening will be completely removed, and some overetching into the substrate (for example, silicon material) can be performed. At the same time, the conductive material layer 85 in the third groove 53 is retained. In some embodiments, the thin nitride layer in the first groove 51 can be used as an etching barrier to protect the sidewalls of the groove.

[0209] In some embodiments, ion implantation, such as low-energy, high-dose ion implantation, may be optionally performed at the bottom of the first trench 51. Such ion implantation will also be implanted into the top of the conductive material layer 85, but this portion of the conductive material layer 85 will be consumed in subsequent processes.

[0210] In some embodiments, a rapid thermal annealing process may be optionally used to seal polysilicon cracks formed near the surface of the third trench, the cracks being damage formed during etching.

[0211] According to a sixth embodiment of the present disclosure, the thin nitride layer in the first trench 51 is removed. In some embodiments, the thin nitride layer 45 and the trench oxide layer 44 in the first trench 51 are removed. In some embodiments, if only an oxide layer is formed without a nitride layer (i.e., a single oxide layer), only the single oxide layer is removed.

[0212] In some embodiments, the trench oxide layer 44 in the first trench 51 is removed after the thin nitride layer 45 is removed.

[0213] In some embodiments, if a thick trench oxide layer (e.g., 1000-2000A) is formed in the previous step, there is no need to remove the thick trench oxide layer in this step, as this will reduce the required additional thin layer oxidation process and thereby minimize the loss of the conductive material layer in such a thin layer oxidation step.

[0214] The thin nitride layer in the third trench 53 will remain and serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon). If only an oxide layer is formed in the previous step without forming a nitride layer (i.e., the case of a single oxide layer), the single oxide layer is maintained to serve as a diffusion barrier to limit the outdiffusion of n-type doping from the conductive material layer (e.g., n-type doped polysilicon).

[0215] According to the sixth embodiment of the present disclosure, wet thin-layer oxidation is performed to form another oxide layer on the sidewalls of the first trench 51. Since the third trench 53 is completely filled with the conductive material layer 85, the wet thin-layer oxidation will not affect the sidewalls of the third trench 53.

[0216] In some embodiments, if a thick trench oxide layer is formed on the trench in the previous step and is not removed, the oxidation process in this step can be reduced, which is beneficial for the management of mechanical stress (especially the mechanical stress at the bottom of the first trench) because the conductive material layer can be oxidized faster, while the mechanical stress will likely slow down such oxidation.

[0217] In a subsequent step, a deposited oxide layer 86 is formed. In some embodiments, the deposited oxide layer 86 forms a second opening 54 extending from the top surface of the epitaxial layer 3 toward the bottom of the first trench 51 in the first trench 51. In some embodiments, the deposited oxide layer 86 can be a tetraethyl orthosilicate (TEOS) layer. For example, tetraethyl orthosilicate (TEOS) deposition is performed to form a tetraethyl orthosilicate layer, and the first trench remains open.

[0218] According to the sixth embodiment of the present disclosure, anisotropic oxide etching is performed on the deposited oxide layer 86 and the trench oxide layer 44 to open the bottom of the first trench 51 to form an opening for substrate connection.

[0219] The second opening 54 is extended to the bottom of the first trench 51 , and a first opening 71 aligned with the second opening 54 is formed at the bottom of the first trench 51 .

[0220] According to the sixth embodiment of the present disclosure, optionally, ion implantation (e.g., low-energy, high-dose ion implantation) may be performed on the substrate 1 through the second opening 54 and the first opening 71 to form a second doped region 9 in the substrate 1 near the bottom of the first trench 51. The second doped region 9 has a first doping type and has a higher doping concentration than the substrate 1. In the case where the doping concentration of the substrate 1 is relatively high, the second doped region 9 may be omitted. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 before anisotropic etching of the deposited oxide layer 86 and the trench oxide layer 44. In addition, in some embodiments, ion implantation may be performed in the substrate 1 near the bottom of the first trench 51 to form the second doped region 9 after the trench oxide layer 44 is formed and before the deposited oxide layer 86 is formed. It is also feasible to form the second doped region 9 in other processes.

[0221] During the above ion implantation process, the top portion of the conductive material layer (n-type doped polysilicon) in the third trench 53 will be converted to p-type by this implantation. The subsequent thermal step and n-type implantation will convert it back to n-type polysilicon. This step can also be done before the thin layer oxidation and TEOS deposition, which allows dopants to enter the bottom of the first trench.

[0222] According to the sixth embodiment of the present disclosure, the conductive material 84 is deposited so that the conductive material 84 fills the first trench 51 and covers the top surface of the hard mask layer 4. In some embodiments, the conductive material 84 includes polysilicon having a first doping type. Other types of conductive materials 84 are also feasible.

[0223] According to the sixth embodiment of the present disclosure, the excess conductive material 84 can be removed by a chemical mechanical polishing (CMP) process, for example, the conductive material 84 on the hard mask layer 4 can be removed. Then, an etch-back process can be performed. In some embodiments, the chemical mechanical polishing process can be omitted and an etch-back process can be performed directly. The etch-back process can more effectively remove the excess conductive material 84. In some embodiments, a stripping step of the nitride layer can also be included.

[0224] According to a fourth embodiment of the present disclosure, a plurality of device regions may be formed in the epitaxial layer 3. For illustrative purposes, a first device region 111 and a second device region 112 are shown in the epitaxial layer 3. For example, the first device region 111 may be a HV device region of a high voltage (HV) device (e.g., an HV transistor). In some embodiments, an LDMOS transistor 140 may be formed in the first device region 111, and a plurality of isolation regions 91, such as STI regions, may be formed in the first device region 111 to isolate different doped regions in the epitaxial layer 3. The second device region 112 may be used as a low voltage (LV) or medium voltage (MV) device region. In some embodiments, a first transistor 112a and a second transistor 112b may be formed in the second device region 112, and a plurality of isolation regions 91, such as shallow trench isolation (STI) regions, may be formed in the second device region 112 to isolate the first transistor 112a and the second transistor 112b. The above structure is merely an exemplary structure, and any other structure different from this may be used.

[0225] Through the above process, a simple one-step etching process of deep trenches can be achieved without using additional masks or steps. In addition, a pick-up structure to the buried layer is generated by filling the third trench rather than by diffusion, wherein the oxide layer and / or nitride layer acts as a diffusion barrier.

[0226] Exemplary embodiments of the present disclosure are also embodied in the following clauses.

[0227] 1. A method for manufacturing a semiconductor device, comprising:

[0228] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0229] forming a hard mask layer (4) on the epitaxial layer (3);

[0230] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11);

[0231] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0232] Depositing undoped polysilicon (80) so that undoped polysilicon (80) is formed on the sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53);

[0233] Depositing a diffusion material (81) so that the diffusion material (81) is formed on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53);

[0234] Completely filling the third trench (53) with a filling material;

[0235] removing the diffusion material (81) and the filling material from the first trench (51) and the second trench (52);

[0236] A first doped region (83) having the second doping type is formed in the epitaxial layer (3) near the sidewall of the third trench (53), wherein the first doped region (83) extends from the top surface of the epitaxial layer (3) to the buried layer (2) and is configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3);

[0237] forming a trench oxide layer (44) on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53);

[0238] Depositing a dielectric layer (8) so that the dielectric layer (8) is formed on the sidewalls and the oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53), and etching the dielectric layer (8) and the oxide layer at the bottom of the first trench (51);

[0239] Depositing a conductive material (84) so ​​that the conductive material at least fills the first trench (51);

[0240] removing the conductive material (84) on the hard mask layer (4);

[0241] A plurality of device regions are formed in the epitaxial layer (3).

[0242] 2. The method of clause 1, wherein forming the hard mask layer (4) comprises:

[0243] growing a first oxide layer (41) on the top surface of the epitaxial layer (3); and

[0244] A nitride layer (42) is deposited on the first oxide layer (41).

[0245] 3. The method according to clause 2, wherein the substrate (1), the buried layer (2) and the epitaxial layer (3) are formed of silicon material, the first oxide layer (41) is formed of silicon dioxide, and the nitride layer (42) is formed of silicon nitride.

[0246] 4. The method of clause 2, wherein the diffusion material (81) and the first oxide layer (41) both comprise silicon dioxide.

[0247] 5. The method according to clause 2, wherein the nitride layer (42) is etched using hot phosphoric acid so that the opening of the nitride layer (42) is enlarged.

[0248] 6. The method according to clause 2, further comprising etching away a portion of the diffusion material (81) so that the height of the diffusion material (81) is reduced to below the nitride layer (42) and the opening formed by the diffusion material (81) is enlarged.

[0249] 7. The method according to item 2 also includes etching the dielectric layer (8) and the trench oxide layer (44), removing the dielectric layer (8) from the top surface of the nitride layer (42), and extending the second opening (54) to the bottom of the first trench (51), and forming a first opening (71) aligned with the second opening (54) at the bottom of the first trench (51).

[0250] 8. The method according to item 7 also includes ion implantation into the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) near the bottom of the first trench (51), wherein the second doped region (9) has a first doping type and has a higher doping concentration than the substrate (1).

[0251] 9. The method of clause 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0252] The hard mask layer (4) and the semiconductor body (11) are etched once using the soft mask layer (10) to form a first trench opening (510), a second trench opening (520) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

[0253] 10. The method according to clause 9, wherein the width of the first groove opening (510) is greater than the width of the second groove opening (520), and the width of the second groove opening (520) is greater than the width of the third groove opening (530).

[0254] 11. The method of clause 1, wherein completely filling the third trench (53) comprises forming an air gap in the third trench (53).

[0255] 12. The method of clause 1, wherein the filling material comprises a diffusion material (81), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with the diffusion material (81).

[0256] 13. The method of clause 1, wherein the filling material comprises a diffusion material (81) and a dielectric material (82), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with the diffusion material (81) and the dielectric material (82).

[0257] 14. A method according to item 13, wherein completely filling the third trench (53) with a diffusion material (81) and a dielectric material (82) includes partially filling the third trench (53) with the diffusion material (81) and continuing to fill the dielectric material (82) in the third trench (53) to seal the diffusion material (81).

[0258] 15. The method of clause 13, wherein the dielectric material (82) is etched so that openings formed by the dielectric material (82) in the first trench (51) and the second trench (52) are enlarged.

[0259] 16. The method of clause 13, wherein the diffusion material (81) and the dielectric material (82) are completely removed from the first trench (51) and the second trench (52) using hydrofluoric acid, and the first oxide layer (41) is protected from etching using the undoped polysilicon (80).

[0260] 17. The method according to clause 1, wherein the third trench (53) is completely filled, whereas the first trench (51) and the second trench (52) are partially filled.

[0261] 18. A method according to item 1, wherein the diffusion material (81) includes dopants of a second doping type, and the method further includes thermally advancing the diffusion material (81) so that the dopants of the second doping type in the diffusion material (81) diffuse into the area of ​​the epitaxial layer (3) near the side wall of the third trench (53), thereby forming a first doped region (83).

[0262] 19. The method of clause 1, wherein forming a first doped region (83) having the second doping type in the epitaxial layer (3) adjacent to a sidewall of the third trench (53) comprises:

[0263] depositing a diffusion material (81) in the third trench (53), the diffusion material (81) comprising a dopant of the second doping type; and

[0264] The diffusion material (81) is thermally annealed to diffuse the dopant into a region of the epitaxial layer (3) close to the side wall of the third trench (53), thereby forming the first doping region (83).

[0265] 20. The method of clause 19, wherein the first doped region (83) is formed on both sides of the third trench (53).

[0266] 21. The method of clause 1, further comprising removing the diffusion material (81) and the filling material in the third trench (53).

[0267] 22. The method of clause 1, wherein the soft mask layer (10) is a photoresist.

[0268] 23. A method according to item 1, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), the second trench (52) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a second depth (D2), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the second depth (D2), and the second depth (D2) is greater than the third depth (D3).

[0269] 24. A method according to item 1, wherein before depositing undoped polysilicon (80), a thin oxide layer (40) is formed on the sidewalls of the first trench (51), the second trench (52) and the third trench (53), wherein the thickness of the thin oxide layer (40) is 50-500A.

[0270] 25. The method of clause 24, further comprising stripping off a thin oxide layer (40) formed on sidewalls of the first trench (51), the second trench (52), and the third trench (53).

[0271] 26. The method of clause 1, wherein the undoped polysilicon (80) is deposited to a thickness of 200-3000 Å.

[0272] 27. A method according to item 1, wherein when the first doping type is p-type, the diffusion material (81) includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus; and wherein when the first doping type is n-type, the diffusion material (81) includes borosilicate glass, and the dopant is boron.

[0273] 28. The method according to clause 1, wherein the dielectric layer (8) comprises tetraethyl orthosilicate or an oxide.

[0274] 29. A method according to item 1, wherein the trench oxide layer (44) and the dielectric layer (8) in the first trench (51) form a first deep trench isolation structure (511), the trench oxide layer (44) and the dielectric layer (8) in the second trench (52) form a second deep trench isolation structure (521), and the trench oxide layer (44) and the dielectric layer (8) in the third trench 53 form a third deep trench isolation structure (531).

[0275] 30. The method of clause 1, wherein the conductive material (84) comprises polysilicon having a first doping type.

[0276] 31. The method of clause 1, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0277] 32. According to the method described in item 1, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0278] 33. A method for manufacturing a semiconductor device, comprising:

[0279] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0280] forming a hard mask layer (4) on the epitaxial layer (3);

[0281] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51) and a third trench (53) in the semiconductor body (11);

[0282] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0283] Depositing undoped polysilicon (80) so that undoped polysilicon (80) is formed on the sidewalls and bottom of the first trench (51) and the third trench (53);

[0284] Depositing a diffusion material (81) so that the diffusion material (81) is formed on the sidewalls and bottom of the first trench (51) and the third trench (53);

[0285] Completely filling the third trench (53) with a filling material;

[0286] removing the diffusion material (81) and the filling material from the first trench (51);

[0287] A first doped region (83) having the second doping type is formed in the epitaxial layer (3) near the sidewall of the third trench (53), wherein the first doped region (83) extends from the top surface of the epitaxial layer (3) to the buried layer (2) and is configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3);

[0288] forming a trench oxide layer (44) on the sidewalls and bottom of the first trench (51) and the third trench (53);

[0289] Depositing a dielectric layer (8) so that a dielectric layer (8) is formed on the sidewalls and the oxide layer at the bottom of the first trench (51) and the third trench (53), and etching the dielectric layer (8) and the oxide layer at the bottom of the first trench (51);

[0290] Depositing a conductive material (84) so ​​that the conductive material at least fills the first trench (51);

[0291] removing the conductive material (84) on the hard mask layer (4);

[0292] A plurality of device regions are formed in the epitaxial layer (3).

[0293] 34. The method of clause 33, wherein forming the hard mask layer (4) comprises:

[0294] growing a first oxide layer (41) on the top surface of the epitaxial layer (3); and

[0295] A nitride layer (42) is deposited on the first oxide layer (41).

[0296] 35. A method according to clause 34, wherein the substrate (1), the buried layer (2) and the epitaxial layer (3) are formed of silicon material, the first oxide layer (41) is formed of silicon dioxide, and the nitride layer (42) is formed of silicon nitride.

[0297] 36. The method of clause 34, wherein the diffusion material (81) and the first oxide layer (41) both comprise silicon dioxide.

[0298] 37. The method of clause 34, wherein the nitride layer (42) is etched using hot phosphoric acid so that the opening of the nitride layer (42) is enlarged.

[0299] 38. The method of clause 34, further comprising etching away a portion of the diffusion material (81) so that a height of the diffusion material (81) is reduced to below the nitride layer (42) and an opening formed by the diffusion material (81) is enlarged.

[0300] 39. The method according to item 34 also includes etching the dielectric layer (8) and the trench oxide layer (44), removing the dielectric layer (8) from the top surface of the nitride layer (42), and extending the second opening (54) to the bottom of the first trench (51), and forming a first opening (71) aligned with the second opening (54) at the bottom of the first trench (51).

[0301] 40. The method according to item 39 also includes ion implantation into the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) near the bottom of the first trench (51), wherein the second doped region (9) has a first doping type and has a higher doping concentration than the substrate (1).

[0302] 41. The method of clause 33, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0303] The hard mask layer (4) and the semiconductor body (11) are etched once using the soft mask layer (10) to form a first trench opening (510) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510) and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

[0304] 42. The method of clause 41, wherein the width of the first groove opening (510) is greater than the width of the third groove opening (530).

[0305] 43. The method of clause 33, wherein completely filling the third trench (53) comprises forming an air gap in the third trench (53).

[0306] 44. The method of clause 33, wherein the fill material comprises a diffusion material (81), and completely filling the third trench (53) with the fill material comprises completely filling the third trench (53) with the diffusion material (81).

[0307] 45. The method of clause 33, wherein the filling material comprises a diffusion material (81) and a dielectric material (82), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with the diffusion material (81) and the dielectric material (82).

[0308] 46. ​​A method according to item 45, wherein completely filling the third trench (53) with a diffusion material (81) and a dielectric material (82) includes partially filling the third trench (53) with the diffusion material (81) and continuing to fill the dielectric material (82) in the third trench (53) to seal the diffusion material (81).

[0309] 47. The method of clause 45, wherein the dielectric material (82) is etched so that an opening formed by the dielectric material (82) in the first trench (51) is enlarged.

[0310] 47. The method of clause 45, wherein the diffusion material (81) and the dielectric material (82) are completely removed from the first trench (51) using hydrofluoric acid, and the first oxide layer (41) is protected from etching using the undoped polysilicon (80).

[0311] 49. A method according to clause 33, wherein the third trench (53) is completely filled, whereas the first trench (51) is partially filled.

[0312] 50. A method according to item 33, wherein the diffusion material (81) includes dopants of a second doping type, and the method further includes thermally advancing the diffusion material (81) so that the dopants of the second doping type in the diffusion material (81) diffuse into the area of ​​the epitaxial layer (3) near the side wall of the third trench (53), thereby forming a first doping region (83).

[0313] 51. The method of clause 33, wherein forming a first doped region (83) having the second doping type in the epitaxial layer (3) adjacent to a sidewall of the third trench (53) comprises:

[0314] depositing a diffusion material (81) in the third trench (53), the diffusion material (81) comprising a dopant of the second doping type; and

[0315] The diffusion material (81) is thermally annealed to diffuse the dopant into a region of the epitaxial layer (3) close to the side wall of the third trench (53), thereby forming the first doping region (83).

[0316] 52. The method of clause 51, wherein the first doped region (83) is formed on both sides of the third trench (53).

[0317] 53. The method of clause 33, further comprising removing the diffusion material (81) and the filling material in the third trench (53).

[0318] 54. The method of clause 33, wherein the soft mask layer (10) is a photoresist.

[0319] 55. A method according to item 33, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the third depth (D3).

[0320] 56. A method according to item 33, wherein before depositing undoped polysilicon (80), a thin oxide layer (40) is formed on the sidewalls of the first trench (51) and the third trench (53), wherein the thickness of the thin oxide layer (40) is 50-500A.

[0321] 57. The method of clause 56, further comprising stripping off a thin oxide layer (40) formed on sidewalls of the first trench (51) and the third trench (53).

[0322] 58. The method of clause 33, wherein the undoped polysilicon (80) is deposited to a thickness of 200-3000 Å.

[0323] 59. A method according to item 33, wherein when the first doping type is p-type, the diffusion material (81) includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus; and wherein when the first doping type is n-type, the diffusion material (81) includes borosilicate glass, and the dopant is boron.

[0324] 60. The method according to clause 33, wherein the dielectric layer (8) comprises tetraethyl orthosilicate or an oxide.

[0325] 61. A method according to item 33, wherein the trench oxide layer (44) and the dielectric layer (8) in the first trench (51) form a first deep trench isolation structure (511), and the trench oxide layer (44) and the dielectric layer (8) in the third trench 53 form a third deep trench isolation structure (531).

[0326] 62. The method of clause 33, wherein the conductive material (84) comprises polysilicon having a first doping type.

[0327] 63. The method of clause 33, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0328] 64. According to the method described in item 33, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0329] 65. A method for manufacturing a semiconductor device, comprising:

[0330] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0331] forming a hard mask layer (4) on the top surface of the epitaxial layer (3);

[0332] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11);

[0333] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0334] Depositing a conductive material layer (85) to fill the first trench (51), the second trench (52) and the third trench (53);

[0335] removing the conductive material layer (85) in the first groove (51) and the second groove (52), and retaining the conductive material layer (85) in the third groove (53);

[0336] forming a deposited oxide layer (86) to fill the second trench (52) while the first trench (51) remains open;

[0337] Performing etching to open the bottom of the first groove (51) to form an opening;

[0338] Depositing a conductive material (84) so ​​that the conductive material (84) at least fills the first trench (51);

[0339] removing the conductive material (84) on the hard mask layer (4);

[0340] A plurality of device regions are formed in the epitaxial layer (3).

[0341] 66. The method according to clause 65, wherein before depositing the conductive material layer (85), the method further comprises:

[0342] A trench oxide layer is formed on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53).

[0343] 67. The method according to clause 66, further comprising removing an oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0344] 68. The method of clause 66, wherein a thin layer oxidation step is performed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53) to form a trench oxide layer (44).

[0345] 69. The method of clause 66, wherein tetraethyl orthosilicate is deposited on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53) to form a trench oxide layer (44).

[0346] 70. The method of clause 66, wherein the layer of conductive material (85) is n-type doped polysilicon.

[0347] 71. The method of clause 66, wherein forming the hard mask layer (4) comprises:

[0348] Growing a first oxide layer (41) on the top surface of the epitaxial layer (3);

[0349] depositing a nitride layer (42) on the first oxide layer (41); and

[0350] A second oxide layer (43) is deposited on the nitride layer (42).

[0351] 72. The method of clause 66, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0352] The hard mask layer (4) and the semiconductor body (11) are etched once using the single soft mask layer (10) to form a first trench opening (510), a second trench opening (520) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

[0353] 73. A method according to item 66, wherein the width of the first groove opening (510) is greater than the width of the second groove opening (520), and the width of the second groove opening (520) is greater than the width of the third groove opening (530).

[0354] 74. The method of clause 66, wherein the soft mask layer (10) is a photoresist.

[0355] 75. A method according to item 66, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), the second trench (52) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a second depth (D2), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the second depth (D2), and the second depth (D2) is greater than the third depth (D3).

[0356] 76. A method according to item 66, wherein before forming a trench oxide layer (44) on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a thin sacrificial oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), and the thin sacrificial oxide layer is then removed.

[0357] 77. The method of clause 66, wherein a thin trench oxide layer is formed on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0358] 78. A method according to item 77, wherein after a thin trench oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a thin nitride layer (45) is formed on the thin trench oxide layer.

[0359] 79. The method of clause 77, wherein the thin trench oxide layer has a thickness of 50-100 Å.

[0360] 80. The method of clause 78, wherein the further oxide layer is formed on the thin nitride layer (45) by oxidizing the surface of the thin nitride layer (45).

[0361] 81. The method of clause 78, wherein the thin nitride layer (42) has a thickness of 100-200 Å.

[0362] 82. The method of clause 78, further comprising removing the thin nitride layer and the thin trench oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0363] 83. The method of clause 78, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), the thin nitride layer in the first trench (51) and the second trench (52) is removed.

[0364] 84. The method of clause 83, further comprising removing a thin trench oxide layer in the first trench (51) and the second trench (52).

[0365] 85. The method of clause 66, wherein a single oxide layer is formed on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0366] 86. The method of clause 85, wherein the single oxide layer has a thickness of 300-500 Å.

[0367] 87. The method of clause 85, further comprising removing a single oxide layer at the bottom of the first trench (51), the second trench (52), and the third trench (53).

[0368] 88. The method of clause 85, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), removing the single oxide layer in the first trench (51) and the second trench (52).

[0369] 89. The method of clause 66, wherein a thick trench oxide layer is formed on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0370] 90. The method of clause 89, wherein the thick trench oxide layer has a thickness of 400-5000 Å.

[0371] 91. A method according to item 89, wherein after a thick trench oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a nitride layer (42) is formed on the thick trench oxide layer.

[0372] 92. The method of clause 91, wherein the thin nitride layer (42) has a thickness of 50-100 Å.

[0373] 93. The method of clause 89, further comprising removing a thick trench oxide layer at the bottom of the first trench (51), the second trench (52), and the third trench (53).

[0374] 94. The method of clause 91, further comprising removing the thin nitride layer and the thick trench oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0375] 95. A method according to item 91, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), the thin nitride layer in the first trench (51) and the second trench (52) is removed.

[0376] 96. A method according to item 66, wherein the opening of the first trench (51) and the opening of the second trench (52) are enlarged by etching the conductive material layer, and the bottom of the first trench (51) and the second trench (52) can be etched away.

[0377] 97. The method according to item 66 also includes performing ion implantation at the bottom of the first trench (51) and the second trench (52).

[0378] 98. The method of clause 66, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0379] 99. According to the method described in item 66, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0380] 100. A method for manufacturing a semiconductor device, comprising:

[0381] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0382] forming a hard mask layer (4) on the top surface of the epitaxial layer (3);

[0383] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51) and a third trench (53) in the semiconductor body (11);

[0384] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0385] Depositing a conductive material layer (85) to fill the first trench (51) and the third trench (53);

[0386] removing the conductive material layer (85) in the first groove (51) and retaining the conductive material layer (85) in the third groove (53);

[0387] Performing etching to open the bottom of the first groove (51) to form an opening;

[0388] Depositing a conductive material (84) so ​​that the conductive material (84) at least fills the first trench (51);

[0389] removing the conductive material (84) on the hard mask layer (4);

[0390] A plurality of device regions are formed in the epitaxial layer (3).

[0391] 101. The method according to clause 100, wherein before depositing the conductive material layer (85), the method further comprises:

[0392] A trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53).

[0393] 102. The method according to clause 101, further comprising removing an oxide layer at the bottom of the first trench (51) and the third trench (53).

[0394] 103. The method of clause 101, wherein a thin layer oxidation step is performed on the sidewalls and bottom of the first trench (51) and the third trench (53) to form a trench oxide layer (44).

[0395] 104. The method of clause 101, wherein tetraethyl orthosilicate is deposited on sidewalls and bottoms of the first trench (51) and the third trench (53) to form a trench oxide layer (44).

[0396] 105. The method of clause 101, wherein the layer of conductive material (85) is n-type doped polysilicon.

[0397] 106. The method of clause 101, wherein forming the hard mask layer (4) comprises:

[0398] Growing a first oxide layer (41) on the top surface of the epitaxial layer (3);

[0399] depositing a nitride layer (42) on the first oxide layer (41); and

[0400] A second oxide layer (43) is deposited on the nitride layer (42).

[0401] 107. The method of clause 101, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0402] The hard mask layer (4) and the semiconductor body (11) are etched once using the single soft mask layer (10) to form a first trench opening (510) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and to form the first trench (51) aligned with the first trench opening (510) and the third trench (53) aligned with the third trench opening (530) in the semiconductor body (11).

[0403] 108. The method of clause 101, wherein a width of the first groove opening (510) is greater than a width of the third groove opening (530).

[0404] 109. The method of clause 101, wherein the soft mask layer (10) is a photoresist.

[0405] 110. A method according to item 101, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the third depth (D3).

[0406] 111. A method according to item 101, wherein before forming the trench oxide layer (44) on the sidewalls and bottom of the first trench (51) and the third trench (53), a thin sacrificial oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53), and the thin sacrificial oxide layer is then removed.

[0407] 112. The method of clause 101, wherein a thin trench oxide layer is formed on sidewalls and bottoms of the first trench (51) and the third trench (53).

[0408] 113. The method of clause 112, wherein after forming a thin trench oxide layer on the sidewalls and bottom of the first trench (51) and the third trench (53), a thin nitride layer (45) is formed on the thin trench oxide layer.

[0409] 114. The method of clause 112, wherein the thin trench oxide layer has a thickness of 50-100 Å.

[0410] 115. The method of clause 113, wherein the further oxide layer is formed on the thin nitride layer (45) by oxidizing the surface of the thin nitride layer (45).

[0411] 116. The method of clause 113, wherein the thin nitride layer (42) has a thickness of 100-200 Å.

[0412] 117. The method of clause 113, further comprising removing the thin nitride layer and the thin trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0413] 118. The method of clause 113, wherein after removing the conductive material layer (85) in the first trench (51), removing the thin nitride layer in the first trench (51).

[0414] 119. The method of clause 118, further comprising removing a thin trench oxide layer in the first trench (51).

[0415] 120. The method of clause 101, wherein a single oxide layer is formed on sidewalls and bottoms of the first trench (51) and the third trench (53).

[0416] 121. The method of clause 120, wherein the single oxide layer has a thickness of 300-500 Å.

[0417] 122. The method of clause 120, further comprising removing the single oxide layer at the bottom of the first trench (51) and the third trench (53).

[0418] 123. The method of clause 120, wherein after removing the conductive material layer (85) in the first trench (51), removing the single oxide layer in the first trench (51).

[0419] 124. The method of clause 101, wherein a thick trench oxide layer is formed on sidewalls and bottoms of the first trench (51) and the third trench (53).

[0420] 125. The method of clause 124, wherein the thick trench oxide layer has a thickness of 400-5000 Å.

[0421] 126. The method of clause 124, wherein after forming a thick trench oxide layer on the sidewalls and bottom of the first trench (51) and the third trench (53), a nitride layer (42) is formed on the thick trench oxide layer.

[0422] 127. The method of clause 126, wherein the thin nitride layer (42) has a thickness of 50-100 Å.

[0423] 128. The method of clause 124, further comprising removing a thick trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0424] 129. The method of clause 126, further comprising removing the thin nitride layer and the thick trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0425] 130. The method of clause 126, wherein after removing the conductive material layer (85) in the first trench (51), removing the thin nitride layer in the first trench (51).

[0426] 131. A method according to item 101, wherein the opening of the first trench (51) is enlarged by etching the conductive material layer, and the bottom of the first trench (51) can be etched away.

[0427] 132. The method according to item 101, further comprising performing ion implantation at the bottom of the first trench (51).

[0428] 133. The method of clause 101, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0429] 134. According to the method described in item 101, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0430] 135. A method for manufacturing a semiconductor device, comprising:

[0431] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0432] forming a hard mask layer (4) on the top surface of the epitaxial layer (3);

[0433] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11);

[0434] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0435] Depositing a conductive material layer (85) to fill the first trench (51), the second trench (52) and the third trench (53);

[0436] removing the conductive material layer (85) in the first groove (51) and the second groove (52), and retaining the conductive material layer (85) in the third groove (53);

[0437] forming a deposited oxide layer (86) to fill the second trench (52) while the first trench (51) remains open;

[0438] Performing etching to open the bottom of the first groove (51) to form an opening;

[0439] Depositing a conductive material (84) so ​​that the conductive material (84) at least fills the first trench (51);

[0440] removing the conductive material (84) on the hard mask layer (4);

[0441] A plurality of device regions are formed in the epitaxial layer (3).

[0442] 136. The method according to clause 135, wherein before depositing the conductive material layer (85), the method further comprises:

[0443] A trench oxide layer is formed on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53).

[0444] 137. The method according to item 136, further comprising removing an oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0445] 138. A method according to item 136, wherein a thin layer oxidation step is performed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53) to form a trench oxide layer (44).

[0446] 139. A method according to item 136, wherein tetraethyl orthosilicate is deposited on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53) to form a trench oxide layer (44).

[0447] 140. The method of clause 136, wherein the layer of conductive material (85) is n-type doped polysilicon.

[0448] 141. The method of clause 136, wherein forming the hard mask layer (4) comprises:

[0449] growing a first oxide layer (41) on the top surface of the epitaxial layer (3); and

[0450] A nitride layer (42) is deposited on the first oxide layer (41).

[0451] 142. The method of clause 136, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0452] The hard mask layer (4) and the semiconductor body (11) are etched once using the single soft mask layer (10) to form a first trench opening (510), a second trench opening (520) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

[0453] 143. A method according to item 136, wherein the width of the first groove opening (510) is greater than the width of the second groove opening (520), and the width of the second groove opening (520) is greater than the width of the third groove opening (530).

[0454] 144. The method of clause 136, wherein the soft mask layer (10) is a photoresist.

[0455] 145. A method according to item 136, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), the second trench (52) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a second depth (D2), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the second depth (D2), and the second depth (D2) is greater than the third depth (D3).

[0456] 146. A method according to item 136, wherein before forming a trench oxide layer (44) on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a thin sacrificial oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), and the thin sacrificial oxide layer is then removed.

[0457] 147. The method of clause 136, wherein a thin trench oxide layer is formed on sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0458] 148. A method according to item 147, wherein after a thin trench oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a thin nitride layer (45) is formed on the thin trench oxide layer.

[0459] 149. The method of clause 147, wherein the thin trench oxide layer has a thickness of 50-100 Å.

[0460] 150. The method of clause 148, wherein the further oxide layer is formed on the thin nitride layer (45) by oxidizing a surface of the thin nitride layer (45).

[0461] 151. The method of clause 148, wherein the thin nitride layer (42) has a thickness of 100-200 Å.

[0462] 152. The method according to item 148 further includes removing the thin nitride layer and the thin trench oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0463] 153. A method according to item 148, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), the thin nitride layer in the first trench (51) and the second trench (52) is removed.

[0464] 154. The method of clause 153, further comprising removing a thin trench oxide layer in the first trench (51) and the second trench (52).

[0465] 155. The method of clause 136, wherein a single oxide layer is formed on the sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0466] 156. The method of clause 155, wherein the single oxide layer has a thickness of 300-500 Å.

[0467] 157. The method of clause 155, further comprising removing a single oxide layer at the bottom of the first trench (51), the second trench (52), and the third trench (53).

[0468] 158. A method according to item 155, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), a single oxide layer in the first trench (51) and the second trench (52) is removed.

[0469] 159. The method of clause 136, wherein a thick trench oxide layer is formed on the sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53).

[0470] 160. The method of clause 159, wherein the thick trench oxide layer has a thickness of 400-5000 Å.

[0471] 161. A method according to item 159, wherein after a thick trench oxide layer is formed on the sidewalls and bottom of the first trench (51), the second trench (52) and the third trench (53), a nitride layer (42) is formed on the thick trench oxide layer.

[0472] 162. The method of clause 161, wherein the thin nitride layer (42) has a thickness of 50-100 Å.

[0473] 163. The method of clause 159, further comprising removing a thick trench oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0474] 164. The method according to item 161 also includes removing the thin nitride layer and the thick trench oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53).

[0475] 165. A method according to item 161, wherein after removing the conductive material layer (85) in the first trench (51) and the second trench (52), the thin nitride layer in the first trench (51) and the second trench (52) is removed.

[0476] 166. A method according to item 136, wherein the opening of the first groove (51) and the opening of the second groove (52) are enlarged by etching the conductive material layer, and the bottom of the first groove (51) and the second groove (52) can be etched away.

[0477] 167. The method according to item 136 also includes performing ion implantation at the bottom of the first trench (51) and the second trench (52).

[0478] 168. The method of clause 136, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0479] 169. According to the method described in item 136, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0480] 170. A method for manufacturing a semiconductor device, comprising:

[0481] A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type;

[0482] forming a hard mask layer (4) on the top surface of the epitaxial layer (3);

[0483] Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51) and a third trench (53) in the semiconductor body (11);

[0484] peeling the soft mask layer (10) from the top surface of the hard mask layer (4);

[0485] Depositing a conductive material layer (85) to fill the first trench (51) and the third trench (53);

[0486] removing the conductive material layer (85) in the first groove (51) and retaining the conductive material layer (85) in the third groove (53);

[0487] Performing etching to open the bottom of the first groove (51) to form an opening;

[0488] Depositing a conductive material (84) so ​​that the conductive material (84) at least fills the first trench (51);

[0489] removing the conductive material (84) on the hard mask layer (4);

[0490] A plurality of device regions are formed in the epitaxial layer (3).

[0491] 171. The method of clause 170, wherein before depositing the conductive material layer (85), further comprising:

[0492] A trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53).

[0493] 172. The method according to item 171 further includes removing the oxide layer at the bottom of the first trench (51) and the third trench (53).

[0494] 173. A method according to clause 171, wherein a thin layer oxidation step is performed on the sidewalls and bottom of the first trench (51) and the third trench (53) to form a trench oxide layer (44).

[0495] 174. The method of clause 171, wherein tetraethyl orthosilicate is deposited on sidewalls and bottoms of the first trench (51) and the third trench (53) to form a trench oxide layer (44).

[0496] 175. The method of clause 171, wherein the layer of conductive material (85) is n-type doped polysilicon.

[0497] 176. The method of clause 171, wherein forming the hard mask layer (4) comprises:

[0498] growing a first oxide layer (41) on the top surface of the epitaxial layer (3); and

[0499] A nitride layer (42) is deposited on the first oxide layer (41).

[0500] 177. The method of clause 171, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises:

[0501] The hard mask layer (4) and the semiconductor body (11) are etched once using the single soft mask layer (10) to form a first trench opening (510) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and to form the first trench (51) aligned with the first trench opening (510) and the third trench (53) aligned with the third trench opening (530) in the semiconductor body (11).

[0502] 178. A method according to item 171, wherein the width of the first groove opening (510) is greater than the width of the third groove opening (530).

[0503] 179. A method according to clause 171, wherein the soft mask layer (10) is a photoresist.

[0504] 180. A method according to item 171, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the third depth (D3).

[0505] 181. A method according to item 171, wherein before forming the trench oxide layer (44) on the sidewalls and bottom of the first trench (51) and the third trench (53), a thin sacrificial oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53), and the thin sacrificial oxide layer is then removed.

[0506] 182. The method of clause 171, wherein a thin trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53).

[0507] 183. A method according to item 182, wherein after a thin trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53), a thin nitride layer (45) is formed on the thin trench oxide layer.

[0508] 184. The method of clause 182, wherein the thin trench oxide layer has a thickness of 50-100 Å.

[0509] 185. A method according to item 183, wherein a further oxide layer is formed on the thin nitride layer (45) by oxidizing the surface of the thin nitride layer (45).

[0510] 186. The method of clause 183, wherein the thin nitride layer (42) has a thickness of 100-200 Å.

[0511] 187. The method according to item 183 also includes removing the thin nitride layer and the thin trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0512] 188. A method according to item 183, wherein after removing the conductive material layer (85) in the first trench (51), the thin nitride layer in the first trench (51) is removed.

[0513] 189. The method of clause 188, further comprising removing a thin trench oxide layer in the first trench (51).

[0514] 190. The method of clause 171, wherein a single oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53).

[0515] 191. A method according to item 190, wherein the thickness of the single oxide layer is 300-500A.

[0516] 192. The method of clause 190, further comprising removing the single oxide layer at the bottom of the first trench (51) and the third trench (53).

[0517] 193. The method of clause 190, wherein after removing the conductive material layer (85) in the first trench (51), removing the single oxide layer in the first trench (51).

[0518] 194. A method according to item 171, wherein a thick trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53).

[0519] 195. A method according to item 194, wherein the thickness of the thick trench oxide layer is 400-5000A.

[0520] 196. A method according to item 194, wherein after a thick trench oxide layer is formed on the sidewalls and bottom of the first trench (51) and the third trench (53), a nitride layer (42) is formed on the thick trench oxide layer.

[0521] 197. A method according to item 196, wherein the thickness of the thin nitride layer (42) is 50-100A.

[0522] 198. The method according to item 194 also includes removing the thick trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0523] 199. The method according to item 196 also includes removing the thin nitride layer and the thick trench oxide layer at the bottom of the first trench (51) and the third trench (53).

[0524] 200. The method of clause 196, wherein after removing the conductive material layer (85) in the first trench (51), the thin nitride layer in the first trench (51) is removed.

[0525] 201. A method according to item 171, wherein the opening of the first trench (51) is enlarged by etching the conductive material layer, and the bottom of the first trench (51) can be etched away.

[0526] 202. The method according to item 171 also includes performing ion implantation at the bottom of the first trench (51).

[0527] 203. The method of clause 171, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

[0528] 204. According to the method described in item 171, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high voltage device region and the second device region (112) is a low voltage or medium voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

[0529] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, comprising: A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type; forming a hard mask layer (4) on the epitaxial layer (3); Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51), a second trench (52) and a third trench (53) in the semiconductor body (11); peeling the soft mask layer (10) from the top surface of the hard mask layer (4); Depositing undoped polysilicon (80) so that undoped polysilicon (80) is formed on the sidewalls and bottoms of the first trench (51), the second trench (52), and the third trench (53); Depositing a diffusion material (81) so that the diffusion material (81) is formed on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53); Completely filling the third trench (53) with a filling material; removing the diffusion material (81) and the filling material from the first trench (51) and the second trench (52); A first doped region (83) having the second doping type is formed in the epitaxial layer (3) near the sidewall of the third trench (53), wherein the first doped region (83) extends from the top surface of the epitaxial layer (3) to the buried layer (2) and is configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3); forming a trench oxide layer (44) on the sidewalls and bottoms of the first trench (51), the second trench (52) and the third trench (53); Depositing a dielectric layer (8) so that the dielectric layer (8) is formed on the sidewalls and the oxide layer at the bottom of the first trench (51), the second trench (52) and the third trench (53), and etching the dielectric layer (8) and the oxide layer at the bottom of the first trench (51); Depositing a conductive material (84) so ​​that the conductive material at least fills the first trench (51); removing the conductive material (84) on the hard mask layer (4); A plurality of device regions are formed in the epitaxial layer (3).

2. The method according to claim 1, wherein forming the hard mask layer (4) comprises: Growing a first oxide layer (41) on the top surface of the epitaxial layer (3); as well as A nitride layer (42) is deposited on the first oxide layer (41).

3. The method according to claim 2, wherein the substrate (1), the buried layer (2) and the epitaxial layer (3) are formed of silicon material, the first oxide layer (41) is formed of silicon dioxide, and the nitride layer (42) is formed of silicon nitride.

4. The method of claim 2, wherein the diffusion material (81) and the first oxide layer (41) both comprise silicon dioxide.

5. The method according to claim 2, wherein the nitride layer (42) is etched using hot phosphoric acid so that the opening of the nitride layer (42) is enlarged.

6. The method according to claim 2, further comprising etching away a portion of the diffusion material (81) so that the height of the diffusion material (81) is reduced to below the nitride layer (42) and the opening formed by the diffusion material (81) is enlarged.

7. The method according to claim 2 further comprises etching the dielectric layer (8) and the trench oxide layer (44), removing the dielectric layer (8) from the top surface of the nitride layer (42), extending the second opening (54) to the bottom of the first trench (51), and forming a first opening (71) aligned with the second opening (54) at the bottom of the first trench (51).

8. The method according to claim 7 further comprises performing ion implantation into the substrate (1) through the second opening (54) and the first opening (71) to form a second doping region (9) in the substrate (1) near the bottom of the first trench (51), wherein the second doping region (9) has a first doping type and has a higher doping concentration than the substrate (1).

9. The method according to claim 1, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises: The hard mask layer (4) and the semiconductor body (11) are etched once using the soft mask layer (10) to form a first trench opening (510), a second trench opening (520) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510), the second trench (52) aligned with the second trench opening (520), and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

10. The method according to claim 9, wherein a width of the first trench opening (510) is greater than a width of the second trench opening (520), and a width of the second trench opening (520) is greater than a width of the third trench opening (530).

11. The method of claim 1, wherein completely filling the third trench (53) comprises forming an air gap in the third trench (53).

12. The method of claim 1, wherein the filling material comprises a diffusion material (81), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with the diffusion material (81).

13. The method of claim 2, wherein the filling material comprises a diffusion material (81) and a dielectric material (82), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with the diffusion material (81) and the dielectric material (82).

14. The method of claim 13, wherein completely filling the third trench (53) with a diffusion material (81) and a dielectric material (82) comprises partially filling the third trench (53) with the diffusion material (81), and continuing to fill the dielectric material (82) in the third trench (53) to seal the diffusion material (81).

15. The method of claim 13, wherein the dielectric material (82) is etched so that openings formed by the dielectric material (82) in the first trench (51) and the second trench (52) are enlarged.

16. The method according to claim 13, wherein the diffusion material (81) and the dielectric material (82) are completely removed from the first trench (51) and the second trench (52) using hydrofluoric acid, and the first oxide layer (41) is protected from etching by the undoped polysilicon (80).

17. The method according to claim 1, wherein the third trench (53) is completely filled, whereas the first trench (51) and the second trench (52) are partially filled.

18. The method according to claim 1, wherein the diffusion material (81) includes dopants of a second doping type, and the method further comprises thermally advancing the diffusion material (81) so that the dopants of the second doping type in the diffusion material (81) diffuse into a region of the epitaxial layer (3) close to the side wall of the third trench (53), thereby forming a first doping region (83).

19. The method according to claim 1, wherein forming a first doped region (83) having the second doping type in the epitaxial layer (3) near the sidewall of the third trench (53) comprises: Depositing a diffusion material (81) in the third trench (53), wherein the diffusion material (81) contains a dopant of the second doping type; as well as The diffusion material (81) is thermally annealed to diffuse the dopant into a region of the epitaxial layer (3) close to the side wall of the third trench (53), thereby forming the first doping region (83).

20. The method according to claim 19, wherein the first doping region (83) is formed on both sides of the third trench (53).

21. The method of claim 1, further comprising removing the diffusion material (81) and the filling material in the third trench (53).

22. The method of claim 1, wherein the soft mask layer (10) is a photoresist.

23. A method according to claim 1, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), the second trench (52) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a second depth (D2), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the second depth (D2), and the second depth (D2) is greater than the third depth (D3).

24. The method according to claim 1, wherein before depositing undoped polysilicon (80), a thin oxide layer (40) is formed on the sidewalls of the first trench (51), the second trench (52) and the third trench (53), wherein the thickness of the thin oxide layer (40) is 50-500 Å.

25. The method according to claim 24, further comprising stripping off the thin oxide layer (40) formed on the sidewalls of the first trench (51), the second trench (52) and the third trench (53).

26. The method according to claim 1, wherein the deposition thickness of the undoped polysilicon (80) is 200-3000 Å.

27. The method according to claim 1, wherein when the first doping type is p-type, the diffusion material (81) includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus; and wherein when the first doping type is n-type, the diffusion material (81) includes borosilicate glass, and the dopant is boron.

28. The method according to claim 1, wherein the dielectric layer (8) comprises tetraethyl orthosilicate or an oxide.

29. The method according to claim 1, wherein the trench oxide layer (44) and the dielectric layer (8) in the first trench (51) form a first deep trench isolation structure (511), the trench oxide layer (44) and the dielectric layer (8) in the second trench (52) form a second deep trench isolation structure (521), and the trench oxide layer (44) and the dielectric layer (8) in the third trench (53) form a third deep trench isolation structure (531).

30. The method of claim 1, wherein the conductive material (84) comprises polysilicon having a first doping type.

31. The method of claim 1, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

32. According to the method according to claim 1, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high-voltage device region, and the second device region (112) is a low-voltage or medium-voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

33. A method for manufacturing a semiconductor device, comprising: A semiconductor body (11) is provided, the semiconductor body (11) comprising a substrate (1), a buried layer (2) arranged on the substrate (1), and an epitaxial layer (3) arranged on the buried layer (2), the substrate (1) having a first doping type, the buried layer (2) having a second doping type opposite to the first doping type; forming a hard mask layer (4) on the epitaxial layer (3); Using a soft mask layer (10) to etch the hard mask layer (4) and the semiconductor body (11) to form a first trench (51) and a third trench (53) in the semiconductor body (11); peeling the soft mask layer (10) from the top surface of the hard mask layer (4); Depositing undoped polysilicon (80) so that undoped polysilicon (80) is formed on the sidewalls and bottom of the first trench (51) and the third trench (53); Depositing a diffusion material (81) so that the diffusion material (81) is formed on the sidewalls and bottom of the first trench (51) and the third trench (53); Completely filling the third trench (53) with a filling material; removing the diffusion material (81) and the filling material from the first trench (51); A first doped region (83) having the second doping type is formed in the epitaxial layer (3) near the sidewall of the third trench (53), wherein the first doped region (83) extends from the top surface of the epitaxial layer (3) to the buried layer (2) and is configured to electrically connect the buried layer (2) to the top surface of the epitaxial layer (3); forming a trench oxide layer (44) on the sidewalls and bottom of the first trench (51) and the third trench (53); Depositing a dielectric layer (8) so that a dielectric layer (8) is formed on the sidewalls and the oxide layer at the bottom of the first trench (51) and the third trench (53), and etching the dielectric layer (8) and the oxide layer at the bottom of the first trench (51); Depositing a conductive material (84) so ​​that the conductive material at least fills the first trench (51); removing the conductive material (84) on the hard mask layer (4); A plurality of device regions are formed in the epitaxial layer (3).

34. The method of claim 33, wherein forming the hard mask layer (4) comprises: Growing a first oxide layer (41) on the top surface of the epitaxial layer (3); as well as A nitride layer (42) is deposited on the first oxide layer (41).

35. The method according to claim 34, wherein the substrate (1), the buried layer (2) and the epitaxial layer (3) are formed of silicon material, the first oxide layer (41) is formed of silicon dioxide, and the nitride layer (42) is formed of silicon nitride.

36. The method of claim 34, wherein the diffusion material (81) and the first oxide layer (41) both comprise silicon dioxide.

37. The method of claim 34, wherein the nitride layer (42) is etched using hot phosphoric acid so that the opening of the nitride layer (42) is enlarged.

38. The method according to claim 34, further comprising etching away a portion of the diffusion material (81) so that the height of the diffusion material (81) is reduced to below the nitride layer (42) and the opening formed by the diffusion material (81) is enlarged.

39. The method according to claim 34 further includes etching the dielectric layer (8) and the trench oxide layer (44), removing the dielectric layer (8) from the top surface of the nitride layer (42), and extending the second opening (54) to the bottom of the first trench (51), and forming a first opening (71) aligned with the second opening (54) at the bottom of the first trench (51).

40. The method according to claim 39 further includes performing ion implantation into the substrate (1) through the second opening (54) and the first opening (71) to form a second doped region (9) in the substrate (1) near the bottom of the first trench (51), wherein the second doped region (9) has a first doping type and has a higher doping concentration than the substrate (1).

41. The method of claim 33, wherein etching the hard mask layer (4) and the semiconductor body (11) using the soft mask layer (10) comprises: The hard mask layer (4) and the semiconductor body (11) are etched once using the soft mask layer (10) to form a first trench opening (510) and a third trench opening (530) penetrating the hard mask layer (4) in the hard mask layer (4), and the first trench (51) aligned with the first trench opening (510) and the third trench (53) aligned with the third trench opening (530) are formed in the semiconductor body (11).

42. The method of claim 41, wherein a width of the first trench opening (510) is greater than a width of the third trench opening (530).

43. The method of claim 33, wherein completely filling the third trench (53) comprises forming an air gap in the third trench (53).

44. The method of claim 33, wherein the fill material comprises a diffusion material (81), and completely filling the third trench (53) with a fill material comprises completely filling the third trench (53) with the diffusion material (81).

45. The method of claim 34, wherein the filling material comprises a diffusion material (81) and a dielectric material (82), and completely filling the third trench (53) with the filling material comprises completely filling the third trench (53) with a diffusion material (81) and a dielectric material (82).

46. ​​The method of claim 45, wherein completely filling the third trench (53) with a diffusion material (81) and a dielectric material (82) comprises partially filling the third trench (53) with the diffusion material (81) and continuing to fill the dielectric material (82) in the third trench (53) to seal the diffusion material (81).

47. The method of claim 45, wherein the dielectric material (82) is etched such that an opening formed by the dielectric material (82) in the first trench (51) is enlarged.

48. The method of claim 45, wherein the diffusion material (81) and the dielectric material (82) are completely removed from the first trench (51) using hydrofluoric acid, and the first oxide layer (41) is protected from etching by the undoped polysilicon (80).

49. The method of claim 33, wherein the third trench (53) is completely filled, whereas the first trench (51) is partially filled.

50. A method according to claim 33, wherein the diffusion material (81) includes dopants of a second doping type, and the method further comprises thermally advancing the diffusion material (81) so that the dopants of the second doping type in the diffusion material (81) diffuse into the area of ​​the epitaxial layer (3) near the side wall of the third trench (53), thereby forming a first doping region (83).

51. The method according to claim 33, wherein forming a first doped region (83) having the second doping type in the epitaxial layer (3) near the sidewall of the third trench (53) comprises: Depositing a diffusion material (81) in the third trench (53), wherein the diffusion material (81) contains a dopant of the second doping type; as well as The diffusion material (81) is thermally annealed to diffuse the dopant into a region of the epitaxial layer (3) close to the side wall of the third trench (53), thereby forming the first doping region (83).

52. The method according to claim 51, wherein the first doping region (83) is formed on both sides of the third trench (53).

53. The method of claim 33, further comprising removing the diffusion material (81) and the filling material in the third trench (53).

54. The method of claim 33, wherein the soft mask layer (10) is a photoresist.

55. A method according to claim 33, wherein the first trench (51) extends from the top surface of the epitaxial layer (3) into the substrate (1) and has a first depth (D1), and the third trench (53) extends from the top surface of the epitaxial layer (3) into the buried layer (2) or to a position in the epitaxial layer (3) close to the buried layer (2) and has a third depth (D3), wherein the first depth (D1) is greater than the third depth (D3).

56. The method according to claim 33, wherein before depositing undoped polysilicon (80), a thin oxide layer (40) is formed on the sidewalls of the first trench (51) and the third trench (53), wherein the thickness of the thin oxide layer (40) is 50-500 Å.

57. The method of claim 56, further comprising stripping off a thin oxide layer (40) formed on sidewalls of the first trench (51) and the third trench (53).

58. The method according to claim 33, wherein the deposition thickness of the undoped polysilicon (80) is 200-3000 Å.

59. A method according to claim 33, wherein when the first doping type is p-type, the diffusion material (81) includes at least one of POCl3 glass and phosphosilicate glass, and the dopant is phosphorus element; and wherein when the first doping type is n-type, the diffusion material (81) includes borosilicate glass, and the dopant is boron element.

60. The method of claim 33, wherein the dielectric layer (8) comprises tetraethyl orthosilicate or an oxide.

61. The method according to claim 33, wherein the trench oxide layer (44) and the dielectric layer (8) in the first trench (51) form a first deep trench isolation structure (511), and the trench oxide layer (44) and the dielectric layer (8) in the third trench (53) form a third deep trench isolation structure (531).

62. The method of claim 33, wherein the conductive material (84) comprises polysilicon having a first doping type.

63. The method of claim 33, further comprising removing the conductive material (84) on the hard mask layer (4) by a chemical mechanical polishing step.

64. According to the method according to claim 33, a first device region (111) and a second device region (112) are formed in the epitaxial layer (3), wherein the first device region (111) is a high-voltage device region, and the second device region (112) is a low-voltage or medium-voltage device region, wherein a first transistor (112a) and a second transistor (112b) are formed in the second device region (112), and a plurality of isolation regions (91) are formed in the second device region (112) for isolating the first transistor (112a) and the second transistor (112b).

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