Pixel circuit of pulse train image sensor, image sensor and device

Abstract

The disclosed embodiment discloses a pixel circuit, an image sensor and a device of a pulse sequence image sensor, wherein the pixel circuit includes: a light pulse generating module, which is used to convert a light signal into a pulse signal; a pulse width time integration module, which is connected to the light pulse generating module, and is used to convert the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal; a voltage buffer module, which is connected to the pulse width time integration module, and is used to buffer a second voltage signal that meets a preset buffering condition based on the first voltage signal output by the pulse width time integration module; and a buffer voltage output module, which is connected to the voltage buffer module, and is used to output a second voltage signal. The disclosed embodiment can make the photosensitive frequency of the pixel higher than the output frequency of the data, thereby effectively reducing the output data volume on the basis of ensuring the time sensitivity of the pixel, and solving the problem of excessive output data volume in the prior art.

Description

Technical Field

[0001] The present disclosure relates to image sensor technology, and in particular to a pixel circuit, an image sensor and a device of a pulse sequence image sensor. Background Art

[0002] As a neuromorphic vision sensor, the pulse sequence image sensor has the characteristics of high frame rate, which can meet the needs of high-speed imaging and can capture and record high-speed moving targets. Therefore, it has great application value in machine vision and dynamic scene capture. However, in related technologies, if the pulse sequence image sensor wants to achieve a high frame rate, it will face the problem of excessive output data volume. Summary of the invention

[0003] The embodiments of the present disclosure provide a pixel circuit, an image sensor and a device of a pulse sequence image sensor, so as to effectively reduce the output data volume while ensuring a high frame rate.

[0004] In one aspect of an embodiment of the present disclosure, a pixel circuit of a pulse sequence image sensor is provided, comprising:

[0005] An optical pulse generating module, used for converting an optical signal into a pulse signal;

[0006] A pulse width time integration module, connected to the optical pulse generation module, for converting the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal;

[0007] a voltage buffer module, connected to the pulse width time integration module, and configured to buffer a second voltage signal satisfying a preset buffer condition based on the first voltage signal output by the pulse width time integration module;

[0008] A cache voltage output module is connected to the voltage cache module and is used to output the second voltage signal.

[0009] Another aspect of the embodiments of the present disclosure provides a pulse sequence image sensor, comprising:

[0010] A pixel circuit of a pulse sequence image sensor provided by any of the above embodiments corresponding to each pixel;

[0011] A bias current module, used for providing a constant current to the pixel circuit;

[0012] The readout circuit is used to control the pixel circuit of the pulse sequence image sensor corresponding to each pixel to output a second voltage signal.

[0013] According to another aspect of the embodiments of the present disclosure, a device is provided, comprising: a pixel circuit of the pulse sequence image sensor provided by any of the above embodiments, and / or the pulse sequence image sensor provided by any of the above embodiments.

[0014] The pixel circuit, image sensor and device of the pulse sequence image sensor provided by the embodiments of the present disclosure convert the light signal into a pulse signal through a light pulse generating module, convert the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal through a pulse time integration module, and then cache the second voltage signal that meets the preset conditions through a voltage cache module, and output the second voltage signal through a cache voltage output module, so that the photosensitivity frequency of the pixel is higher than the output frequency of the data, thereby effectively reducing the output data volume while ensuring the pixel time sensitivity, thereby solving the problem of excessive output data volume in the prior art.

[0015] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0017] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0018] Figure 1 is a schematic structural diagram of a pixel circuit of a pulse sequence image sensor provided by an exemplary embodiment of the present disclosure;

[0019] Figure 2 is a structural schematic diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure;

[0020] Figure 3 is an exemplary structural diagram of a pulse width time integration module 22 provided by an exemplary embodiment of the present disclosure;

[0021] Figure 4 is a schematic diagram of the structure of a voltage buffer module 23 provided by an exemplary embodiment of the present disclosure;

[0022] Figure 5 is a schematic structural diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure;

[0023] Figure 6 is a structural schematic diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure;

[0024] Figure 7is a schematic diagram of the timing relationship of voltages of key nodes provided by an exemplary embodiment of the present disclosure;

[0025] Figure 8 is a schematic structural diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure;

[0026] Fig. 9 is a structural schematic diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure;

[0027] Fig.10 is a schematic diagram of the timing relationship of voltages of key nodes provided by another exemplary embodiment of the present disclosure;

[0028] Fig.11 is a schematic diagram of simulation results of a pixel circuit provided by an exemplary embodiment of the present disclosure;

[0029] Fig.12 is a schematic structural diagram of a pulse sequence image sensor provided by an exemplary embodiment of the present disclosure;

[0030] Fig.13 is a schematic structural diagram of an application embodiment of the electronic device disclosed herein;

[0031] Fig.14 It is a structural schematic diagram of a pulse camera provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0033] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0034] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0035] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0036] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0037] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0038] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0040] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0041] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] The disclosed embodiments can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0043] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0044] SUMMARY OF THE DISCLOSURE

[0045] In the process of realizing the present disclosure, the inventors discovered that the pulse sequence image sensor, as a neuromorphic vision sensor, has the characteristics of high frame rate, can meet the needs of high-speed imaging, and can capture and record high-speed moving targets. Therefore, it has great application value in machine vision and dynamic scene capture. However, in the related art, if the pulse sequence image sensor wants to achieve a high frame rate, it will face the problem of excessive output data volume.

[0046] Exemplary Overview

[0047] In a scenario where a camera based on a pulse sequence image sensor records information, by utilizing the pixel circuit of the pulse sequence image sensor disclosed herein, the image sensor can output a voltage signal that satisfies the preset cache condition according to the preset cache condition, so that the photosensitivity frequency of the pixel is higher than the output frequency of the data, thereby effectively reducing the output data volume while ensuring the pixel time sensitivity, thereby solving the problem of excessive output data volume in the prior art.

[0048] Figure 1 1 is a schematic diagram of a pixel circuit of a pulse sequence image sensor provided by an exemplary embodiment of the present disclosure. The pixel circuit of the pulse sequence image sensor (hereinafter referred to as pixel circuit) can be applied to a pulse sequence image sensor. Figure 1 As shown, the pixel circuit includes: a light pulse generating module 21 , a pulse width time integration module 22 , a voltage buffer module 23 and a buffer voltage output module 24 .

[0049] An optical pulse generating module 21 is used to convert an optical signal into a pulse signal; a pulse width time integration module 22 is connected to the optical pulse generating module 21 and is used to convert the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal; a voltage buffer module 23 is connected to the pulse width time integration module 22 and is used to buffer a second voltage signal that meets a preset buffering condition based on each first voltage signal output by the pulse width time integration module 22; a buffer voltage output module 24 is connected to the voltage buffer module 23 and is used to output a second voltage signal.

[0050] Among them, the light pulse generating module 21 can be implemented by any feasible circuit structure, for example, it can include a photodiode, a comparator, and a reset unit. The reset unit can be, for example, a reset transistor. The photodiode senses the light intensity during exposure and converts the light signal into an electrical signal, so that the voltage at one end of the photodiode changes. When the voltage reaches the threshold, the comparator outputs a pulse signal, thereby converting the light signal into a pulse signal. The pulse signal disclosed in the present invention refers to a high-level signal. In actual applications, the exposure intensity may be weak and the conditions for outputting a high-level signal may not be met. In this case, a low-level signal may be output, and the low-level signal will not trigger the cache function of the voltage cache module.

[0051] The pulse width time integration module 22 can usually realize integration based on an integrator, and the integrator can be, for example, a capacitor, which can be specifically set according to actual needs. The pulse width time integration module 22 integrates the pulse interval time between two consecutive pulse signals at a fixed rate. When the light intensity is large, the light pulse generating module 21 will generate a pulse signal in a shorter time, so that the pulse interval time between the pulse signal and the previous pulse signal is shorter, and the integration time of the pulse width time integration module 22 is shorter, so that the voltage at one end of the integrator after integration (i.e., the first voltage signal) is larger, so the magnitude of the voltage can be used to characterize the intensity of the light intensity, thereby realizing the conversion of the pulse interval time between two consecutive pulse signals into the corresponding first voltage signal.

[0052] It should be noted that, in order to ensure that the pulse width time integration module 22 can integrate at a fixed rate, it is necessary to provide a constant bias current for the pulse width time integration module 22, and the specific provision method can be set according to actual needs.

[0053] The voltage buffer module 23 can buffer the voltage signal in any feasible manner, such as implementing voltage buffering based on capacitors, or can also implement buffering in other ways, which can be set according to actual needs. The preset buffering condition can also be set according to actual needs, such as the preset buffering condition is the voltage signal corresponding to the maximum light intensity within a preset period, and the preset buffering condition is that the exposure intensity has changed relative to the previous exposure, etc.

[0054] The specific structure of the cache voltage output module 24 can be set according to actual needs, as long as it can output the second voltage signal within a preset period cached by the voltage cache module 23. It can also output other signals according to actual needs. For example, if the exposure intensity changes, a high-level pulse is output. The specific structure can be set according to actual needs.

[0055] The pixel circuit of this embodiment refers to the pixel circuit corresponding to each pixel. In practical applications, the pixel circuits corresponding to each pixel can be set in the pulse sequence image sensor according to the number of pixels of the sensor, and the pixel circuits corresponding to each pixel can be controlled by the readout circuit, so that the second voltage signal that meets the preset cache condition can be read out.

[0056] The pixel circuit of the pulse sequence image sensor provided by the embodiment of the present disclosure converts the light signal into a pulse signal through a light pulse generating module, converts the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal through a pulse time integration module, and then caches a second voltage signal that meets a preset cache condition through a voltage cache module, and outputs the cached second voltage signal through a cache voltage output module, so that the photosensitivity frequency of the pixel is higher than the output frequency of the data, thereby effectively reducing the output data volume while ensuring the pixel time sensitivity, thereby solving the problem of excessive output data volume in the prior art.

[0057] In an optional embodiment, the voltage cache module 23 is specifically used to: cache the second voltage signal corresponding to the maximum light intensity within the preset period based on each first voltage signal output by the pulse width time integration module within the preset period; the cache voltage output module 24 is specifically used to output the second voltage signal when the end time of the preset period is reached.

[0058] In order to further reduce the amount of data output by the image sensor, the present embodiment sets a preset period as the output period. The duration of the preset period can be set according to actual needs. For example, the preset period needs to include at least two exposure periods, which is not specifically limited. Each time exposure occurs, if a pulse signal can be generated, a first voltage signal will be generated. Multiple first voltage signals may be generated within the preset period. The voltage cache module 23 only caches the voltage signal corresponding to the maximum value of the first voltage signal currently generated in the current period after each exposure. The cached voltage signal may be the first voltage signal of the maximum value, or the voltage signal after a certain consumption of the first voltage signal of the maximum value. For example, when a certain device is used to determine whether the first voltage signal currently generated needs to be cached, the device itself needs to consume a certain voltage, and the first voltage signal will be reduced by a certain amount after passing through the device, resulting in the cached voltage signal being less than the first voltage signal of the current maximum value. Since the consumption of the judgment device is fixed, relative to the first voltage signal, the cached voltage signal can also represent the size of the exposure intensity. Based on this, after completing a preset period of time, the voltage cache module 23 caches the voltage signal corresponding to the maximum light intensity in the preset period, and the voltage signal is called the second voltage signal.

[0059] The specific structure of the cache voltage output module 24 can be set according to actual needs, as long as it can output the second voltage signal within a preset period cached by the voltage cache module 23. For example, the cache voltage output module 24 may include a source follower and a row select tube. The row select tube is controlled by a peripheral readout circuit. When the readout circuit detects that the end time of a preset period has been reached, the readout circuit controls the row select tube to turn on (or turn on) to indicate that the pixel has been selected and needs to be output. The source follower is used to follow the cached second voltage signal to output the second voltage signal to the readout circuit.

[0060] The pixel circuit of this embodiment can select the second voltage signal corresponding to the maximum light intensity of the pixel to be read out in a preset period by row and column, so as to represent the maximum light intensity felt by the pixel in the preset period.

[0061] The pixel circuit of the pulse sequence image sensor provided by the embodiment of the present disclosure converts the light signal into a pulse signal through a light pulse generating module, converts the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal through a pulse time integration module, and then caches the second voltage signal corresponding to the first voltage signal of the maximum light intensity in a preset period through a voltage cache module, and outputs the cached second voltage signal of the maximum light intensity after the preset period ends through a cache voltage output module, so that the photosensitivity frequency of the pixel is higher than the output frequency of the data, thereby effectively reducing the output data volume on the basis of ensuring the time sensitivity of the pixel, thereby solving the problem of excessive output data volume in the prior art.

[0062] Figure 2 Detailed description is a schematic diagram of the structure of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure.

[0063] In an optional example, the pulse width time integration module 22 includes: a bias current input unit 221 , a first capacitor 222 and an operational amplifier 223 .

[0064] A bias current input unit 221 is used to output a first constant current; a first capacitor 222, a first end of which is connected to the bias current input unit 221, and the first capacitor 222 is used to be charged under the action of the first constant current during the pulse interval time; an operational amplifier 223, a first input end of which is respectively connected to the bias current input unit 221 and the first end of the first capacitor 222, a first output end of which is connected to the second end of the first capacitor 222, a first reference voltage is input to the second input end, and a first output end outputs a first voltage signal after the first capacitor 222 completes charging during the pulse interval time.

[0065] Among them, Vref1 represents the first reference voltage, I1 represents the first constant current, and during exposure, when the light signal in the light pulse generating module 21 accumulates to a certain threshold, a pulse signal is output, and between the two pulse signals, the first constant current I1 charges the first capacitor 222 and converts the pulse interval into a voltage signal. Specifically, the operational amplifier 223 fixes the voltage of the first end of the first capacitor 222 at the first reference voltage. When the first capacitor 222 is not charged, the voltage of the second end of the first capacitor 222 is the first reference voltage. When the first capacitor 222 is charged, since the voltage of the first end is fixed, as the charging progresses, the plate of the first end of the first capacitor 222 is positively charged, and the plate of the second end is negatively charged, so that the voltage Vc of the second end of the first capacitor 222 decreases from the first reference voltage Vref1 at a fixed rate, for example, decreases to V1, then V1 is the first voltage signal, the light pulse generating module 21 outputs a pulse signal, triggering the voltage cache module 23 to enter the cache stage, the pulse width time integration module 22 outputs the first voltage signal to the voltage cache module 23 for caching, at the beginning of each preset cycle, the cache voltage of the voltage cache module 23 is 0, after the first exposure generates a pulse signal within the preset cycle, the first voltage signal V1 outputted by the pulse width time integration module 22 based on the exposure is cached, so that the cache voltage signal corresponding to V1 is cached to the voltage cache module 23. After caching, the first capacitor 222 of the trigger light pulse generating module 21 and the pulse width time integration module 22 is reset. The triggering reset method can be set according to actual needs, such as delaying the pulse signal for a certain time and transmitting it to the light pulse generating module 21 and the pulse width time integration module 22 to trigger its reset. The specific method can be set according to actual needs. After resetting, the first capacitor 222 starts to charge again. The light pulse generating module generates a second pulse signal after the second exposure. At the second pulse signal, the voltage Vc at the second end of the first capacitor 222 drops to V2. If the second exposure light intensity is greater than the first exposure, the light pulse generating module will generate a second pulse signal in a shorter time. This causes the pulse interval time between the second pulse signal and the first pulse signal to be shorter than the pulse interval time between the first pulse signal and the previous pulse signal. The integration time of the first capacitor 222 is also short, so the degree of Vc decrease is small, then V2 is greater than V1, and the voltage cache module 23 will cache the cache voltage signal corresponding to V2. On the contrary, if the light intensity of the second exposure is less than that of the first exposure, V2 is less than V1, and V2 will not be cached. Similarly, at any time, the voltage signal cached by the voltage cache module 23 is the voltage signal corresponding to the maximum light intensity generated in the current preset cycle. When the preset cycle ends, the voltage cache module 23 caches the second voltage signal corresponding to the maximum light intensity in the preset cycle.

[0066] The present invention provides a constant current to the first capacitor through a bias current input unit, so that the first capacitor can be charged at a fixed rate, and then combined with an operational amplifier, the first voltage signal of the second terminal voltage Vc of the first capacitor after charging is completed can represent the magnitude of the exposure intensity, which is convenient for subsequent caching of the voltage signal corresponding to the maximum light intensity in the preset period, so that the second voltage signal corresponding to the maximum light intensity in the preset period can be output at the end time of the preset period, effectively reducing the amount of data output by the pixel circuit.

[0067] In an optional example, the pulse width time integration module 22 further includes: a first resetting unit 224, which is respectively connected to the optical pulse generating module 21 and the first end and the second end of the first capacitor 222, and is used to reset the first capacitor under the action of the pulse signal.

[0068] Among them, the first reset unit 224 can adopt any feasible reset structure, such as a reset transistor, the gate of the reset transistor is connected to the light pulse generating module 21, so that under the action of the pulse signal, the reset transistor is turned on to discharge the first capacitor 222 and reset it to an uncharged state.

[0069] Optionally, the pulse signal for triggering the first reset unit 224 to turn on may be a pulse signal generated by the optical pulse generating module 21 after a certain delay, so as to provide sufficient time for the caching of the voltage caching module 23 and ensure the accuracy of the caching result of the voltage caching module 23 .

[0070] The present disclosure resets the first capacitor through the reset unit, so that the first capacitor can be repeatedly used to convert the new pulse interval time into a voltage signal, thereby ensuring that the output first voltage signal is accurate and effective.

[0071] Figure 3 Schematic diagram of an exemplary structure of a pulse width time integration module 22 provided by an exemplary embodiment of the present disclosure.

[0072] In an optional example, the pulse width time integration module 22 includes: a bias current unit 225, which is used to provide a second constant current; a second capacitor 226, the first end of which is connected to the bias current unit 225, and the voltage of the second end is set to a second reference voltage, and the second capacitor 226 is used to charge under the action of the second constant current during the pulse interval time. After completing the charging during the pulse interval time, the first end of the second capacitor 226 outputs a first voltage signal; a second reset unit 227, which is respectively connected to the optical pulse generating module 21 and the first end and the second end of the second capacitor 226, and is used to reset the second capacitor 226 under the action of the pulse signal.

[0073] Wherein, Vref2 represents the second reference voltage, I2 represents the second constant current, and during the pulse width interval, the second constant current I2 charges the second capacitor 226, so that the second end plate of the second capacitor is positively charged and the first end plate is negatively charged. Since the second end voltage of the second capacitor 226 is the fixed second control voltage Vref2, the first end voltage of the second capacitor 226 is the variable Vc. As the second capacitor 226 is continuously charged, Vc decreases from Vref2 to a certain value such as the aforementioned V1 or V2 at a fixed rate, and the voltage Vc (the value after the decrease) of the first end of the charged second capacitor 226 is output as the first voltage signal. The specific structure and working principle of the second reset unit 227 are similar to those of the aforementioned first reset unit 224, and will not be repeated here. The bias current unit 225 can use any implementable device as long as it can provide the required second constant current I2 for the second capacitor 226.

[0074] The present disclosure realizes the conversion of the pulse interval time of the pulse width time integration module into a voltage signal based on a bias current unit, a second reset unit and a second capacitor. Compared with the above examples, an operational amplifier is saved, thereby reducing costs and circuit area.

[0075] In an optional example, the voltage buffer module 23 includes: a first selection unit 231 , a first judgment unit 232 and a first buffer unit 233 .

[0076] The first gating unit 231 is connected to the optical pulse generating module 21 and the pulse width time integration module 22 respectively, and is used to be turned on under the action of the pulse signal; the first judging unit 232 is connected to the first gating unit 231, and is used to determine whether the first voltage signal needs to be cached when the first gating unit 231 is turned on; the first cache unit 233 is connected to the first judging unit 232, and is used to cache the cache voltage signal corresponding to the first voltage signal in response to the need for caching of the first voltage signal, and the cache voltage signal is a second voltage signal after reaching the end time of the preset cycle.

[0077] Among them, the first gating unit 231 can adopt any implementable gating device, for example, a gating tube can be adopted, and the gate of the gating tube is connected to the light pulse generating module 21. When the light pulse generating module 21 generates a pulse signal, the pulse signal triggers the gating tube to turn on, and the first voltage signal generated by the pulse width time integration module 22 is output to the first judgment unit 232. The first judgment unit 232 can be implemented by any implementable device, as long as it can determine whether the first voltage signal needs to be cached based on the voltage signal currently cached by the first cache unit 233 and the first voltage signal. For example, the first judgment unit 232 can be implemented by a source follower or a comparator, which can be specifically set according to actual needs, and this embodiment does not limit it. The first cache unit 233 can adopt any device with a cache function, such as a capacitor device, which can be specifically set according to actual needs. When the first judgment unit 232 determines that the first voltage signal needs to be cached, the cache voltage signal corresponding to the first voltage signal is cached to the first cache unit 233, for example, the capacitor is charged by the first voltage signal, so that the capacitor voltage is equal to the cache voltage signal corresponding to the first voltage signal. The cached cache voltage signal may be equal to the first voltage signal or less than the first voltage signal, which is determined according to the specific device of the first judgment unit 232. For example, when the first judgment unit 232 adopts a source follower, since there is a certain threshold voltage consumption between the gate and the source of the source follower, the cached cache voltage signal is equal to the difference between the first voltage signal and the gate-source threshold voltage signal of the source follower. When the first judgment unit 232 does not need consumption, the first voltage signal can be directly cached to the first cache unit 233, for example, by charging the capacitor so that the capacitor voltage is equal to the voltage corresponding to the first voltage signal.

[0078] The present invention discloses a first selection unit that turns on the cache of the trigger voltage signal under the action of a pulse signal, and combines with a first judgment unit to realize the judgment of whether the first voltage signal needs to be cached, thereby ensuring that the cached voltage signal is the voltage signal corresponding to the maximum light intensity generated in the current cycle. When caching is required, the cache voltage signal corresponding to the first voltage signal is cached through the first cache unit, thereby ensuring that at the end of the preset cycle, the first cache unit caches the second voltage signal corresponding to the maximum light intensity in the preset cycle.

[0079] In an optional example, the voltage cache module 23 also includes: a third reset unit 234, which is respectively connected to the peripheral readout circuit and the first end and the second end of the first cache unit 233, and is used to reset the first cache unit 233 after outputting the second voltage signal in each preset period.

[0080] Among them, the specific structure and principle of the third reset unit 234 can be set according to actual needs, referring to the aforementioned first reset unit 224. In this example, the triggering of the third reset unit 234 is controlled by the read-out circuit. When the read-out circuit detects that the end time of the preset cycle has been reached and the second voltage signal is read from the cache voltage output module 24, the third reset unit 234 can be controlled to reset the first cache unit 233 so that the first cache unit 233 can enter the voltage cache of the next cycle.

[0081] The present disclosure resets the first cache unit after each preset cycle, so that the first cache unit can be reused for voltage caching in a new cycle, thereby enabling the pixel circuit to continuously output the second voltage signal corresponding to the maximum light intensity in each cycle, thereby ensuring continuous normal operation of the image sensor.

[0082] Figure 4 is a schematic diagram of the structure of a voltage buffer module 23 provided by an exemplary embodiment of the present disclosure.

[0083] In an optional example, the first judgment unit 232 includes a first source follower 2321, and the first cache unit 233 includes a third capacitor 2331; the first end of the first source follower 2321 is connected to the first selection unit 231, the second end of the first source follower 2321 is connected to the first end of the third capacitor 2331, and the third end of the first source follower 2321 is connected to a preset power supply, so that the voltage of the third end is a preset voltage, and the second end of the third capacitor 2331 is grounded; the first source follower 2321 is used to charge the third capacitor 2331 based on the first voltage signal when the first selection unit 231 is turned on, if the difference between the first voltage signal at its first end and the current voltage signal at its second end is greater than the first threshold voltage of the first source follower 2321, so that the third capacitor 2331 caches the cache voltage signal corresponding to the first voltage signal.

[0084] Wherein, Vpulse represents a pulse signal, Vdd represents a preset voltage provided by a preset power supply, the first judgment unit 232 is implemented by a first source follower 2321, and the first cache unit 233 is implemented by a third capacitor 2331. The second end of the third capacitor 2331 is grounded, the first end of the third capacitor 2331 is connected to the second end (source) of the first source follower 2321, the first end (gate) of the first source follower 2321 is connected to the first selection unit 231, when the first selection unit 231 is turned on, the first end of the first source follower 2321 inputs a first voltage signal, before the first voltage signal is input, the voltage at the second end of the first source follower 2321 is the voltage Vout cached by the third capacitor 2331, when the first voltage signal is input, if the first voltage signal (for example, Vc=V 1) If the difference between Vout and Vout is greater than the first threshold voltage Vt of the first source follower 2321, the third capacitor 2331 will be triggered to charge, so that the voltage signal Vout cached by the third capacitor 2331 is V1-Vt, then Vout is the cache voltage signal corresponding to the current maximum light intensity cached by the third capacitor 2331. As the number of exposures increases, Vout may change continuously to ensure that it is always equal to the cache voltage signal corresponding to the maximum light intensity. When the preset cycle ends, Vout can be used as the second voltage signal corresponding to the maximum light intensity of the preset cycle. If the current first voltage signal is less than the previous first voltage signal, it means that the light intensity of this exposure is less than the previous light intensity, resulting in the difference between the gate voltage and the source voltage of the first source follower 2321 cannot meet the gate-source threshold voltage Vt of the first source follower 2321, so the third capacitor 2331 cannot be charged, so that the third capacitor 2331 keeps caching the cache voltage signal corresponding to the previous stronger light intensity.

[0085] The present invention uses a source follower to determine whether the first voltage signal is cached, and then combines capacitor charging to cache the voltage signal of the maximum light intensity within the cycle, so that the pixel circuit can output the second voltage signal corresponding to the maximum light intensity within the cycle, further reducing the output data volume.

[0086] In an optional example, the third reset unit 234 is connected to the peripheral readout circuit, the first end and the second end of the third capacitor, respectively, and is used to reset the third capacitor 2331 after outputting the second voltage signal in each preset period.

[0087] Among them, Vrst represents the control voltage of the third reset unit 234, which is controlled by the readout circuit. When the third capacitor 2331 needs to be reset, Vrst is controlled to be high level, so that the third reset unit 234 is turned on, so that the third capacitor 2331 is discharged, and the third capacitor 2331 is reset to an uncharged state. After the reset is completed, Vrst is controlled to be low level, so that the third reset unit 234 is turned off, and the third capacitor 2331 is prepared for the next preset cycle by charging the cache voltage signal. Specifically, the readout circuit is responsible for detecting whether the end time of the preset cycle has been reached. When it is detected that the end time of the preset cycle has been reached, the cache voltage output module 24 is controlled to output the second voltage signal finally cached by the voltage cache module 23. After the readout circuit reads the second voltage signal, the third reset unit 234 can be controlled to be turned on by controlling the state of Vrst to reset the third capacitor 2331.

[0088] The present disclosure implements periodic resetting of the third capacitor through the third reset unit, so that the third capacitor can be repeatedly used for voltage caching in a new cycle, thereby enabling the pixel circuit to continuously output the second voltage signal corresponding to the maximum light intensity in each cycle, thereby ensuring continuous normal operation of the image sensor.

[0089] In an optional example, the first judgment unit 232 can also be implemented by a comparator. For example, the first judgment unit 232 is a first comparator, and the two input terminals of the first comparator are respectively connected to the first selection unit and the second end of the third capacitor. The first voltage signal newly generated by the pulse width time integration module is compared with the current voltage of the third capacitor. When the first voltage signal is greater than the current voltage of the third capacitor, the third capacitor is charged based on the first voltage signal, so that the voltage signal corresponding to the new higher light intensity is cached to the third capacitor.

[0090] In an optional example, the cache voltage output module 24 includes: a first row selection unit 241 , a second row selection unit 242 , a second source follower 243 and a third source follower 244 .

[0091] The first row selection unit 241 is used to be turned on or off under the control of the peripheral readout circuit; the second row selection unit 242 is used to be turned on or off under the control of the readout circuit; the second source follower 243 has a first end connected to the voltage cache module 23, a second end connected to the first row selection unit 241, and a third end connected to a preset power supply. The second source follower 243 is used to output the second voltage signal cached by the voltage cache module 23 to the readout circuit when the first row selection unit 241 is turned on; the third source follower 244 has a first end connected to the light pulse generating module 21, a second end connected to the second row selection unit 242, and a third end connected to the preset power supply. The third source follower 244 is used to output the third voltage signal of the photodiode in the light pulse generating module 21 to the readout circuit when the second row selection unit 244 is turned on.

[0092] Among them, Vdd represents the preset voltage provided by the preset power supply, and the working principles of the second source follower 243 and the third source follower 244 are similar to those of the first source follower, which will not be repeated here. The first row selection unit 241 and the second row selection unit 242 can be implemented by a gate tube. Taking the first row selection unit 241 as an example, its gate is connected to the controllable voltage Vs1. When the readout circuit detects that an over-pulse signal is generated in the current preset cycle, the controllable voltage Vs1 of the first row selection unit 241 can be controlled to be a high level, so that the first row selection unit 241 is turned on, and the second source follower 243 transmits the second voltage signal cached by the voltage cache module 23 to the readout circuit through the bus, so that the readout circuit completes the reading of the second voltage signal of the pixel circuit. The same is true for other pixels, which will not be repeated one by one. When the readout circuit detects that no pulse signal is generated within the current preset cycle, the cache result in the voltage cache module 23 is 0, and the readout circuit can control the gate controllable voltage Vs2 of the second row selection unit 242 to be high, and keep the gate controllable voltage Vs1 of the first row selection unit 241 to be low, to indicate that the second row selection unit 242 is selected, and the gate of the third source follower 244 connected to the second row selection unit 242 is connected to the optical pulse generating module 21, so that the third voltage signal of the photodiode of the optical pulse generating module 21 is output to the readout circuit through the column bus.

[0093] The present invention uses two row selection units and two source followers to realize that if a pulse signal is generated within any preset period, the second voltage signal corresponding to the maximum light intensity is read out, and if no pulse signal is generated, the third voltage signal of the photodiode can be read out. The third voltage signal can be used for subsequent analysis of changes in the photodiode voltage to improve user experience.

[0094] Figure 5 4 is a schematic structural diagram of a pixel circuit of a pulse sequence image sensor provided by yet another exemplary embodiment of the present disclosure.

[0095] In an optional example, the pixel circuit of the pulse sequence image sensor disclosed in the present invention also includes: a delay module 25; the delay module 25 is respectively connected to the light pulse generating module 21 and the pulse width time integration module 22, and is used to delay the pulse signal for a first time and then transmit it to the light pulse generating module 21 and the pulse width time integration module 22, so as to reset the light pulse generating module 21 and the pulse width time integration module 22.

[0096] The delay module 25 can be implemented in any feasible manner, for example, an inverter chain can be used to implement the delayed trigger reset of the pulse signal, which can be specifically configured according to actual needs.

[0097] The present invention delays the pulse signal generated by the optical pulse generating module for a certain period of time before triggering the reset of the optical pulse generating module and the pulse width time integration module, so as to ensure that the voltage cache module can successfully complete the voltage cache, thereby ensuring the accuracy and effectiveness of the output second voltage signal.

[0098] In an optional example, the optical pulse generating module 21 includes: a fourth resetting unit 211 , a photodiode 212 , and a second comparator 213 .

[0099] A fourth reset unit 211, wherein a first end of the fourth reset unit 211 is connected to an output end of the delay module 25, a second end of the fourth reset unit 211 is connected to a second end of the photodiode 212, and a third end of the fourth reset unit 211 is connected to a preset power supply; a first end of the photodiode 212 is grounded, and the photodiode 212 is used to convert an optical signal into an electrical signal so that a voltage signal at a second end of the photodiode 212 changes with an exposure time; a second comparator 213 is used to compare a voltage signal at a second end of the photodiode 212 with a second threshold voltage signal, and output a pulse signal when the voltage signal at the second end of the photodiode 212 is equal to the second threshold voltage signal; an input end of the delay module 25 is connected to an output end of the second comparator 213, and an output end of the delay module 25 is also connected to a first reset unit 224 of the pulse width time integration module 22, and the delay module 25 is used to delay a pulse signal output by the second comparator 213 by a first time and transmit it to the first reset unit 224 and the fourth reset unit 211, so as to reset the capacitance of the photodiode and the pulse width time integration module 22.

[0100] Wherein, Vth represents the second threshold voltage signal, and Vdd represents the preset voltage provided by the preset power supply. The first time can be set according to actual needs. The first time setting principle is to be greater than the cache time of the voltage cache module 23 to ensure that the voltage cache module 23 can successfully complete the cache of the voltage signal, which is not specifically limited. The specific structure of the fourth reset unit 211 can be set according to actual needs, refer to the aforementioned first reset unit 224, and will not be repeated here. The photodiode 212 can adopt any feasible photodiode, which can be set according to actual needs. After resetting, the voltage Vpd at the first end of the photodiode 212 is the reset voltage Vdd. When no pulse signal reaches the fourth reset unit 211, the fourth reset unit 211 is turned off. During exposure, the photodiode senses the light signal and converts the light signal into an electrical signal, so that Vpd continuously decreases from the reset voltage. After a certain exposure time, Vpd drops to Vth, triggering the second comparator 213 to output a pulse signal Vpulse=Vh (high level), and the first selection unit 231 is turned on, and then the cache stage is started. The time required for the cache stage can be expressed as tw. The specific value of tw is determined according to the cache device in the voltage cache module 23, such as a capacitor, which takes a certain amount of time to charge. When the voltage buffer After the cache is completed, the storage module 23 enters the reset stage, and the photodiode of the light pulse generating module 21 and the integral capacitor of the pulse width time integration module 22 are reset. The time required for the reset stage is expressed as tr, and the specific value of tr is determined according to the delay time of the delay module and the time tw required for the cache stage. Since the delay time (the aforementioned first time) is greater than the time tw required for the cache stage, after the cache is completed, the reset pulse has not yet reached the fourth reset unit 211 of the light pulse generating module 21 and the first reset unit 224 of the pulse width time integration module 22. Reset can only be performed after the pulse signal reaches the two reset units. During reset, it also takes a certain amount of time for the capacitor to discharge, so reset requires a certain amount of time.

[0101] The present disclosure realizes that the light pulse generating module converts the light signal into a pulse signal through the photodiode, the second comparator and the fourth reset unit, and then ensures the continuous operation of the light pulse generating module through reset, thereby providing necessary support for the normal operation of the image sensor.

[0102] In an optional example, the delay module 25 may also be a module in the optical pulse generating module 21 , and may be specifically configured according to actual requirements.

[0103] In an optional example, the delay module 25 can be implemented by an inverter chain or other structures, such as a clock-based counter. It can be set according to actual needs as long as it can delay the pulse signal for a certain period of time and then reset the capacitor of the photodiode and the pulse width time integration module.

[0104] In an alternative example, Figure 6 1 is a schematic diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure. In which, Col_bus represents a column bus connected to the readout circuit, C1 represents a first capacitor 222, Vref represents a first reference voltage, SF0, SF1, and SF2 represent a first source follower 2321, a second source follower 243, and a third source follower 244, respectively, C2 represents a third capacitor 2331, T1 represents a first selection unit 231, T2 represents a bias current input unit 221, T3 is a peripheral bias current introduction tube, and Id represents a constant current source, which is symmetrical with T2 and converts the first current provided by the constant current source Id into a bias current input tube. The constant current I is input to the pulse width time integration module; Row_sel represents the row selection unit, the left side is the first row selection unit 241 and the right side is the second row selection unit 242; PD represents the photodiode 212; R1 represents the first reset unit 224, R2 represents the third reset unit 234, and R3 represents the fourth reset unit 211; the delay module is implemented by an inverter chain, specifically by two inverters in cascade; Vth corresponds to the second threshold voltage signal of the second comparator 213, and Vref corresponds to the first reference voltage of the operational amplifier 223. The working principle of each part can be found in the above content, which will not be repeated here.

[0105] For example, Figure 7 It is a schematic diagram of the voltage timing relationship of key nodes provided by an exemplary embodiment of the present disclosure. Among them, V3 represents the value to which Vc drops after the third exposure C1 is charged, t1 represents the time required for Vpd to reach Vth in the first exposure, t2 represents the time required for Vpd to reach Vth in the second exposure, and t3 represents the time required for Vpd to reach Vth in the third exposure; the specific meanings of other symbols can be found in the above content, which will not be repeated here. During the t1 time, Vc drops from Vref to V1 at a fixed rate. When Vpd reaches Vth, Vpulse becomes a high level (pulse signal), triggering T1 to turn on and enter the cache stage. After V1 charges Vout to V1-Vt through the source follower SF0, SF0 is cut off, C2 is no longer charged, and the time required for the cache stage is tw (i.e., t w ), then enter the reset phase to reset Vpd and Vc. The time required for the reset phase is t r(i.e., tr), repeat the above process. If the light intensity increases during the second exposure, the time required for Vpd to reach Vth shortens, and the decrease in Vc becomes smaller, i.e., V2 > V1. Then, the gate-source voltage of the source follower SF0 is greater than its threshold voltage Vt, and the source follower SF0 conducts, charging Vout to V2 - Vt. If the light intensity weakens during the third exposure, then V3 < V2, and the gate-source voltage of the source follower SF0 is less than its threshold voltage Vt, and the source follower SF0 cuts off, and Vout will continue to remain at V2 - Vt. After the end of a readout period (preset period), the voltage cached on Vout can represent the strongest light intensity within that period.

[0106] In an alternative embodiment, the voltage caching module 23 is specifically configured to: determine the current second voltage signal based on the first voltage signal output by the pulse-width time integration module 22, and cache the current second voltage signal as the new second voltage signal. The cached voltage output module 24 is specifically configured to output the cached second voltage signal that meets the preset conditions.

[0107] Among them, the current second voltage signal can be the difference between the cached second voltage signal and the current integration amount. The current integration amount is the integration amount of the pulse-width time integration module 22 during the current most recent exposure time. Exemplarily, after resetting the pulse-width time integration module 22 after the first exposure, the second voltage signal cached by the voltage caching module 23 is V ref represents the reference voltage, t1 represents the integration time of the first capacitor 222 during the first exposure, I c represents the charging current of the first capacitor, which is equal to the aforementioned first constant current I1, C1 represents the capacitance value of the first capacitor. For the second exposure, the integration amount of the pulse-width time integration module 22 is t2 represents the integration time of the first capacitor 222 during the second exposure, then the second voltage signal is The caching of the second voltage signal can be achieved through a capacitor. The preset condition can be that the difference between the cached second voltage signal and the reference voltage (such as ) is not 0 or the absolute value of the difference is greater than the threshold. Then, the cached voltage output module 24 can output the cached second voltage signal that meets the preset conditions. It can be seen that the difference between the second voltage signal and the reference voltage characterizes the strength of the exposure intensity during the second exposure relative to the exposure intensity during the first exposure. When the difference is greater than 0, it indicates that the exposure intensity during the second exposure is greater than that during the first exposure. When the difference is less than 0, it indicates that the exposure intensity during the second exposure is less than that during the first exposure. When the difference meets the preset conditions, the cached second voltage signal is output.

[0108] In an alternative embodiment, it is also possible to based on the difference between the cached new second voltage signal and the reference voltage v refA comparison is performed, and in response to the comparison result satisfying a preset condition, a target voltage signal is output. The target voltage signal is used to characterize that the most recent exposure intensity has changed relative to the previous exposure intensity, or the amount of change exceeds a threshold. The target voltage signal can be set according to actual needs, for example, it can be a high-level pulse, so that sparse pulses can be output as the exposure continues.

[0109] In an optional embodiment, the voltage cache module 23 is specifically used to: based on the first voltage signal output by the pulse width time integration module 22, cache the difference between the pulse width time integration amount of the current exposure and the previous exposure corresponding to the first voltage signal as a new second voltage signal, or cache the difference between the pulse width time integration amount of the previous exposure and the current exposure as a new second voltage signal.

[0110] The current exposure refers to the most recent exposure, and the previous exposure refers to the exposure before the current exposure. For example, if the current exposure is the third exposure, the previous exposure is the second exposure. The pulse width time integral refers to the integral generated by the pulse width time integral module 22 during the exposure. For example, the first capacitor of the pulse width time integral module is charged at a fixed rate under the action of a constant current to generate the integral. For example, the pulse width time integral of the i-1th exposure is The pulse width time integral of the i-th exposure is If the current exposure is the i-th exposure, then or The second voltage signal is used as a new buffer. The specific buffering method and buffering structure can be set according to actual needs.

[0111] This embodiment implements the buffering of the difference between the pulse width time integrals of two exposures, so as to facilitate the output of sparse pulses with varying light intensities.

[0112] In an optional embodiment, the voltage buffer module is specifically used for:

[0113] Based on the first voltage signal output by the pulse width time integration module, if it is determined that the pulse width time integration amount of the current exposure corresponding to the first voltage signal is different from the pulse width time integration amount of the previous exposure, the pulse width time integration amount of the current exposure is cached as a new second voltage signal.

[0114] Among them, after the previous exposure, the pulse width time integral of the previous exposure can be cached. After the current exposure, the pulse width time integral of the current exposure can be compared with the cached pulse width time integral of the previous exposure to determine whether the pulse width time integral of the current exposure is the same as the pulse width time integral of the previous exposure. If they are the same, the cached integral can be kept. If they are not the same, the pulse width time integral of the current exposure can be cached as a new second voltage signal. The specific caching method and caching structure can be set according to actual needs.

[0115] Exemplarily, the pulse width time integral of the i-1th exposure is The pulse width time integral of the i-th exposure is If the current exposure is the i-th exposure, it can be judged that or Is it 0? If not, you can The signal is buffered as a new second voltage signal.

[0116] This embodiment implements the cache of the pulse width time integral of the light intensity change, which is convenient for the user to understand the light intensity change and the sparse pulses of the output light intensity change.

[0117] Figure 8 4 is a schematic structural diagram of a pixel circuit of a pulse sequence image sensor provided by yet another exemplary embodiment of the present disclosure.

[0118] In an optional embodiment, the voltage cache module 23 includes: a voltage buffer 235 and a fourth capacitor 236 ; and the cache voltage output module 24 includes a third comparator 245 .

[0119] The first input terminal of the voltage buffer 235 is connected to the pulse width time integration module 22, the second input terminal of the voltage buffer 235 is connected to the first output terminal of the voltage buffer 235, the first output terminal of the voltage buffer 235 is connected to the first terminal of the fourth capacitor 236, and the voltage buffer 235 is used to transmit the first voltage signal to the first terminal of the fourth capacitor 236.

[0120] A second terminal of the fourth capacitor 236 is connected to the first input terminal of the third comparator 245 , and the fourth capacitor 236 is used to cache the current second voltage signal as a new second voltage signal.

[0121] The second input terminal of the third comparator 245 is connected to the third reference voltage. The third comparator 245 is used to compare the new second voltage signal with the third reference voltage, and output a light intensity change pulse signal if the comparison result meets a preset condition.

[0122] The voltage buffer module 23 is further configured to output a first voltage signal.

[0123] The voltage buffer 235 can be implemented by any feasible structure, and its function is to maintain the voltage V at its first output terminal. c2 =V c1 , realizing the transmission of the first voltage signal output by the pulse width time integration module 22 to the first end of the fourth capacitor 236. The third comparator 245 can be implemented by any feasible structure, and Vref3 represents the third reference voltage. The output of the light intensity change pulse signal indicates that the current exposure intensity has changed relative to the previous exposure intensity or the change amount meets the preset condition. After the i-th exposure is completed, Vc2 decreases to Vi along with Vc1, and Vc3 increases from the cached second voltage signal The new second voltage signal is converted into a cache

[0124] In this embodiment, at the end of each exposure, the cached second voltage signal is updated once, and a new second voltage signal can be output. A sparse pulse representing the change in exposure intensity or the change in exposure intensity meeting certain conditions can be output through a third comparator, so as to facilitate understanding of the change in exposure intensity.

[0125] In an optional embodiment, the circuit of the present disclosure further includes a delay module 25 ; the voltage buffer module further includes a fifth reset unit 237 and a sixth reset unit 238 .

[0126] The time delay module 25 is used to delay the pulse signal output by the optical pulse generating module 21 by a first time and then transmit it to the sixth reset unit.

[0127] The fifth resetting unit 237 is connected to the second end of the fourth capacitor 236 and the optical pulse generating module 21 respectively, and is used to reset the voltage of the second end of the fourth capacitor 236 to the third reference voltage under the action of the pulse signal of the optical pulse generating module 21 .

[0128] The sixth reset unit 238 is connected to the delay module 25, the second input terminal and the first output terminal of the voltage buffer 235 respectively, and is used to reset the voltage of the first output terminal of the voltage buffer 235 to the third reference voltage under the action of the delayed pulse signal.

[0129] When the voltage at the first output terminal of the voltage buffer 235 is reset to the third reference voltage, the voltage at the second terminal of the fourth capacitor 236 becomes the third voltage, and the third voltage is cached as a new second voltage signal.

[0130] The specific structures and working principles of the fifth reset unit 237 and the sixth reset unit 238 are similar to those of the first reset unit 224, and are not described in detail here. After the exposure is completed and the second voltage signal and the sparse pulse are output, the fifth reset unit 237 is driven to turn on by the pulse signal output by the light pulse generating module 21, and the second terminal voltage Vc3 of the fourth capacitor 236 is reset to the third reference voltage. After the pulse signal is delayed for a first time by the delay module 25, the first reset unit 224 of the first capacitor and the sixth reset unit 238 of the voltage buffer 235 are triggered to turn on, and the first capacitor 222 and the voltage buffer 235 are reset. The first output terminal voltage of the voltage buffer 235 is is reset to the third reference voltage V ref3 , and at the same time reset Vc2 Coupled to Vc3, so that Vc3 caches the third voltage As the buffered second voltage signal required for the next exposure.

[0131] For example, Fig. 9 : is a structural schematic diagram of a pixel circuit of a pulse sequence image sensor provided by another exemplary embodiment of the present disclosure. Among them, Vref3 represents the third reference voltage, Vref1 represents the first reference voltage, Vref3=Vref1, Vc1 represents the output terminal voltage of the operational amplifier 223 of the pulse width time integration module 22, and the output event detection result represents the light intensity change pulse signal output by the third comparator. The meanings of other symbols refer to the above content and will not be repeated here.

[0132] Fig.10 : is a schematic diagram of the timing relationship of the voltages of key nodes provided by another exemplary embodiment of the present disclosure. Wherein, Vref represents the third reference voltage Vref3, and the specific process is as follows:

[0133] 1. At the end of the first exposure, the exposure time of the first exposure is expressed as t1, which is determined by the characteristics of the photodiode and the exposure intensity. After resetting Vc3, and resetting Vc1 and Vc2, That is, the second voltage signal that has been buffered during the second exposure.

[0134] 2. At the end of the second exposure, the exposure time is expressed as t2.

[0135] 3. The third comparator determines and decides whether to output a light intensity change pulse signal.

[0136] 4. Reset Vc3, Vc3 = Vref3.

[0137] 5. Reset Vc1 and Vc2, Vc2 = Vc1 = Vref3, and

[0138] 6. The third exposure ends.

[0139] 7. Vc3 resets, and after the first delay, Vc1 and Vc2 reset.

[0140] Fig.11 : is a schematic diagram of the simulation results of a pixel circuit provided by an exemplary embodiment of the present disclosure. Among them, Vspike represents the inverted delayed pulse signal output by the delay module, and the coefficient pulse is the light intensity change pulse signal output by the third comparator. It can be seen that after the exposure is completed, if the updated second voltage signal is near the third reference voltage, it means that the current light intensity and the previous light intensity change amount do not meet the preset conditions, so the light intensity change pulse signal will not be output. Thereby reducing the output data volume.

[0141] It should be noted that the above-mentioned embodiments or optional examples of the present disclosure may be implemented separately, or may be implemented in combination in any combination without conflict, and may be specifically configured according to actual needs.

[0142] Fig.12 1 is a schematic diagram of the structure of a pulse sequence image sensor provided by an exemplary embodiment of the present disclosure. The pulse sequence image sensor may include: a pixel circuit 20 of the pulse sequence image sensor provided by any of the above embodiments or optional examples corresponding to each pixel; a bias current module 31, used to provide a constant current to the pixel circuit; and a readout circuit 32, used to control the pixel circuit 20 of the pulse sequence image sensor corresponding to each pixel to output a second voltage signal.

[0143] The specific structure of the pixel circuit 20 of the pulse sequence image sensor is shown in the above-mentioned embodiment or optional example, which will not be described in detail here. The bias current module 31 can be set according to actual needs, for example, Figure 6 , T3 and Id constitute a bias current module 31. In practical applications, other implementations may also be adopted, which are not limited by the present disclosure. The specific structure of the readout circuit can be based on a conventional readout circuit structure, and the control functions related to the present disclosure are added, which can be specifically set according to actual needs.

[0144] Optionally, the readout circuit 32 is also used to detect whether the end time of the current preset cycle has been reached. When it is detected that the end time of the current preset cycle has been reached, it is determined whether a pulse signal is generated within the current preset cycle. When it is determined that a pulse signal is generated, the pixel circuit 20 corresponding to each pixel is controlled to output a second voltage signal. When it is determined that no pulse signal is generated within the current preset cycle, the pixel circuit 20 is controlled to output a third voltage signal of the photodiode. The specific control principle refers to the aforementioned embodiment and will not be repeated here.

[0145] In practical applications, the pulse sequence image sensor may also include other possible components, which are not limited in the present disclosure.

[0146] In addition, an embodiment of the present disclosure further provides an electronic device, comprising: the pulse sequence image sensor provided by any of the above embodiments. The electronic device may also include: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the output signal of the pulse sequence image sensor described in any of the above embodiments of the present disclosure is processed to achieve the desired function.

[0147] Fig.13 FIG. 1 is a schematic diagram of a structure of an application embodiment of the electronic device disclosed in the present invention. Fig.13 As shown, the electronic device includes one or more processors 11 and a memory 12, and the pulse sequence image sensor 30 provided in the above-mentioned embodiment.

[0148] The processor 11 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0149] The memory 12 may store one or more computer program products, and the memory 12 may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program products to implement the desired functions described above.

[0150] In one example, the electronic device may further include: an input device 13 and an output device 14, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0151] In addition, the input device 13 may also include, for example, a keyboard, a mouse, and the like.

[0152] The output device 14 can output various information to the outside, including the determined distance information, direction information, etc. The output device 14 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0153] Of course, to simplify, Fig.13 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0154] In another embodiment of the present disclosure, a device is also provided, which includes the pixel circuit of the above-mentioned pulse sequence image sensor, and / or includes the above-mentioned pulse sequence image sensor, and / or a chip having the pixel circuit of the above-mentioned pulse sequence image sensor.

[0155] Specifically, the device includes at least one of the following: camera, webcam, audio / video player, navigation device, fixed location terminal, entertainment device, smart phone, communication device, mobile device, transportation vehicle or facility, industrial equipment, medical equipment, security equipment, flight equipment, household appliance.

[0156] In the embodiments of the present disclosure, the camera includes but is not limited to a pulse camera, a high-speed camera, an industrial inspection camera, etc. The camera includes but is not limited to: a car camera, a mobile phone camera, a traffic camera, a camera mounted on a flying object, a medical camera, a security camera, or a home appliance camera.

[0157] Taking a pulse camera as an example, the device provided by the embodiment of the present disclosure is described in detail. Fig.14 is a schematic diagram of the structure of a pulse camera provided by an exemplary embodiment of the present disclosure. Fig.14 As shown, the pulse camera includes: a lens 1201, a pulse signal circuit 1202, a data processing circuit 1203, a non-volatile memory 1204, a power circuit 1205, a volatile memory 1206, a control circuit 1207 and an I / O interface 1208.

[0158] The lens 1201 is used to receive incident light from the object, that is, the optical signal.

[0159] The pulse signal circuit 1202 is used to convert the optical signal received by the lens 1201 into an electrical signal, and generate a pulse signal according to the electrical signal. The pulse signal circuit 1202 includes, for example, the pixel circuit of the pulse sequence image sensor described above, and / or the pulse sequence image sensor described above, and / or a chip having the pixel circuit of the pulse sequence image sensor described above.

[0160] The data processing circuit 1203 is used to control the pulse signal reading process. The data processing circuit 1203 includes, for example: an arithmetic processing unit (for example, a CPU) and / or an image processing unit (GPU). For example, it controls the pulse signal reading process of the pulse signal reading circuit, controls the read row selector therein to send a row read signal, controls the reset row selector to send a column reset signal, etc.

[0161] 1206 is a volatile memory, such as a random access memory (RAM), and 1204 is a non-volatile storage device, such as a solid state disk (SSD), a hybrid hard disk (HHD), a secure digital (SD) card, a mini SD card, etc.

[0162] In one embodiment of the present invention, the pulse camera further comprises: a display unit for real-time / playback display of the pulse signal / image information. The pulse camera described in the embodiment of the present invention may further comprise at least one of the following: a wired / wireless transmission interface, such as a WiFi interface, a Bluetooth interface, a USB interface, an RJ45 interface, a mobile industry processor interface (MIPI) interface, a low voltage differential signal (LVDS) interface, and other interfaces with wired or wireless transmission functions.

[0163] The pulse camera provided in the embodiment of the present invention can be used to detect visible light, infrared light, ultraviolet light, X-rays, etc., and can be applied to various scenarios. Commonly used scenarios include but are not limited to:

[0164] It can be used as an on-board camera installed in various types of transportation vehicles or facilities, such as for vehicle-road collaboration, smart transportation, and information acquisition and control of autonomous driving. For example, it can be installed in rail transportation vehicles such as high-speed rail or on rail transportation lines as a high-speed rail driving recorder; it can also be installed in autonomous vehicles or vehicles equipped with advanced driver assistance systems (ADAS), such as for detection and alarm of vehicle, pedestrian, lane, driver and other information.

[0165] It can be used as a traffic camera installed on traffic signal poles to capture, warn, and coordinate control of vehicles and pedestrians on urban roads and highways.

[0166] It can be used as an industrial inspection camera, for example, installed on high-speed rail transit lines for high-speed rail line inspection and for high-speed rail safety inspection; it can also be used for coal mine conveyor belt break detection, substation arc detection, real-time detection of wind turbine blades, high-speed turbine non-stop detection and other specific industrial scenarios detection, early warning, etc.

[0167] It is installed on flying objects, such as airplanes, satellites, etc., and is used for high-definition imaging of objects in high-speed flight or even high-speed rotation scenarios.

[0168] Industry (machine vision in intelligent manufacturing, etc.), civil (judicial evidence collection, sports refereeing, etc.) and consumer electronics (cameras, film and television media, etc.).

[0169] It can be used as a medical camera to perform high-definition medical imaging in clinical diagnosis and treatment such as medicine, beauty, and health care.

[0170] It can be used as a sports camera or a wearable camera, for example, a head-mounted camera or a camera embedded in a watch, and can be used to shoot various sports competitions, daily leisure sports and other scenes.

[0171] It can also be used as a security camera, mobile phone camera or home appliance camera, etc.

[0172] The flow charts and block diagrams in the accompanying drawings of the present disclosure show the possible architecture, functions and operations of the systems, methods and computer program products according to the various embodiments disclosed in the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the boxes can also occur in the order of the standards in different drawings. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0173] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to perform steps in the desired functions according to various embodiments of the present disclosure described in the above part of this specification.

[0174] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0175] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to perform the steps of the desired functions according to the embodiment of the present disclosure described in the above part of this specification.

[0176] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0177] A person of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned desired functions can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, which, when executed, executes the steps including the above-mentioned desired functions; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0178] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0179] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0180] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0181] The method and apparatus of the present disclosure may be implemented in many ways. For example, the circuits and desired functions of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the desired functions is for illustration only, and the steps of the desired functions of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the desired functions according to the present disclosure. Therefore, the present disclosure also covers recording media storing programs for executing methods according to the present disclosure.

[0182] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0183] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0184] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A pixel circuit of a pulse sequence image sensor, characterized in that: include: An optical pulse generating module, used for converting an optical signal into a pulse signal; A pulse width time integration module, connected to the optical pulse generation module, for converting the pulse interval time between two consecutive pulse signals into a corresponding first voltage signal; a voltage buffer module, connected to the pulse width time integration module, and configured to buffer a second voltage signal satisfying a preset buffer condition based on the first voltage signal output by the pulse width time integration module; a cache voltage output module, connected to the voltage cache module, and configured to output the second voltage signal; Wherein, the pulse width time integration module comprises: A bias current unit, used for providing a constant current; A capacitor, a first end of which is connected to the bias current unit, and the capacitor is used to be charged under the action of the constant current during the pulse interval; The reset unit is connected to the optical pulse generating module and the first end and the second end of the capacitor respectively, and is used for resetting the capacitor under the action of the pulse signal.

2. The circuit according to claim 1, characterized in that The voltage buffer module is specifically used for: Based on each of the first voltage signals output by the pulse width time integration module within a preset period, a second voltage signal corresponding to the maximum light intensity within the preset period is cached; The cache voltage output module is specifically configured to output the second voltage signal when the end time of the preset period is reached.

3. The circuit according to claim 1, characterized in that The bias current unit is a bias current input unit, used to output a first constant current; the capacitor is a first capacitor; The first capacitor has a first end connected to the bias current input unit, and the first capacitor is used to be charged under the first constant current during the pulse interval; The pulse width time integration module also includes: An operational amplifier, wherein the first input terminal is respectively connected to the bias current input unit and the first terminal of the first capacitor, the first output terminal is connected to the second terminal of the first capacitor, the second input terminal inputs a first reference voltage, and the first output terminal outputs the first voltage signal after the first capacitor completes charging for the pulse interval time.

4. The circuit according to claim 1, characterized in that The bias current unit is used to provide a second constant current; the capacitor is a second capacitor; The second capacitor has a first end connected to the bias current unit, and a second end voltage set to a second reference voltage. The second capacitor is used to be charged under the action of the second constant current during the pulse interval time. After completing the charging during the pulse interval time, the first end of the second capacitor outputs the first voltage signal.

5. The circuit according to claim 2, characterized in that The voltage buffer module comprises: A first gating unit, connected to the optical pulse generating module and the pulse width time integration module respectively, and configured to be turned on under the action of the pulse signal; A first judgment unit, connected to the first gating unit, for determining whether the first voltage signal needs to be cached when the first gating unit is turned on; The first cache unit is connected to the first judgment unit and is used to cache a cache voltage signal corresponding to the first voltage signal in response to the need to cache the first voltage signal, and the cache voltage signal is the second voltage signal after reaching the end time of the preset cycle.

6. The circuit according to claim 5, characterized in that The first judgment unit includes a first source follower, and the first cache unit includes a third capacitor; The first end of the first source follower is connected to the first gating unit, the second end of the first source follower is connected to the first end of the third capacitor, the third end of the first source follower is connected to a preset power supply, so that the voltage of the third end is a preset voltage, and the second end of the third capacitor is grounded; The first source follower is used to charge the third capacitor based on the first voltage signal when the first selection unit is turned on, if the difference between the first voltage signal at its first end and the current voltage signal at its second end is greater than the first threshold voltage of the first source follower, so that the third capacitor caches the cached voltage signal corresponding to the first voltage signal.

7. The circuit according to claim 6, characterized in that The voltage buffer module further includes: The third reset unit is connected to the peripheral readout circuit, the first end and the second end of the third capacitor respectively, and is used to reset the third capacitor after outputting the second voltage signal in each preset period.

8. The circuit according to claim 2, characterized in that The cache voltage output module comprises: A first row selection unit, used to be turned on or off under the control of a peripheral readout circuit; A second row selection unit, used to be turned on or off under the control of the readout circuit; a second source follower, a first end of which is connected to the voltage cache module, a second end of which is connected to the first row selection unit, and a third end of which is connected to a preset power supply, the second source follower being used to output the second voltage signal cached by the voltage cache module to the readout circuit when the first row selection unit is turned on; A third source follower, a first end connected to the optical pulse generating module, a second end connected to the second row selection unit, and a third end connected to the preset power supply. The third source follower is used to output the third voltage signal of the photodiode in the optical pulse generating module to the readout circuit when the second row selection unit is turned on.

9. The circuit according to claim 1, characterized in that Also includes: The time delay module is connected to the optical pulse generating module and the pulse width time integration module respectively, and is used to transmit the pulse signal to the optical pulse generating module and the pulse width time integration module after delaying the pulse signal for a first time, so as to reset the optical pulse generating module and the pulse width time integration module.

10. The circuit according to claim 9, characterized in that The optical pulse generating module comprises: a fourth reset unit, wherein a first end of the fourth reset unit is connected to the output end of the delay module, a second end of the fourth reset unit is connected to the second end of the photodiode, and a third end of the fourth reset unit is connected to a preset power supply; A photodiode, a first end of which is grounded, and the photodiode is used to convert an optical signal into an electrical signal so that a voltage signal at the second end of the photodiode changes with exposure time; a second comparator, configured to compare the voltage signal at the second end of the photodiode with a second threshold voltage signal, and output the pulse signal when the voltage signal at the second end of the photodiode is equal to the second threshold voltage signal; The input end of the delay module is connected to the output end of the second comparator, and the output end of the delay module is also connected to the first reset unit of the pulse width time integration module. The delay module is used to delay the pulse signal output by the second comparator for a first time and transmit it to the first reset unit and the fourth reset unit to reset the photodiode and the capacitor of the pulse width time integration module.

11. The circuit according to claim 1, characterized in that The voltage buffer module is specifically used for: Determine a current second voltage signal based on the first voltage signal output by the pulse width time integration module, and cache the current second voltage signal as a new second voltage signal; The cache voltage output module is specifically used to output the cached second voltage signal that meets a preset condition.

12. The circuit according to claim 11, characterized in that The voltage buffer module is specifically used for: Based on the first voltage signal output by the pulse width time integration module, the difference between the pulse width time integration amount of the current exposure and the previous exposure corresponding to the first voltage signal is cached as a new second voltage signal, or the difference between the pulse width time integration amount of the previous exposure and the current exposure is cached as a new second voltage signal.

13. The circuit according to claim 11, characterized in that The voltage buffer module is specifically used for: Based on the first voltage signal output by the pulse width time integration module, if it is determined that the pulse width time integration amount of the current exposure corresponding to the first voltage signal is different from the pulse width time integration amount of the previous exposure, the pulse width time integration amount of the current exposure is cached as a new second voltage signal.

14. The circuit according to claim 11, characterized in that The voltage buffer module includes: a voltage buffer and a fourth capacitor; The cache voltage output module includes a third comparator; The first input terminal of the voltage buffer is connected to the pulse width time integration module, the second input terminal of the voltage buffer is connected to the first output terminal of the voltage buffer, the first output terminal of the voltage buffer is connected to the first terminal of the fourth capacitor, and the voltage buffer is used to transmit the first voltage signal to the first terminal of the fourth capacitor; The second end of the fourth capacitor is connected to the first input end of the third comparator, and the fourth capacitor is used to cache the current second voltage signal as a new second voltage signal; The second input terminal of the third comparator is connected to a third reference voltage, and the third comparator is used to compare the new second voltage signal with the third reference voltage, and output a light intensity change pulse signal if the comparison result meets a preset condition; The voltage buffer module is further configured to output the first voltage signal.

15. The circuit according to claim 14, characterized in that It also includes a delay module; the voltage cache module also includes a fifth reset unit and a sixth reset unit; The delay module is used to delay the pulse signal output by the optical pulse generating module for a first time and transmit it to the sixth reset unit; The fifth resetting unit is connected to the second end of the fourth capacitor and the optical pulse generating module respectively, and is used for resetting the voltage of the second end of the fourth capacitor to the third reference voltage under the action of the pulse signal; The sixth reset unit is connected to the delay module, the second input terminal and the first output terminal of the voltage buffer respectively, and is used to reset the voltage of the first output terminal of the voltage buffer to the third reference voltage under the action of the delayed pulse signal; When the voltage at the first output terminal of the voltage buffer is reset to the third reference voltage, the voltage at the second terminal of the fourth capacitor becomes a third voltage, and the third voltage is cached as a new second voltage signal.

16. A pulse sequence image sensor, characterized in that: include: A pixel circuit of a pulse sequence image sensor as claimed in any one of claims 1 to 15 corresponding to each pixel; A bias current module, used for providing a constant current to the pixel circuit; The readout circuit is used to control the pixel circuit of the pulse sequence image sensor corresponding to each pixel to output a second voltage signal.

17. An electronic device, characterized in that: The electronic device comprises: a pixel circuit of a pulse sequence image sensor according to any one of claims 1 to 15, and / or a pulse sequence image sensor according to claim 16.

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