A semiconductor device cyclic test apparatus and method

Abstract

The application discloses a kind of semiconductor device cycle test device and method.The device includes: power module, freewheeling inductance, current loop control module and measured module.Power module is used to provide the electric energy required for testing;Freewheeling inductance is used to limit current variation;Current loop control module includes: first half-bridge branch, second half-bridge branch and third half-bridge branch connected in parallel with power module;Freewheeling inductance is connected between the third end of first half-bridge branch and the third end of second half-bridge branch;First half-bridge branch and second half-bridge branch cooperate to charge freewheeling inductance;First half-bridge branch and third half-bridge branch cooperate to be used for the cycle test of measured semiconductor device;Measured module is connected between the third end of second half-bridge branch and the third end of third half-bridge branch;Measured module is used to carry out cycle test to semiconductor device.The embodiment of the application can realize the constant-current output of test device test current, and is favorable to improve the accuracy and safety of testing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device cycle testing apparatus and method. Background Technology

[0002] Semiconductor devices are core components of new energy equipment such as photovoltaic inverters and converters, and their reliability directly affects the quality of these devices. Power cycle testing is one of the main methods for evaluating the lifespan of semiconductor devices (such as IGBTs). In existing technologies, testing semiconductor devices requires switching the power supply output mode.

[0003] However, voltage surges occur during power mode switching, which can affect the accuracy of semiconductor device testing, resulting in lower test accuracy. Voltage surges can also affect test safety. Summary of the Invention

[0004] This invention provides a semiconductor device cyclic testing apparatus and method to improve the accuracy and safety of testing.

[0005] According to one aspect of the present invention, a semiconductor device cycle testing apparatus is provided, the apparatus comprising:

[0006] Power module, the power module being used to provide the electrical energy required for testing;

[0007] A freewheeling inductor, wherein the freewheeling inductor is used to limit current variations;

[0008] A current loop control module includes: a first half-bridge branch, a second half-bridge branch, and a third half-bridge branch; a first terminal of the first half-bridge branch, a first terminal of the second half-bridge branch, and a first terminal of the third half-bridge branch are respectively connected to the positive terminal of the power supply module; a second terminal of the first half-bridge branch, a second terminal of the second half-bridge branch, and a second terminal of the third half-bridge branch are respectively connected to the negative terminal of the power supply module; a freewheeling inductor is connected between the third terminal of the first half-bridge branch and the third terminal of the second half-bridge branch; the first half-bridge branch and the second half-bridge branch cooperate to charge the freewheeling inductor; the first half-bridge branch and the third half-bridge branch cooperate to perform cyclic testing of the semiconductor device under test;

[0009] The module under test is connected between the third end of the second half-bridge branch and the third end of the third half-bridge branch; the module under test is used to perform cyclic testing on the semiconductor device.

[0010] Optionally, the first half-bridge branch includes: a first switching unit and a second switching unit;

[0011] The first end of the first switching unit serves as the first end of the first half-bridge branch; the second end of the first switching unit serves as the third end of the first half-bridge branch; the first end of the second switching unit is connected to the second end of the first switching unit; the second end of the second switching unit serves as the second end of the first half-bridge branch.

[0012] The second half-bridge branch includes: a third switching unit and a fourth switching unit;

[0013] The first end of the third switch unit serves as the first end of the second half-bridge branch; the second end of the third switch unit serves as the third end of the second half-bridge branch; the first end of the fourth switch unit is connected to the second end of the third switch unit; the second end of the fourth switch unit serves as the second end of the second half-bridge branch.

[0014] The third half-bridge branch includes: a fifth switch unit and a sixth switch unit;

[0015] The first end of the fifth switch unit serves as the first end of the third half-bridge branch; the second end of the fifth switch unit serves as the third end of the third half-bridge branch; the first end of the sixth switch unit is connected to the second end of the fifth switch unit; the second end of the sixth switch unit serves as the second end of the third half-bridge branch.

[0016] Optionally, the current loop control module further includes a control unit, which includes: a multiplier, a subtractor, a sample-and-hold circuit, a compensator, a pulse width modulator, and an arithmetic subunit;

[0017] The first terminal of the sample-and-hold circuit is connected to the second terminal of the freewheeling inductor; the second terminal of the sample-and-hold circuit is connected to the first input terminal of the subtractor; the output terminal of the subtractor is connected to the first terminal of the compensator; the second terminal of the compensator is connected to the first terminal of the pulse width modulator; the second terminal of the pulse width modulator is connected to the arithmetic subunit; and the second input terminal of the subtractor is connected to the multiplier.

[0018] Optionally, the module under test includes: a small current source, a clamping circuit, a conduction signal source, and the semiconductor device under test;

[0019] The first terminal of the semiconductor device under test (DUT) is connected to the third terminal of the second half-bridge branch; the second terminal of the DUT is connected to the third terminal of the third half-bridge branch; the first terminal of the small current source is connected to the first terminal of the DUT; the second terminal of the small current source is connected to the second terminal of the DUT; the first terminal of the clamping circuit is connected to the first terminal of the DUT; the second terminal of the clamping circuit is connected to the second terminal of the DUT; the first terminal of the conduction signal source is connected to the third terminal of the DUT; and the second terminal of the conduction signal source is connected to the second terminal of the DUT.

[0020] Optionally, the low current source includes: a first voltage source, a current limiting unit, and a first diode;

[0021] The positive terminal of the first voltage source is connected to the first terminal of the current limiting unit; the second terminal of the current limiting unit is connected to the anode terminal of the first diode; the cathode terminal of the first diode serves as the first terminal of the small current source; and the second terminal of the first voltage source serves as the second terminal of the small current source.

[0022] Optionally, the current limiting unit includes a resistor.

[0023] Optionally, the module under test further includes: a current direction limiting unit;

[0024] The first end of the current direction limiting unit is connected to the second end of the semiconductor device under test; the second end of the current direction limiting unit is connected to the third end of the third half-bridge branch.

[0025] Optionally, the current direction limiting unit includes a second diode.

[0026] Optionally, the power module includes: a second voltage source and a supporting capacitor;

[0027] The positive terminal of the second voltage source serves as the positive terminal of the power supply module; the negative terminal of the second voltage source serves as the negative terminal of the power supply module; and the supporting capacitor is connected in parallel with the second voltage source.

[0028] According to another aspect of the present invention, a method for cyclic testing of a semiconductor device is also provided, the method comprising:

[0029] Control the first half-bridge branch and the second half-bridge branch to charge the freewheeling inductor;

[0030] After the freewheeling inductor completes charging, the first junction temperature and first saturation voltage drop of the semiconductor device under test are obtained.

[0031] The first half-bridge branch and the third half-bridge branch are controlled to provide test current to the semiconductor device under test, and the semiconductor device under test is heated and the heating time is recorded.

[0032] After the semiconductor device under test is heated, the second saturation voltage drop and the second junction temperature of the semiconductor device under test are obtained.

[0033] Control the first half-bridge branch and the second half-bridge branch to discharge the freewheeling inductor;

[0034] While the freewheeling inductor is discharging, the semiconductor device under test is cooled, and after cooling is completed, a finite cycle test is performed on the semiconductor device under test.

[0035] The lifetime of the semiconductor device under test is evaluated based on the first junction temperature, the second junction temperature, the heating time, and the number of cycles.

[0036] This invention suppresses current surges during the switching between the second and third half-bridge branches by using a freewheeling inductor. The first and second half-bridge branches charge the freewheeling inductor, and after charging is complete, the second half-bridge branch is disconnected and the third half-bridge branch is connected. The output current of the power module is then output to the module under test (DUT) through the first and third half-bridge branches, thereby enabling the testing of the semiconductor device under test. This invention achieves constant current output and rapid disconnection of the test current by using the first and second half-bridge branches to charge and disconnect the freewheeling inductor, and by suppressing current surges during the switching between the second and third half-bridge branches. This helps avoid the influence of freewheeling on the test, improving the accuracy and safety of the test.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a semiconductor device cycle testing device provided in an embodiment of the present invention;

[0040] Figure 2 This is another semiconductor device cycle testing device provided in the embodiments of the present invention;

[0041] Figure 3 This is a waveform diagram of a semiconductor device cyclic test waveform provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a control unit provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of an operational subunit provided in an embodiment of the present invention;

[0044] Figure 6 This is yet another semiconductor device cycle testing device provided in the embodiments of the present invention;

[0045] Figure 7 This is yet another semiconductor device cycle testing device provided in the embodiments of the present invention;

[0046] Figure 8 This is a waveform diagram of another semiconductor device cyclic test waveform provided in an embodiment of the present invention;

[0047] Figure 9 This is a flowchart of a semiconductor device cyclic testing method provided in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] This invention provides a semiconductor device cyclic testing apparatus. This apparatus can be used to perform cyclic testing on semiconductor devices. Figure 1 This is a semiconductor device cycle testing apparatus provided in an embodiment of the present invention. (Refer to...) Figure 1 The device includes: a power module 110, a freewheeling inductor 120, a current loop control module 130, and a module under test 140.

[0051] Power module 110 provides the electrical energy required for testing; freewheeling inductor 120 limits current variations; current control module 130 includes: a first half-bridge branch 131, a second half-bridge branch 132, and a third half-bridge branch 133; the first terminals of the first half-bridge branch 131, the second half-bridge branch 132, and the third half-bridge branch 133 are respectively connected to the positive terminal of power module 110; the second terminals of the first half-bridge branch 131, the second half-bridge branch 132, and the third half-bridge branch 133 are respectively connected to the positive terminal of power module 110. The negative terminal of block 110 is connected; the freewheeling inductor 120 is connected between the third terminal of the first half-bridge branch 131 and the third terminal of the second half-bridge branch 132; the first half-bridge branch 131 and the second half-bridge branch 132 cooperate to charge the freewheeling inductor 120; the first half-bridge branch 131 and the third half-bridge branch 133 cooperate to perform cyclic testing on the semiconductor device under test; the module under test 140 is connected between the third terminal of the second half-bridge branch 132 and the third terminal of the third half-bridge branch 133; the module under test 140 is used to perform cyclic testing on the semiconductor device.

[0052] Specifically, the current loop control module 130 achieves constant current control of the freewheeling inductor 120 through the first half-bridge branch 131, the second half-bridge branch 132, and the third half-bridge branch 133. Before testing the semiconductor device under test, the first half-bridge branch 131 and the second half-bridge branch 132 cooperate to pre-charge the freewheeling inductor 120. At this time, the current output by the power supply module 110 charges the freewheeling inductor 120 through the first half-bridge branch 131 and the second half-bridge branch 132, and the output current of the power supply module 110 is not output to the module under test 140. When the current flowing through the freewheeling inductor 120 stabilizes, the freewheeling inductor 120 is fully charged. At this time, the second half-bridge branch 132 is deactivated, and the third half-bridge branch 133 is activated. It should be noted that the third half-bridge branch 133 is activated simultaneously with the deactivation of the second half-bridge branch 132. At this time, due to the limitation of current change by the freewheeling inductor 120, the current magnitude in the test device does not change when switching from the second half-bridge branch 132 to the third half-bridge branch 133, and the current surge during switching is suppressed by the freewheeling inductor 120. The first half-bridge branch 131 and the third half-bridge branch 133 cooperate to conduct. At this time, the output current of the power module 110 is output to the module under test 140 through the first half-bridge branch 131 and the freewheeling inductor 120. At this time, the module under test 140 tests the semiconductor device under test. It should be noted that when the module under test 140 tests the semiconductor device under test, the power module 110, the first half-bridge branch 131, the freewheeling inductor 120, the module under test 140, and the third half-bridge branch 133 form a loop.

[0053] After a preset testing period, the testing device disconnects the third half-bridge branch 133 and reconnects the second half-bridge branch 132. At this time, no output current from the power module 110 flows through the module under test 140. Similarly, when the testing device switches from the third half-bridge branch 133 to the second half-bridge branch 132, the freewheeling inductor 120 also suppresses the current surge during the switching, and the current in the testing device remains constant.

[0054] This embodiment of the invention uses a freewheeling inductor 120 to suppress current surges during the switching between the second half-bridge branch 132 and the third half-bridge branch. The first half-bridge branch 131 and the second half-bridge branch 132 charge the freewheeling inductor 120, and after charging is complete, the second half-bridge branch 132 is disconnected and the third half-bridge branch 133 is connected. The output current of the power module 110 is then output to the module under test 140 through the first half-bridge branch 131 and the third half-bridge branch 133, thereby enabling the testing of the semiconductor device under test. This embodiment of the invention uses the first half-bridge branch 131 and the second half-bridge branch to charge and disconnect the freewheeling inductor 120, and uses the freewheeling inductor 120 to suppress current surges during the switching between the second half-bridge branch 132 and the third half-bridge branch 133. This achieves constant current output and rapid disconnection of the test current in the testing device, which helps to avoid the influence of freewheeling on the test and improves the accuracy and safety of the test.

[0055] Figure 2 This is another semiconductor device cycle testing apparatus provided in the embodiments of the present invention. Optionally, based on the above embodiments, refer to... Figure 2 The first half-bridge branch 131 includes: a first switch unit S1 and a second switch unit S2.

[0056] The first end of the first switching unit S1 serves as the first end of the first half-bridge branch 131; the second end of the first switching unit S1 serves as the third end of the first half-bridge branch 131; the first end of the second switching unit S2 is connected to the second end of the first switching unit S1; the second end of the second switching unit S2 serves as the second end of the first half-bridge branch 131.

[0057] The second half-bridge branch 132 includes: a third switch unit S3 and a fourth switch unit S4.

[0058] The first end of the third switch unit S3 serves as the first end of the second half-bridge branch 132; the second end of the third switch unit S3 serves as the third end of the second half-bridge branch 132; the first end of the fourth switch unit S4 is connected to the second end of the third switch unit S3; the second end of the fourth switch unit S4 serves as the second end of the second half-bridge branch 132.

[0059] The third half-bridge branch 133 includes: the fifth switch unit S5 and the sixth switch unit S6.

[0060] The first end of the fifth switch unit S5 serves as the first end of the third half-bridge branch 133; the second end of the fifth switch unit S5 serves as the third end of the third half-bridge branch 133; the first end of the sixth switch unit S6 is connected to the second end of the fifth switch unit S5; the second end of the sixth switch unit S6 serves as the second end of the third half-bridge branch 133.

[0061] Figure 3This is a waveform diagram of a semiconductor device cyclic test provided in an embodiment of the present invention. Specifically, refer to... Figure 3 During the time interval t0-t1, the first half-bridge branch 131 and the second half-bridge branch 132 pre-charge the freewheeling inductor 120. The first switching unit S1 and the fourth switching unit S4 are simultaneously turned on or off; the second switching unit S2 and the third switching unit S3 are simultaneously turned on or off. At time t1, the pre-charging of the freewheeling inductor 120 is complete, the current of the freewheeling inductor 120 stabilizes, and the second half-bridge branch 132 is deactivated, while the third half-bridge branch 133 is activated. During the switching process, the freewheeling inductor 120 suppresses the current surge during switching, thereby keeping the test current in the test device in a constant current state. For example, depending on the test requirements, the junction temperature and saturation voltage drop of the semiconductor device under test can be collected before time t1.

[0062] During the time period t1-t2, the first half-bridge branch 131 and the third half-bridge branch 133 jointly provide test current to the module under test 140. The first switching unit S1 and the sixth switching unit S6 are synchronously turned on or off; the second switching unit S2 and the fifth switching unit S5 are synchronously turned on or off. It should be noted that after the third half-bridge branch 133 is connected, the load size in the test device changes, and the charging and discharging slope of the freewheeling inductor 120 changes, but it has no effect on the average current. During this time period, the module under test 140 tests the semiconductor device under test. At time t2, the module under test 140 completes the test of the semiconductor device under test. At this time, the third half-bridge branch 133 is disconnected, the second half-bridge branch 132 is reconnected, and the module under test 140 begins to cool. Similarly, during the switching process, the freewheeling inductor 120 suppresses the current surge during switching, thereby keeping the test current in the test device in a constant current state. For example, depending on the testing requirements, the junction temperature and saturation voltage drop of the semiconductor device under test can be collected at time t2.

[0063] During the time period t2-t3, the first half-bridge branch 131 and the second half-bridge branch 132 release the electrical energy stored in the freewheeling inductor 120. The first switching unit S1 and the fourth switching unit S4 are simultaneously turned on or off; the second switching unit S2 and the third switching unit S3 are simultaneously turned on or off. At time t3, the release of the electrical energy stored in the freewheeling inductor 120 is complete.

[0064] During the time period t3-t4, both the first bridge branch 131 and the second half-bridge branch 132 are turned off. During this period, the first switching unit S1, the second switching unit S2, the third switching unit S3, and the fourth switching unit S4 are also turned off. There is no current flowing through the freewheeling inductor 120, and the power module 110 is in an unloaded state. This configuration in this embodiment helps reduce test energy consumption and improve energy-saving performance.

[0065] Figure 4 This is a schematic diagram of a control unit provided in an embodiment of the present invention. Optionally, based on the above embodiments, the current loop control module 130 may further include a control unit (not shown), see reference... Figure 4 The control unit includes: a multiplier 210, a subtractor 220, a sample-and-hold circuit 230, a compensator 240, a pulse width modulator 250, and an arithmetic subunit 260.

[0066] The first terminal of the sample-and-hold circuit 230 is connected to the second terminal of the freewheeling inductor 120; the second terminal of the sample-and-hold circuit 230 is connected to the first input terminal of the subtractor 220; the output terminal of the subtractor 220 is connected to the first terminal of the compensator 240; the second terminal of the compensator 240 is connected to the first terminal of the pulse width modulator 250; the second terminal of the pulse width modulator 250 is connected to the arithmetic subunit 260; and the second input terminal of the subtractor 220 is connected to the multiplier 210.

[0067] Specifically, the first input terminal of the multiplier 210 is connected to the reference current I. ref The second input terminal of multiplier 210 is connected to the reference current enable signal I. ref_EN The first input terminal of the arithmetic subunit 260 is connected to the second terminal of the pulse width modulator 250, and the second input terminal of the arithmetic subunit 260 is connected to the reference current enable signal I. ref_EN The third input terminal of the arithmetic subunit 260 is connected to the junction temperature enable signal H. EN It should be noted that the reference current I... ref Reference current enable signal I ref_EN and junction temperature enable signal H EN The methods for obtaining the current are diverse, and this embodiment does not limit them. Specifically, the current of the freewheeling inductor 120 is the same as the reference current I. ref The difference is calculated, and the modulated wave is output from the pulse width modulator 250 after passing through the compensator 240. The modulated wave is then distributed by the operation subunit 260 to complete the control waveform of each switching unit.

[0068] Figure 5 This is a schematic diagram of an operational subunit provided in an embodiment of the present invention. (Refer to...) Figure 5 For example, one mode of operation subunit 260 is a reference current enable signal I. ref_EN The modulated wave is ANDed to obtain the control signal for the first switching unit S1. The control signal for the first switching unit S1 is then inverted by a NOT gate to obtain the control signal for the second switching unit S2; the reference current enable signal I... ref_EN With junction temperature enable signal H ENThe NOT result is ANDed with the control signals of the first switching unit S1 and the second switching unit S2, respectively, to obtain the control signals of the third switching unit S3 and the fourth switching unit S4; the junction temperature enable signal H EN After the operation, the control signals of the first switch unit S1 and the second switch unit S2 are respectively combined to obtain the control signals of the fifth switch unit S5 and the sixth switch unit S6.

[0069] Figure 6 This is yet another semiconductor device cycle testing apparatus provided in the embodiments of the present invention. Optionally, based on the above embodiments, refer to... Figure 6 The module under test 140 includes: a small current source 141, a clamping circuit 142, a conduction signal source VH, and a semiconductor device under test 143.

[0070] The first terminal of the semiconductor device under test 143 is connected to the third terminal of the second half-bridge branch 132; the second terminal of the semiconductor device under test 143 is connected to the third terminal of the third half-bridge branch 133; the first terminal of the small current source 141 is connected to the first terminal of the semiconductor device under test 143; the second terminal of the small current source 141 is connected to the second terminal of the semiconductor device under test 143; the first terminal of the clamping circuit 142 is connected to the first terminal of the semiconductor device under test 143; the second terminal of the clamping circuit 142 is connected to the second terminal of the semiconductor device under test 143; the first terminal of the conduction signal source VH is connected to the third terminal of the semiconductor device under test 143; the second terminal of the conduction signal source VH is connected to the second terminal of the semiconductor device under test 143.

[0071] Specifically, the small current source 141 provides a small current to the semiconductor device under test (DUT) 143 to saturate it. The conduction signal source VH provides a conduction signal to the DUT 143 to keep it in a conducting state. During testing, the performance of the DUT 143 gradually degrades, posing a risk of damage. When the DUT 143 fails, it becomes open-circuited or exhibits high resistance, resulting in a high voltage across its terminals under the influence of the test current. The clamping circuit 142 detects the voltage across the DUT 143 and cuts off the test current when it exceeds a safe voltage, thus preventing damage to the semiconductor device cyclic testing device.

[0072] Based on the above embodiments, optionally, refer to... Figure 6 The low current source 141 includes: a first voltage source Vc, a current limiting unit 1411, and a first diode D1.

[0073] The positive terminal of the first voltage source Vc is connected to the first terminal of the current limiting unit 1411; the second terminal of the current limiting unit 1411 is connected to the anode terminal of the first diode D1; the cathode terminal of the first diode D1 serves as the first terminal of the small current source 141; and the second terminal of the first voltage source Vc serves as the second terminal of the small current source 141.

[0074] Optionally, based on the above embodiments, the current limiting unit 1411 includes a resistor.

[0075] Based on the above embodiments, optionally, refer to... Figure 6 The power module 110 includes a second voltage source Vs and a supporting capacitor C.

[0076] The positive terminal of the second voltage source Vs serves as the positive terminal of the power supply module 110; the negative terminal of the second voltage source Vs serves as the negative terminal of the power supply module 110; the supporting capacitor C is connected in parallel with the second voltage source Vs.

[0077] Figure 7 This is yet another semiconductor device cycle testing apparatus provided in the embodiments of the present invention. Optionally, based on the above embodiments, refer to... Figure 7 The module under test 140 also includes a current direction limiting unit 144.

[0078] The first end of the current direction limiting unit 144 is connected to the second end of the semiconductor device under test 143; the second end of the current direction limiting unit 144 is connected to the third end of the third half-bridge branch 133.

[0079] Figure 8 This is a waveform diagram of another semiconductor device cyclic test waveform provided in an embodiment of the present invention. Specifically, the current direction limiting unit 144 is used to limit the current direction. Under the action of the current direction limiting unit 144, the semiconductor device cyclic test device can also... Figure 8 The semiconductor device is tested under the waveform shown.

[0080] Optionally, based on the above embodiments, the current direction limiting unit 144 includes a second diode.

[0081] Figure 9 This is a flowchart of a semiconductor device cyclic testing method provided in an embodiment of the present invention. The semiconductor device cyclic testing apparatus provided in the above embodiment can be used to test the semiconductor device under test using this testing method. (Refer to...) Figure 9 The method includes:

[0082] S110, controls the first half-bridge branch and the second half-bridge branch to charge the freewheeling inductor;

[0083] S120. After the freewheeling inductor is fully charged, obtain the first junction temperature and the first saturation voltage drop of the semiconductor device under test.

[0084] S130: Control the first half-bridge branch and the third half-bridge branch to provide test current to the semiconductor device under test, heat the semiconductor device under test and record the heating time;

[0085] S140. After the semiconductor device under test is heated, obtain the second saturation voltage drop and the second junction temperature of the semiconductor device under test.

[0086] S150 controls the first half-bridge branch and the second half-bridge branch to discharge the freewheeling inductor;

[0087] S160. While the freewheeling inductor is discharging, the semiconductor device under test enters the cooling process, and the semiconductor device under test is tested again after the cooling is completed.

[0088] S170. The lifetime of the semiconductor device under test is evaluated based on the first junction temperature, the second junction temperature, the heating time, and the number of cycles.

[0089] Specifically, the specific steps of the semiconductor device cycle testing method have been described in detail in the above embodiments, and will not be repeated here.

[0090] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device cycle testing apparatus, characterized in that, include: Power module, the power module being used to provide the electrical energy required for testing; A freewheeling inductor is used to limit current changes and suppress current surges during the switching between the second and third half-bridge branches. A current loop control module includes: a first half-bridge branch, a second half-bridge branch, and a third half-bridge branch; a first terminal of each of the first, second, and third half-bridge branches is connected to the positive terminal of a power supply module; a second terminal of each of the first, second, and third half-bridge branches is connected to the negative terminal of the power supply module; a freewheeling inductor is connected between the third terminal of the first and second half-bridge branches; the first and second half-bridge branches cooperate to charge the freewheeling inductor; and after the freewheeling inductor is fully charged, the second half-bridge branch is disconnected and connected to the third half-bridge branch; the first and third half-bridge branches cooperate to perform cyclic testing of the semiconductor device under test. The module under test is connected between the third end of the second half-bridge branch and the third end of the third half-bridge branch; the module under test is used to perform cyclic testing on the semiconductor device.

2. The semiconductor device cycle testing apparatus according to claim 1, characterized in that, The first half-bridge branch includes: a first switching unit and a second switching unit; The first end of the first switching unit serves as the first end of the first half-bridge branch; the second end of the first switching unit serves as the third end of the first half-bridge branch; the first end of the second switching unit is connected to the second end of the first switching unit; the second end of the second switching unit serves as the second end of the first half-bridge branch. The second half-bridge branch includes: a third switching unit and a fourth switching unit; The first end of the third switch unit serves as the first end of the second half-bridge branch; the second end of the third switch unit serves as the third end of the second half-bridge branch; the first end of the fourth switch unit is connected to the second end of the third switch unit; the second end of the fourth switch unit serves as the second end of the second half-bridge branch. The third half-bridge branch includes: a fifth switch unit and a sixth switch unit; The first end of the fifth switch unit serves as the first end of the third half-bridge branch; the second end of the fifth switch unit serves as the third end of the third half-bridge branch; the first end of the sixth switch unit is connected to the second end of the fifth switch unit; the second end of the sixth switch unit serves as the second end of the third half-bridge branch.

3. The semiconductor device cycle testing apparatus according to claim 1, characterized in that, The current loop control module also includes a control unit, which includes: a multiplier, a subtractor, a sample-and-hold circuit, a compensator, a pulse width modulator, and an arithmetic subunit; The first terminal of the sample-and-hold circuit is connected to the second terminal of the freewheeling inductor; the second terminal of the sample-and-hold circuit is connected to the first input terminal of the subtractor; the output terminal of the subtractor is connected to the first terminal of the compensator; the second terminal of the compensator is connected to the first terminal of the pulse width modulator; the second terminal of the pulse width modulator is connected to the arithmetic subunit; and the second input terminal of the subtractor is connected to the multiplier.

4. The semiconductor device cycle testing apparatus according to claim 1, characterized in that, The module under test includes: a small current source, a clamping circuit, a conduction signal source, and the semiconductor device under test; The first terminal of the semiconductor device under test (DUT) is connected to the third terminal of the second half-bridge branch; the second terminal of the DUT is connected to the third terminal of the third half-bridge branch; the first terminal of the small current source is connected to the first terminal of the DUT; the second terminal of the small current source is connected to the second terminal of the DUT; the first terminal of the clamping circuit is connected to the first terminal of the DUT; the second terminal of the clamping circuit is connected to the second terminal of the DUT; the first terminal of the conduction signal source is connected to the third terminal of the DUT; and the second terminal of the conduction signal source is connected to the second terminal of the DUT.

5. The semiconductor device cycle testing apparatus according to claim 4, characterized in that, The low current source includes: a first voltage source, a current limiting unit, and a first diode; The positive terminal of the first voltage source is connected to the first terminal of the current limiting unit; the second terminal of the current limiting unit is connected to the anode terminal of the first diode; the cathode terminal of the first diode serves as the first terminal of the small current source; and the second terminal of the first voltage source serves as the second terminal of the small current source.

6. The semiconductor device cycle testing apparatus according to claim 4, characterized in that, The module under test further includes: a current direction limiting unit; The first end of the current direction limiting unit is connected to the second end of the semiconductor device under test; the second end of the current direction limiting unit is connected to the third end of the third half-bridge branch.

7. The semiconductor device cycle testing apparatus according to claim 6, characterized in that, The current direction limiting unit includes a second diode.

8. The semiconductor device cycle testing apparatus according to claim 1, characterized in that, The power module includes: a second voltage source and a supporting capacitor; The positive terminal of the second voltage source serves as the positive terminal of the power supply module; the negative terminal of the second voltage source serves as the negative terminal of the power supply module; and the supporting capacitor is connected in parallel with the second voltage source.

9. A method for cyclic testing of semiconductor devices, applicable to the cyclic testing apparatus for semiconductor devices as described in any one of claims 1-8, characterized in that, include: Control the first half-bridge branch and the second half-bridge branch to charge the freewheeling inductor; After the freewheeling inductor completes charging, the first junction temperature and first saturation voltage drop of the semiconductor device under test are obtained. The first half-bridge branch and the third half-bridge branch are controlled to provide test current to the semiconductor device under test, and the semiconductor device under test is heated and the heating time is recorded. After the semiconductor device under test is heated, the second saturation voltage drop and the second junction temperature of the semiconductor device under test are obtained. Control the first half-bridge branch and the second half-bridge branch to discharge the freewheeling inductor; While the freewheeling inductor is discharging, the semiconductor device under test is cooled, and after cooling is completed, a finite cycle test is performed on the semiconductor device under test. The lifetime of the semiconductor device under test is evaluated based on the first junction temperature, the second junction temperature, the heating time, and the number of cycles.

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