A method for generating unique identifiers based on RAM tags
By using a unique identifier generation method based on RAM tags, the problem of identifier management difficulties in RDMA systems is solved, achieving efficient and secure resource management and reducing storage requirements and latency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA TELECOM CLOUD TECH CO LTD
- Filing Date
- 2023-12-14
- Publication Date
- 2026-05-26
AI Technical Summary
In existing RDMA systems, hardware resource management is difficult, especially when the identification code is reused, the search latency is high and the storage requirements are large, and there is a lack of security protection measures.
A unique identifier generation method based on RAM tags is adopted. The command processing module identifies and processes commands, and the BRAM module creates, destroys and initializes unique identifiers. Combining serial and parallel search, accumulator and scrambling processing are used to achieve parallel output of multi-bit tags and avoid the reuse of identifiers.
It shortens the latency of identification code generation, improves resource management efficiency, reduces storage requirements, and enhances the security of identification codes.
Smart Images
Figure CN117850874B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of DPU processing in data centers, and particularly to a method for generating a unique identifier based on RAM tags. Background Technology
[0002] In data processing systems, RDMA systems have always been the preferred choice for data center and high-performance computing center layouts due to their high system performance and low latency. When designing an RDMA system, a globally unique identifier is required to manage various processing resources, such as QP, CQ, and MR resources. The RDMA protocol specifies the use of 24 bits as the identifier for this resource. However, in reality, the hardware cannot manage so many resources; only a portion of the identifiers are used. The CPU manages these resources by creating and destroying them. Destroyed identifiers can be reused, but the same identifier should be used at intervals to avoid system management chaos caused by the hardware using the same identifier before higher-level resources are completely destroyed. Therefore, to achieve maximum interval spacing in system usage, the identifier needs to be processed using 24 bits. Currently, bit-marking is commonly used for identifier reuse after destruction. However, existing bit-marking methods require 2 megabytes of storage when all 24 bits are used. For FPGAs, 2 megabytes of internal BRAM is a large amount. Furthermore, this method has high search latency during reuse and lacks corresponding identifier security protection measures, which is detrimental to hardware management. Summary of the Invention
[0003] The purpose of this invention is to provide a method for generating a unique identifier based on RAM tags, so as to solve the problems mentioned in the background art.
[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for generating a unique identifier based on RAM tags, the method comprising the following steps;
[0005] The first step is to receive commands from higher-level software through the command processing module;
[0006] The second step is to use the command processing module to identify the command type and process it.
[0007] The third step involves receiving commands from the command processing module after they have been parsed and identified by the initialization module and the control logic module, and then performing processing operations, including creating a unique identifier, destroying the unique identifier, and initializing the BRAM.
[0008] The fourth step is to return the processing result.
[0009] Preferably, in the fourth step, the processing result is returned to mark the bit corresponding to the BRAM and a success status is returned. When the unique identifier creation operation is successful, the mark bit is cleared and a success status is returned in the fourth step. When the unique identifier destruction operation is performed, the mark is found in the BRAM through the control logic module.
[0010] Preferably, the step of identifying the command type operation through the command processing module specifically includes the following steps;
[0011] A1 defines the supported command types, which include creation commands, destruction commands, and initialization commands;
[0012] A2. Design a command type identification strategy, which includes identification through fixed command format, keyword matching, and regular expressions;
[0013] A3, Parse the received command, wherein parsing the command includes passing the command received via serial port and network communication to the command processing module for parsing;
[0014] A4. Command type identification is performed according to the identification strategy. The identification operation includes string processing and matching algorithm.
[0015] A5, execute the corresponding processing logic, which includes sending the command to the initialization module or the control logic module;
[0016] A6, Design error handling and fault tolerance mechanisms, the errors including failure to recognize command type and incorrect command format.
[0017] Preferably, the third step of creating a unique identifier specifically includes the following steps;
[0018] B1, creates a new unique identifier through the control logic module;
[0019] B2, using the newly created identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM;
[0020] B3, based on the verification result, performs the corresponding result output operation.
[0021] Preferably, the BRAM lookup operation in B2 includes dividing the unique identifier into low L bits and high H bits to look up the BRAM, where the low L / H bits are used as the address of the BRAM to read the BRAM content, and the high H / L bits are used as the index of the output data.
[0022] Preferably, the result output operation in B3 includes scrambling the current unique identifier and then using the unique identifier. When the corresponding bit in the BRAM content is not used, the result output operation in A3 includes searching the next bit in the output result of the BRAM until a usable bit is found. When the corresponding bit in the BRAM content is already used, the result output operation in A3 includes returning a creation failure. When there is no usable corresponding bit in the BRAM content.
[0023] Preferably, the operation of destroying the unique identification code in the third step specifically includes the following steps;
[0024] C1, the control logic module first descrambles the current unique identification code;
[0025] C2, using the identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM;
[0026] C3 outputs the corresponding results based on the search results.
[0027] Preferably, the result output operation in C3 includes clearing the corresponding bit of the unique identifier and returning a success status. When the output value of the BRAM content search is 1, the result output operation in B3 returns a failure status, and when the output value of the BRAM content search is 0.
[0028] Preferably, the initialization module operation in the third step includes receiving an initialization module command issued by the command processing module through the initialization module, and running internal logic to erase the contents of the BRAM. The operation of erasing the contents of the BRAM includes clearing all flag bits in the BRAM.
[0029] Preferably, the operations of creating a unique identifier, destroying a unique identifier, and initializing BRAM in the third step are all performed based on the BRAM module. The BRAM module is a block storage unit of the FPGA and includes the tag bits of all unique identifiers.
[0030] The technical effects and advantages of this invention are as follows:
[0031] This invention utilizes the characteristics of BRAM to simultaneously achieve serial and parallel searching, processing multiple tags at once and shortening the delay in generating unique identifiers. During processing, a temporary 24-bit counter is divided into two parts: one part indexes the BRAM to obtain multiple tag outputs, and the other part indexes these tag outputs in parallel, enabling one-time multi-bit tag output usable position checking. Through accumulator and scrambling processing, the tags are randomly generated, avoiding the reuse of recently destroyed identifiers. Attached Figure Description
[0032] Figure 1This is a schematic diagram of the overall method flow of the present invention.
[0033] Figure 2 This is a schematic diagram of the unique identification code generation structure of this invention.
[0034] Figure 3 This is a schematic diagram of the process for generating the unique identification code of this invention.
[0035] Figure 4 This is a schematic diagram of the FPGA application structure of the present invention. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] This invention provides, for example Figure 1-4 The present invention provides a method for generating a unique identifier based on RAM tags, the method comprising the following steps;
[0038] The first step is to receive commands from higher-level software through the command processing module;
[0039] The second step is to use the command processing module to identify the command type and process it.
[0040] The third step involves receiving commands from the command processing module after parsing and recognizing them through the initialization module and the control logic module, and then performing processing operations, including creating a unique identifier, destroying the unique identifier, and initializing the BRAM.
[0041] The fourth step is to return the processing result.
[0042] It should be noted that this invention offloads data processing below the RDMA transport layer from the FPGA. FPGA refers to Field Programmable Gate Array, which is an integrated digital circuit that can modify and configure the internal connection structure and logic units of the device through programmable means to complete a predetermined function. RDMA refers to Remote Direct Memory Access, which is a new technology that allows direct access between local computer memory and remote memory without the need for CPU involvement in data transfer.
[0043] Furthermore, unique identifiers are used to identify different hosts, network interface cards, and RDMA resources, including globally unique identifiers (GUIDs), local identifiers (LIDs) that identify physical ports in the InfiniBand network, QP numbers that uniquely identify queue pairs in RDMA transmissions, MR numbers that uniquely identify memory regions, and CQ numbers that uniquely identify completion queues.
[0044] In the fourth step, the processing result is returned to mark the corresponding bit in the BRAM and a success status is returned. When the unique identifier creation operation is successful, the mark bit is cleared in the fourth step and a success status is returned. When the unique identifier destruction operation is performed, the mark is found in the BRAM through the control logic module.
[0045] The command processing module identifies command type operations, which includes the following steps;
[0046] A1 defines the supported command types, including creation commands, destruction commands, and initialization commands;
[0047] A2. Design a command type identification strategy, which includes identification through fixed command format, keyword matching, and regular expressions;
[0048] Furthermore, fixed format refers to a specific field order and delimiters. By parsing the input command or statement through a predefined format, the command type can be identified and relevant parameters can be extracted. Keyword matching refers to identifying the command type by looking for whether the command or statement contains specific keywords or identifiers. Regular expressions are tools used to describe and match string patterns. They are expressions composed of a series of characters and special symbols, used to define a certain pattern, and can be used for text search, replacement, validation, and extraction operations.
[0049] A3, Parse the received command. Parsing the command includes passing the command received via serial port and network communication to the command processing module for parsing;
[0050] A4, command type identification is performed according to the identification strategy. The identification operation includes string processing and matching algorithm.
[0051] A5 executes the corresponding processing logic, which includes sending commands to the initialization module or the control logic module;
[0052] A6, designed with error handling and fault tolerance mechanisms, errors include failure to recognize command type and incorrect command format.
[0053] Furthermore, after the command processing module is completed, it needs to be tested and verified to ensure that it can correctly identify and process various command types and work in coordination with other system components.
[0054] The third step, creating a unique identifier, includes the following steps:
[0055] B1, creates a new unique identifier through the control logic module;
[0056] B2, using the newly created identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM;
[0057] B3, based on the verification result, performs the corresponding result output operation.
[0058] The BRAM lookup operation in B2 involves dividing the unique identifier into low L bits and high H bits to search for the BRAM. The low L / H bits are used as the address of the BRAM to read the BRAM content, and the high H / L bits are used as the index of the output data.
[0059] The result output operation in B3 includes scrambling the current unique identifier and then using the unique identifier. If the corresponding bit in the BRAM content is not used, the result output operation in A3 includes searching for the next bit in the output result of the BRAM until a usable bit is found. If the corresponding bit in the BRAM content is already used, the result output operation in A3 includes returning a creation failure. If no usable corresponding bit is found in the BRAM content.
[0060] Example 1:
[0061] An 18K-bit BRAM has an FPGA output bit width of 36 or 32 bits, an address width of 9 bits, and a data index of 6 or 5 bits. However, in practical applications, H is not an integer power of 2, so some unique identifiers may not be used. In this case, unused unique identifiers can be discarded without further processing, or the BRAM output bit width can be set to 32 bits, allowing the data bit width to be an integer power of 2. In an RDMA system, the system's unique identifier is 24 bits. A single BRAM cannot mark all identifiers, so to fully utilize the 24-bit width, a 24-bit accumulator output is used as an intermediate result. The lower 10 + 5 = 15 bits of the intermediate result are used as the index for searching the BRAM. Furthermore, to ensure the confidentiality of the unique identifier, the intermediate result is scrambled before being used as the system's unique identifier. It should be noted that when the unique identifier is a QP number, the unique identifier must be greater than 1. Therefore, when generating QPn, an additional check is required; identifiers that do not meet the requirement of being greater than 1 need to be recalculated.
[0062] Example 2:
[0063] According to the above embodiment 1, the specific operation steps after the control logic module receives the command to create a unique identification code are as follows;
[0064] D1, the control logic module first generates a 24-bit index;
[0065] D2, extract the lower 15 bits for index lookup in BRAM;
[0066] D3 divides the 15-bit index into a 10-bit index and a 5-bit index. The 10-bit index is used as the address to read the BRAM content, and the other 5-bit index is used as the index for the BRAM output content.
[0067] D4, use the lower 15 index to look up BRAM;
[0068] D5. Process the search results.
[0069] Furthermore, in the above D5, a new 24-bit index is generated for searching. When the search BRAM is marked as 1, it indicates successful generation. The current 24-bit index is scrambled and returned as the system's unique identifier. When the search BRAM is marked as 0, it indicates failure. And when all BRAMs are marked.
[0070] The third step, destroying the unique identifier, includes the following steps:
[0071] C1, the control logic module first descrambles the current unique identification code;
[0072] C2, using this identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM;
[0073] C3 outputs the corresponding results based on the search results.
[0074] The result output operation in C3 includes clearing the corresponding bit of the unique identifier and returning a success status. When the output value of searching the BRAM content is 1, the result output operation in B3 returns a failure status, and when the output value of searching the BRAM content is 0.
[0075] Furthermore, the steps for searching to destroy a unique identifier are the same as those for searching to create a unique identifier.
[0076] The third step involves the initialization module operation, which includes receiving the initialization module command issued by the command processing module through the initialization module and running the internal logic to erase the contents of the BRAM. The BRAM erasure operation includes clearing all the flag bits in the BRAM.
[0077] Furthermore, since the FPGA logic cannot erase the BRAM contents during a warm boot, the BRAM needs to be initialized during a warm boot. Otherwise, the BRAM will retain all previous markings. Therefore, the initialization module operation is often used during a system warm boot.
[0078] The third step, which involves creating, destroying, and initializing the unique identifier, is based on the BRAM module. The BRAM module is the block storage unit of the FPGA and includes the tag bits for all unique identifiers.
[0079] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for generating a unique identification code based on RAM marking, characterized by, The generation method includes the following steps; The first step is to receive commands from higher-level software through the command processing module; The second step is to use the command processing module to identify the command type and process it. The third step involves receiving commands from the command processing module after they have been parsed and identified by the initialization module and the control logic module, and then performing processing operations, including creating a unique identifier, destroying the unique identifier, and initializing the BRAM. The fourth step is to return the processing result, including: if the unique identifier is successfully created, the corresponding bit in the BRAM is marked and the creation success status is returned; When the unique identifier is destroyed, if the control logic module finds the corresponding marked bit in the BRAM, it clears the marked bit and returns a successful destruction status.
2. The method of claim 1, wherein the RAM flag-based unique identification code is generated by using a RAM flag. The command processing module identifies command type operations, which includes the following steps; A1 defines the supported command types, which include creation commands, destruction commands, and initialization commands; A2. Design a command type identification strategy, which includes identification through fixed command format, keyword matching, and regular expressions; A3, parsing the received commands, including passing commands received via serial port and network communication to the command processing module for parsing; A4. Command type identification is performed according to the identification strategy, which includes string processing and matching algorithms; A5, execute the corresponding processing logic, which includes sending commands to the initialization module or the control logic module; A6, Design error handling and fault tolerance mechanisms, where errors include failure to recognize command type and incorrect command format.
3. The method of claim 1, wherein the RAM flag-based unique identification code is generated by using a RAM flag. The third step of creating a unique identification code specifically includes the following steps; B1, creates a new unique identifier through the control logic module; B2, using the newly created identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM; B3, based on the verification result, perform the corresponding result output operation.
4. The method of claim 3, wherein the RAM flag is set to 1 when the RAM is not used. The BRAM lookup operation in B2 includes dividing the unique identifier into low L bits and high H bits to look up the BRAM. The low L bits are used as the address of the BRAM to read the BRAM content, and the high H bits are used as the index of the BRAM output content.
5. The method of claim 4, wherein the RAM flag is set to a value of 1. The result output operation in B3 includes: when the corresponding bit in the BRAM content is not used, the current unique identifier is scrambled and used as the output unique identifier; when the corresponding bit in the BRAM content is used, the search continues in the next bit of the BRAM output result until a usable corresponding bit is found; when no usable corresponding bit is found in the BRAM content, the creation failure status is returned.
6. The method of claim 4, wherein the RAM flag-based unique identification code is generated by using a RAM flag. The operation of destroying the unique identification code in the third step includes the following steps; C1, the control logic module first descrambles the current unique identification code; C2, using the identification code as the address to look up the BRAM, the BRAM lookup operation includes checking the usage of the corresponding bit in the BRAM; C3 outputs the corresponding results based on the search results.
7. The method for generating a unique identifier based on RAM tags according to claim 6, characterized in that, The result output operation in C3 includes: when the output value of the BRAM content is found to be 1, the bit corresponding to the unique identifier is cleared and the destruction success status is returned; when the output value of the BRAM content is found to be 0, the destruction failure status is returned.
8. The method for generating a unique identifier based on RAM tags according to claim 1, characterized in that, The third step of the initialization module operation includes receiving the initialization module command issued by the command processing module through the initialization module, and running the internal logic to erase the contents of the BRAM. The operation of erasing the contents of the BRAM includes clearing all the flag bits in the BRAM.
9. The method for generating a unique identifier based on RAM tags according to claim 1, characterized in that, The creation, destruction, and initialization of the unique identifier in the third step are all performed based on the BRAM module, which is the block storage unit of the FPGA and includes the tag bits of all unique identifiers.