A Multi-Project Wafer Layout Stitching Method, Device and Storage Medium Based on Adaptive Search

Abstract

The present application discloses a method for splicing multi-project wafer layouts, including: S1: obtaining chip specification parameters and constraint parameters of an envelope rectangle formed after splicing; S2: sorting a plurality of polygon chips to be spliced in descending order of area and sequentially placing them in a preset splicing area, and calculating the area of the envelope rectangle after all the polygon chips corresponding to the initial width are placed; S3: calculating the area of each envelope rectangle corresponding to each of the remaining widths; S4: obtaining a set of areas of the envelope rectangles sorted in descending order of area; S5: setting the probability that the k-th envelope rectangle corresponding to the area of the k-th envelope rectangle in the set of areas of the envelope rectangles is selected as P, and selecting one of the envelope rectangles with this probability; S6: using the simulated annealing algorithm to rotate at least one polygon chip in the selected envelope rectangle, and outputting the envelope rectangle with reduced area as the optimal splicing area.

Description

Technical Field

[0001] This application belongs to the field of electronic design automation, and particularly relates to a method for stitching MPW (Multi-Project Wafer) layouts based on adaptive search. Background Art

[0002] In the design, manufacturing, etc. of integrated circuits (ICs), if only one type of integrated circuit is tested on the same silicon wafer, the cost of such a sample is extremely high. Therefore, in order to save costs and reduce risks, the Multi-Project Wafer (MPW) technology is often used. A Multi-Project Wafer (MPW) is to place multiple integrated circuit designs using the same process on the same wafer for wafer processing. After manufacturing, each design can obtain dozens of chip samples, and this quantity is sufficient for experiments and tests in the prototype design stage. The manufacturing cost of this time is shared by all projects participating in the MPW according to the chip area, and the cost is only 5%-10% of the cost of separately manufacturing prototypes, greatly reducing the product development risk, the threshold for cultivating integrated circuit design talents, and the threshold for small and medium-sized integrated circuit design enterprises at the start.

[0003] In a Multi-Project Wafer (MPW), multiple chip layouts (modules) are stitched together. That is, for a given number of chip layouts (modules) with different shapes and sizes, according to given rules, they are reasonably arranged so that the area of the combined rectangular region is the smallest. The Multi-Project Wafer MPW is stitched into a rectangular region for one-time exposure, and this rectangular region is usually called a shot (i.e., the area size for one-time exposure by a lithography machine).

[0004] The multi-project wafer processing service means that multiple users share the same mask and the same shot area at the same time. The original shot used by a single user is divided into multiple small grids (called die, that is, the final obtained chip), and each small grid is provided with design patterns by multiple users. The entire wafer takes the shot as the basic unit, and repeats the design patterns of these multiple users. Finally, multiple users jointly bear the wafer processing cost of this time.

[0005] For the stitching of a multi-project wafer MPW, it is necessary to find the smallest rectangular region for one-time exposure, so that the utilization rate of the wafer is the highest.

[0006] Currently, the layout design for MPW can only achieve a relatively optimized design to a certain extent, and the utilization rate of the wafer needs to be further improved. In addition, the time taken to achieve this relatively optimized design is long, increasing the burden of layout design, and further extending the overall duration of each MPW layout wafer project. Summary of the Invention

[0007] This application is completed in view of the above problems. This application proposes a method for MPW splicing based on random field search to effectively improve the utilization rate of wafers and overcome the problem of low design efficiency of MPW layout splicing in the prior art.

[0008] In the first aspect of this application, a method for splicing multi-project wafer layouts based on adaptive search is proposed, including:

[0009] S1: Obtain multiple chip specification parameters and constraint parameters of the bounding rectangle formed after splicing multiple chips;

[0010] S2: Randomly select a width W from the set W of candidate widths of the set splicing area as the initial width of the set splicing area, set the initial height of the set splicing area to the maximum height H_max of the splicing area, sort multiple polygon chips to be spliced in descending order of area and sequentially place them in the set splicing area, and calculate the area of the bounding rectangle after all the polygon chips corresponding to the initial width W m are placed; m S3: Repeat step S2 for the remaining widths in the set W of candidate widths of the splicing area in sequence, and calculate the areas of the respective bounding rectangles corresponding to each of the remaining widths;

[0011] S4: Sort the calculated areas of the respective bounding rectangles in descending order to obtain a set A_i of the sorted areas of the bounding rectangles;

[0012] S5: Set the probability that the k-th bounding rectangle corresponding to the area of the k-th bounding rectangle in the set A_i of the areas of the bounding rectangles is selected to be

[0013] and select one of the bounding rectangles with this probability P, where |W| represents the size of the set A_i of the areas of the generated bounding rectangles; S6: Use the simulated annealing algorithm to rotate at least one polygon chip in the selected bounding rectangle, and through iterative optimization, calculate the area of the bounding rectangle after rotating the at least one polygon chip.

[0014] S7: Repeat steps S4 to S6, and successively determine whether the area of the bounding rectangle obtained by rotating the at least one polygon chip decreases,

[0015] where, if it is determined that the area of the bounding rectangle obtained by rotating the at least one polygon chip decreases, then output the bounding rectangle with the decreased area as the optimal splicing area.

[0016]

[0017] ​In a second aspect of the present application, an electronic device is further provided, including: a memory and a processor;

[0018] A computer program is stored in the memory, and when the computer program is executed by the processor, the multi-project wafer layout stitching method based on adaptive search is executed.

[0019] In a third aspect of the present application, a computer-readable storage medium is further provided, on which computer program instructions are stored. It is characterized in that when the computer program instructions are executed by a processor, the multi-project wafer layout stitching method based on adaptive search is implemented.

[0020] Based on adaptive search, the present application aims to search for an appropriate envelope rectangle size with as few iterations as possible, reducing the overhead of traditional MPW stitching algorithms. At the same time, in combination with the simulated annealing algorithm to optimize the rotation state of the polygons to be stitched, a high-quality solution can be obtained at a lower cost, thereby improving the wafer utilization rate during exposure.

[0021] Through the MPW stitching method based on random neighborhood search of the present application, the efficiency of MPW layout stitching design is also effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a cutting schematic diagram after placing polygonal chips according to an embodiment of the present application.

[0023] Figure 2 、 3 is a cutting schematic diagram after placing complex polygonal chips according to an embodiment of the present application.

[0024] Figure 4 is a flowchart of the MPW stitching method based on self-adaptive search according to the present application.

[0025] Figure 5 is an MPW stitching schematic diagram according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application belong to the scope of protection of the present application.

[0027] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are usually of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / ", generally represents an "or" relationship between the associated objects before and after.

[0028] A MPW splicing method based on random field search according to this application includes:

[0029] (1) Obtain the specification parameters of multiple chips and the constraint parameters of the bounding rectangle formed after splicing the multiple chips. The bounding rectangle is defined as: the smallest rectangle formed after all chips are spliced.

[0030] In one implementation, obtaining the specification parameters of the chips includes obtaining parameters such as the shape and area of each chip. The multiple chips to be spliced respectively have polygon design patterns of the same or different shapes, and the polygon design patterns include pentagrams, triangles, circles, squares, etc. This application does not limit the shape of each chip.

[0031] The specification constraint parameters of the bounding rectangle formed after splicing include the height and width of the bounding rectangle. For example, the height of the bounding rectangle is limited to the interval [H min , H max , and the width is limited to the interval [W min , W max . The upper limit value of the height or width interval of the above bounding rectangle can be preset by the user.

[0032] In one implementation, obtain data such as the specification parameters of multiple chips and the constraint parameters of the bounding rectangle formed after splicing based on the user's input.

[0033] In one implementation, directly extract data such as the specification parameters of multiple chips and the constraint parameters of the bounding rectangle formed after splicing from a database or a memory.

[0034] In one implementation, data such as the specification parameters of multiple chips and the constraint parameters of the envelope rectangle formed after splicing are obtained from a server. Here, the server can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, and big data and artificial intelligence platforms.

[0035] (2) Construction of the initial solution, that is, calculating the initial placement coordinates of all polygonal chips within the splicing area and the initial area of the envelope rectangle.

[0036] The user inputs the shape parameters of multiple chips to be spliced, including geometric shapes, areas, etc. At the same time, the user inputs the constraint parameters such as the length and width of the envelope rectangle formed after splicing, so as to constrain the splicing area generated by the splicing algorithm of this application. Here, the splicing area is the constraint area specified by the user for splicing multiple chips, and the envelope rectangle is the area occupied by multiple chips obtained after actual splicing.

[0037] In this application, first calculate the total area tol_area of multiple polygonal chips to be spliced, and at the same time define:

[0038]

[0039] min_width is the minimum width of the set splicing area, and max_width is the maximum width of the set splicing area; in one example, define the candidate width set of the set splicing area as:

[0040] W = {max{W min , min_width}, max{W min , min_width} + 1, …, min{W max , max_width}}, that is, the length interval of the candidate widths of the set splicing area is 1 length unit (step size), and it takes values between the minimum width and the maximum width.

[0041] For the construction of each initial solution in the candidate width set of the set splicing area, this application adopts a heuristic algorithm to sort multiple polygonal chips to be spliced in descending order of area, and each time place the polygonal chips at the lower left corner of the free rectangle of the candidate splicing area in the order of from large to small arranged before. The specific process is as follows:

[0042] (a) For multiple candidate splicing areas set according to the candidate width set, first arbitrarily select a width W from the candidate width set W of the splicing area _m, define it as the width of the initial splicing area, and set the height of the initial splicing area to the maximum height H_max of the splicing area;

[0043] In an implementable manner, the initial rectangular area for internally placing multiple chips is the above-mentioned initial splicing area. Sort i (i is a natural number greater than 1) polygon chips to be spliced in descending order of area to obtain the area set A of the i polygon chips to be spliced after area sorting _i .

[0044] According to the area set A of the i polygon chips to be spliced after area sorting _i , place each chip in turn at the lower left corner of the above-mentioned initial splicing area (free rectangle), and record the coordinates of the placed chips in turn. After each chip placement is completed, the above-mentioned initial splicing area (free rectangle) will be cut based on the placed chip to generate a sub-splicing area (i.e., a sub-free rectangle).

[0045] As Figure 1 shown, first place the polygon chip 1 to be spliced. After placing the next polygon chip 2 to be spliced, two new free rectangles are generated.

[0046] In an implementable manner, there may be complex polygon chips among the i polygon chips to be spliced. For complex polygon chips, after sorting them according to the area size and placing them in the above-mentioned initial splicing area, the cutting results of the splicing area (free rectangle) based on the placed complex polygon chips are as Figure 2 、 Figure 3 shown.

[0047] The cutting algorithm used by this application to cut the splicing area (free rectangle) is similar to the trapezoidal cutting and maximum rectangle cutting in the vertical direction based on the placed chips. The cut rectangles always tend to have the bottom side falling on the boundary of the splicing area (free rectangle) or the placed polygon chips, and their aspect ratios tend to be close to 1. Make vertical tangents (as shown by the dotted lines) to the vertices of the remaining available splicing area ( Figure 2 、 3 the white area inside the border in), obtain several rectangles, and score each rectangle according to these two rules of trapezoidal cutting and maximum rectangle cutting in the vertical direction based on the placed chips.

[0048] In one implementable manner, scoring each newly formed rectangle relies on a cost function, that is, the total score score = A + B + C; where the value of A is affected by the aspect ratio of each newly formed rectangle. The closer the aspect ratio is to 1:1, the higher the score; the value of B is affected by the proportion of the bottom suspension length of each newly formed rectangle. The smaller the proportion of the suspension length, the higher the score; the value of C is affected by the area of each newly formed rectangle itself. When the area is too small, the score is very low or even a negative score is given to avoid the appearance of overly small rectangles.

[0049] In this application, if the total score of the newly formed rectangles near a certain vertex is too low, a horizontal tangent is made to this vertex and the above scoring operation is repeated. After several iterations, the cutting result with a higher total score is selected.

[0050] (b) Repeat the above process until all the polygonal chips are placed. At this time, an initial envelope rectangle formed by placing the plurality of chips is generated, and then record the initial envelope rectangle corresponding to the initial width W at this time _m and calculate the area W of the initial envelope rectangle _m ×H _max and denote it as A _m

[0051] (3) Adaptive selection search algorithm

[0052] Since only one candidate width of the splicing area (i.e., the initial splicing width) is selected when generating the initial solution (i.e., obtaining the placement coordinates of all polygonal chips in the splicing area and the area of the envelope rectangle) in step (2), the optimality of the solution cannot be guaranteed. This application adopts an adaptive selection search algorithm to improve the quality of the initial solution through iteration. The main steps are as follows:

[0053] a) For each width ∈ W in the set of candidate widths of the splicing area, construct an initial solution (i.e., obtain the placement coordinates of all polygonal chips in the splicing area and the corresponding area of the envelope rectangle) in turn using the method in step (2), and record the placement coordinates of all polygonal chips in the splicing area corresponding to each width and the area of the envelope rectangle

[0054] b) Sort the calculated areas of the envelope rectangles in a decreasing manner to generate a set A of the areas of the envelope rectangles _i .

[0055] c) Set the probability that the k-th envelope rectangle in the generated set A_i of the areas of the envelope rectangles is selected as and select one of the envelope rectangles (such as the k-th envelope rectangle) to enter the next step with this probability P, where |W| represents the size of the generated set A of the areas of the envelope rectangles _i .

[0056] In this application, there are |W| envelope rectangles corresponding to each area in the set of areas of the generated envelope rectangles. The selected probability corresponding to each envelope rectangle is calculated, and the sum of the selected probabilities of all envelope rectangles is 1.

[0057] The value of k is not known before selecting the envelope rectangle. After the selection is completed, the value of k is obtained, and rotation optimization is performed in the subsequent process.

[0058] d) For the k-th envelope rectangle selected based on the above probability, use the simulated annealing algorithm to rotate at least one polygon chip in the k-th envelope rectangle (see the detailed process below). Through iterative optimization, calculate the latest envelope rectangle area A obtained by the above rotation. k 。

[0059] e) Repeat steps (b) to (d) multiple times. Each time the iterative rotation optimization process is repeated, determine whether the area of the envelope rectangle obtained by rotating and optimizing the at least one polygon chip decreases. If it is determined to decrease, output the envelope rectangle with the decreased area as the optimal splicing area, and update the set A of envelope rectangle areas based on the envelope rectangle with the decreased area. i 。

[0060] Among them, the specific process of rotating the polygon chip in the k-th envelope rectangle using the simulated annealing algorithm is as follows:

[0061] The simulated annealing algorithm optimizes the rotation state of the polygon chip: maintain an array x with the same size as the number of polygon chips. Each element in the array x records the rotation direction of each polygon chip, which represents the current rotation state of each polygon chip. In step d), the following simulated annealing algorithm iteration is performed:

[0062] d-1: Let T = T0, which represents the initial annealing temperature. Randomly generate an initial rotation state x0, and calculate the corresponding objective function value E(x0) = A0 using the method of constructing the initial solution in step (2), that is, the area of the envelope rectangle obtained in the current rotation state.

[0063] d-2: Let T = kT, where k ranges from 0 to 1 and is the temperature reduction rate.

[0064] d-3: Apply a random perturbation to the current rotation state to generate a new state x t+1 , calculate E(x t ), and calculate ΔE = E(x t+1 ) - E(x t )

[0065] d - 4: If ΔE < 0, accept the new state transition; otherwise, according to the probability e -ΔE / kT Determine whether to accept the new solution. If the solution is not updated, the temperature will not decrease. After iterating a certain number of times at the current temperature, whether the solution is updated or not, the temperature will decrease and enter the next iteration round.

[0066] d - 5: Repeat steps d - 1 to d - 4, and determine whether the temperature reaches the termination temperature level. If it reaches, terminate the algorithm; otherwise, return to step d - 2.

[0067] Figure 4 It is the MPW stitching flowchart based on the adaptive selection search algorithm according to the present application.

[0068] Refer to Figure 4 , the MPW stitching method based on the adaptive selection search algorithm of the present application includes the following steps:

[0069] S1: Obtain the specification parameters of multiple chips and the constraint parameters of the bounding rectangle formed after splicing multiple chips

[0070] The specification parameters of multiple chips include the number, shape, or area of the polygonal chips to be spliced. In this example, assume the number of polygonal chips to be spliced is, for example, 80; the designed shapes of the polygonal chips include pentagrams, triangles, circles, squares, etc.

[0071] Obtaining the constraint parameters of the bounding rectangle formed after splicing multiple chips includes obtaining the height and width limits [W min , W max , [H min , H max .

[0072] S2: Sequentially place multiple polygonal chips within the specified splicing area, calculate the coordinates of all the placed polygonal chips, and the area of the bounding rectangle actually formed after splicing the polygonal chips

[0073] In this step S2, first, implement the adaptive selection search algorithm to obtain the optimal splicing area width. The main steps are as follows:

[0074] a) For each candidate width of the splicing area ∈ W, use the method in step (2) to construct an initial solution, that is, calculate the placement coordinates of all the polygonal chips within the splicing area, obtain the corresponding height and the area of the bounding rectangle from the splicing area according to the placement coordinates, and then record the height corresponding to each candidate width of the splicing area and the area of the bounding rectangle.

[0075] b) Sort the calculated areas of the bounding rectangles in a decreasing manner to generate the area set A_ i .

[0076] c) The area A_ of the generated bounding rectangle i Let the probability that the k-th bounding rectangle in the set is selected be According to the probability to select one of the bounding rectangles, such as the k-th bounding rectangle, where |W| represents the size of the set A_ of the areas of the generated bounding rectangles i and |W| = 80.

[0077] d) For the k-th bounding rectangle selected according to the above probability, use the simulated annealing algorithm to rotate at least one polygon chip in the k-th bounding rectangle, and through iterative optimization, calculate the corresponding area A of the bounding rectangle obtained after the above rotation k .

[0078] As above, in this application, every time an iterative rotation optimization process is repeated, it is determined whether the area of the bounding rectangle obtained by rotating and optimizing the at least one polygon chip is reduced. If it is determined to be reduced, the bounding rectangle with the reduced area is output as the optimal splicing area, and at the same time, the set A_ of the areas of the bounding rectangles is updated based on the bounding rectangle with the reduced area i .

[0079] Among them, in this application, the rotation of the polygon based on the simulated annealing algorithm is optimized as follows:

[0080] Set an array x, the size of this array x is the same as the number of polygon chips, where each element in the array x records the rotation direction of each polygon, representing the current rotation state, and the following simulated annealing algorithm iteration is performed in step S2:

[0081] d-1: Let T = T0, representing the starting annealing temperature, randomly generate an initial rotation state x0, and use the method of constructing the initial solution in (2) to calculate the corresponding objective function value E(x0) = A0, that is, the area of the bounding rectangle obtained in the current rotation state.

[0082] d-2: Let T = kT, where k ranges from 0 to 1 and is the temperature reduction rate. In this example, k = 0.05 is taken

[0083] d-3: Apply a random perturbation to the current rotation state to generate a new state x in its neighborhood t+1 , calculate E(x t ), and calculate ΔE = E(x t+1 ) - E(x t )

[0084] d-4: If ΔE < 0, accept the new state transition, otherwise with probability e -ΔE / kTDetermine whether to accept the new solution

[0085] d-5: Repeat steps d-2 to d-4 to determine whether the temperature reaches the termination temperature level. If it reaches, terminate the algorithm; otherwise, return to step d-2.

[0086] a) Repeat steps (c) to (d) N times. If A k decreases, update A k , and re-sort the candidate width set W.

[0087] S3: Generate the optimal stitching area (i.e., the free rectangle) based on the optimal stitching area width obtained in step S2, and place multiple polygon chips in this optimal stitching area. The specific process is as follows:

[0088] S3-1: Set the optimal stitching area width as the width of the stitching area for placing multiple chips, and set the height of the optimal stitching area as the maximum height H max . Sort the multiple polygon chips to be stitched in descending order of area, and then place each chip in turn at the lower left corner of the optimal stitching area. During the placement process, the optimal stitching area will be cut to generate sub-stitching areas. As Figure 1 shown, after placing the next polygon chip, two new sub-stitching areas are generated; for complex polygons, the cutting of the stitching area is as Figure 2 , Figure 3 shown.

[0089] S3-2 Repeat the above process until all polygon chips are placed, record the width W i and height H i of the bounding rectangle at this time, calculate the area W i ×H i , denoted as A i

[0090] After Figure 4 a series of processes as above, the result shown in Figure 5 is obtained. It can be seen from Figure 5 that the MPW layout stitching method based on adaptive search described in this application can minimize the area of the rectangular region composed of multiple polygon chips, and the space utilization rate of the wafer layout is very high, which can prove the effectiveness of the algorithm.

[0091] As described above, the embodiments of the present application reduce the overhead of the traditional MPW stitching algorithm. At the same time, by cooperating with the simulated annealing algorithm to optimize the rotation state of the polygon chips to be stitched, a high-quality solution can be obtained at a lower cost, thereby improving the wafer utilization rate during exposure and effectively improving the efficiency of MPW layout stitching design.

[0092] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory. When the computer program is executed by the processor, the above-mentioned method can be executed.

[0093] Among them, the processor in the electronic device for executing the above method can be a newly designed one or obtained by improving the processing unit of an existing processor. The types of existing processing units can include but are not limited to: Central Processing Unit (CPU), Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, and can also include a microprocessing unit or a processing unit of other conventional processors.

[0094] The memory of the electronic device can be used to store program instructions executable by the processor (such as application programs, drivers, and even program instructions of the operating system). The processor in the electronic device for executing the above method is configured to execute the computer program stored in the memory, thereby implementing the above method.

[0095] Optionally, the electronic device may further include more components, such as a power supply component, a wired or wireless network interface, and an input / output interface. The exemplary components of the electronic device should not be construed as a limitation to the present application.

[0096] The present application also provides a readable storage medium. A program or instruction is stored on the readable storage medium. When the program or instruction is executed by the processor, each process of the above-mentioned MPW layout stitching method based on adaptive search is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be elaborated here.

[0097] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the spirit and scope protected by the present application and the claims, and all of them belong to the protection scope of the present application.

Claims

1. A splicing method for multi-project wafer layout based on adaptive search, characterized in that Including: S1: Obtain multiple chip specification parameters and the constraint parameters of the bounding rectangle formed after splicing multiple chips; S2: Select an arbitrary width \(W\) from the set \(W\) of candidate widths of the set splicing region m as the initial width of the set splicing region, set the initial height of the set splicing region to the maximum height \(H_{max}\) of the splicing region, sort the multiple polygonal chips to be spliced in descending order of area and sequentially place them in the set splicing region, and calculate the area of the bounding rectangle after all the polygonal chips corresponding to the initial width \(W\) m are placed; S3: Repeat step S2 for the remaining widths in the candidate width set W of the splicing region in sequence, and calculate the areas of the respective bounding rectangles corresponding to each of the remaining widths; S4: Sort the calculated areas of the respective bounding rectangles in descending order to obtain the set A_i of the areas of the sorted bounding rectangles; S5: Set the probability that the k-th envelope rectangle corresponding to the area of the envelope rectangles in the set \(A_i\) is selected as and select one of the envelope rectangles with this probability \(P\), where \(|W|\) represents the size of the set \(A_i\) of the areas of the generated envelope rectangles; S6: Use the simulated annealing algorithm to rotate at least one polygon chip in the selected bounding rectangle, and through iterative optimization, calculate the area of the bounding rectangle after rotating the at least one polygon chip; S7: Repeat steps S4 to S6, and successively determine whether the area of the bounding rectangle obtained by rotating the at least one polygon chip decreases, wherein, if it is determined that the area of the bounding rectangle obtained by rotating the at least one polygon chip decreases, then use the bounding rectangle with the decreased area as the optimal splicing region for output.

2. The splicing method according to claim 1, characterized in that If it is determined that the area of the bounding rectangle obtained by rotating the at least one polygon chip does not decrease, then continue to repeat the iterative optimization process of steps S4 to S6.

3. The splicing method according to claim 1, wherein Place multiple polygon chips based on the width of the optimal splicing region.

4. An electronic device, characterized in that, Including: A memory and a processor; A computer program is stored in the memory, and when the computer program is executed by the processor, it executes the multi-project wafer layout splicing method based on adaptive search according to any one of claims 1-3.

5. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the multi-project wafer layout splicing method based on adaptive search according to any one of claims 1-3.

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