FPGA-based power line channel feature acquisition device and generation method

Abstract

The application provides a kind of power line channel feature acquisition device and generation method based on FPGA, belongs to the technical field of power line carrier communication, including power line coupler, band pass filter, FPGA host, D / A digital-analog converter, A / D analog-digital converter, SD memory card, VAE generation model.The application generates OFDM signal through FPGA host, sends to power line and couples to receive, stores channel signal, uses the stored signal to give the general method for constructing power line channel feature dataset, and completes VAE generation model verification, to accurately build low-voltage power line channel model;It can realize long-time mounting of power line channel channel feature and accurate modeling of field channel feature, with long-time mounting, portability, safety, high flexibility.

Description

Technical Field

[0001] This invention relates to the field of power line carrier communication technology, and specifically to an FPGA-based power line channel feature acquisition device and generation method. Background Technology

[0002] Power line communication uses power lines as communication channels, offering advantages such as comprehensive coverage, cost-effectiveness (allowing for independent networking without additional cabling), and significant advantages in solving the "last mile" communication problem. However, as a power energy transmission network, power line networks were not designed with communication in mind, resulting in severe attenuation of high-frequency signals and a harsh, complex channel characteristic environment. Therefore, research into the channel characteristics of power line communication channels is becoming increasingly important to ensure communication reliability and improve communication speed.

[0003] In power line channel acquisition, signal generators and oscilloscopes are commonly used for power line channel feature sampling. While current equipment meets basic channel feature sampling requirements, it suffers from limited signal transmission, inconvenience, and poor long-term data acquisition and storage capabilities. This device utilizes an FPGA as its core system and an SD card as its channel feature storage device. It features small size, long-term mounting capability, and convenient data extraction and processing. It also facilitates storage expansion and file management, providing reliable data for the subsequent construction of a power line channel feature database.

[0004] Current research on power line channel characteristic modeling mostly uses simulation-generated data or computational data from formula-based inference models as training datasets. However, there are still differences between theoretical and actual data, and a general method for constructing power line channel characteristic datasets is lacking. Summary of the Invention

[0005] The purpose of this invention is to provide an FPGA-based power line channel feature acquisition device and generation method to solve at least one of the technical problems in the background art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] On one hand, the present invention provides a power line channel feature acquisition device, comprising:

[0008] The FPGA master controller is used to generate test signals for the incoming power line and receive the buffered data of the power line. The buffered data is stored in the SD card through the communication protocol to store the power line channel characteristics.

[0009] The output of the FPGA main controller is connected to a D / A digital-to-analog converter, the output of the D / A digital-to-analog converter is connected to a first bandpass filter, the output of the first bandpass filter is connected to a first coupler, and the first coupler sends the test signal to the power line.

[0010] The second coupler receives buffered data returned from the power line. The output of the second coupler is connected to the second bandpass filter. The output of the second bandpass filter is connected to the A / D digital-to-analog converter. The A / D analog-to-digital converter is connected to the input of the FPGA main controller. The FPGA main controller stores the acquired signal to the SD card.

[0011] Furthermore, the FPGA controller includes a DDS signal generation module; the DDS signal generation module sends a quantized preamble sequence to the D / A digital-to-analog converter to generate an analog waveform; wherein, the preamble sequence consists of 10.5 SYNCPs and 2.5 SYNCMs; wherein, SYNCP is defined as: The P symbol is quantized to generate a MIF table; the required waveform is read from the ROM core of the DDS signal generation module.

[0012] Furthermore, the FPGA controller also includes a clock management module, which generates a system clock signal and divides it to generate clocks of different frequencies.

[0013] Furthermore, the FPGA controller also includes an A / D receive buffer module, which provides a clock to the A / D analog-to-digital converter and buffers the received data into a data buffer FIFO.

[0014] Furthermore, the FPGA controller also includes an SD card control module for storing FIFO data into the SD card for subsequent processing.

[0015] Furthermore, the SD card control module includes a clock manager module, a data receiving control module, a receiving indicator, an SD card initialization module, an SD card writing data module, and an SD card reading data module. Specifically, when the SD card storage is nearly full, the data is uploaded to the server via the SD card reading module, ensuring the module remains mounted for extended periods without data loss.

[0016] Furthermore, a 1:1 high-frequency transformer is used to connect the first coupler to the first bandpass filter and the second coupler to the second bandpass filter.

[0017] Secondly, the present invention provides a method for generating power line channel features based on the device described in the first aspect. Since the received data stored on the SD card has voltage bias and the data format is inconsistent with the data format processed by the subsequent neural network, the data in the SD card is converted into actual values; the data is imported into MATLAB and labeled with different tags according to different sampling times to obtain training data; the VAE network uses latent variables to capture the features of the training data, thereby realizing new data with similar characteristics to the training data.

[0018] Furthermore, in the VAE network, the average vector and dispersion vector are calculated from the input data by the Encoder, and then the hidden variables are obtained according to the normal distribution of the average vector and dispersion vector. Finally, the original data is reproduced by the Decoder, thereby realizing channel generation.

[0019] Furthermore, after obtaining the vector of actual values, the P symbols are divided into n n*1024 matrices composed of P(0,1,2,...n) symbols according to their length. These matrices are then sampled at m-step intervals to obtain multiple m*1024 matrices. The mean of one step is used to compress m sets of data information to identify abnormal data.

[0020] The beneficial effects of this invention are as follows: An FPGA-based power line channel feature acquisition and generation device and method converts the signal generated by the FPGA into an analog signal on a D / A board, amplifies its power, and then injects it into the power line channel through a bandpass filter and high-frequency coupling circuit. The signal is received on the A / D board via a coupler and bandpass filter circuit. The FPGA buffers the data and transfers it to an SD card. A power line channel feature dataset is constructed based on the stored data, and a VAE-based network is used for training. This enables channel feature acquisition and modeling under real-world channel conditions.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of the invention. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a functional principle structure block diagram of the FPGA-based power line channel feature acquisition device described in an embodiment of the present invention.

[0024] Figure 2This is a block diagram illustrating the functional principle of the power line bandpass coupling filter according to an embodiment of the present invention.

[0025] Figure 3 This is a block diagram illustrating the functional principle structure of the D / A board according to an embodiment of the present invention.

[0026] Figure 4 This is a block diagram illustrating the functional principle structure of the FPGA internal module according to an embodiment of the present invention.

[0027] Figure 5 This is a block diagram illustrating the functional principle structure of the DDS module according to an embodiment of the present invention.

[0028] Figure 6 This is a block diagram illustrating the functional principle of the SD card storage module according to an embodiment of the present invention.

[0029] Figure 7 This is a flowchart illustrating the construction of a channel feature dataset according to an embodiment of the present invention.

[0030] Figure 8 This is a block diagram illustrating the functional principle of the VAE generator network as described in an embodiment of the present invention. Detailed Implementation

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0032] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0033] It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as here.

[0034] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or groups thereof.

[0035] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0036] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In the description of this specification, the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this technology and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this technology.

[0038] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection or setting, a detachable connection or setting, or an integral connection or setting. Those skilled in the art can understand the specific meaning of these terms in this art according to the specific circumstances.

[0039] To facilitate understanding of the present invention, the present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments. However, the specific embodiments do not constitute a limitation on the embodiments of the present invention.

[0040] Those skilled in the art should understand that the accompanying drawings are merely schematic diagrams of embodiments, and the components in the drawings are not necessarily essential for implementing the present invention.

[0041] This embodiment provides an FPGA-based power line channel feature acquisition device, including a power line coupler (including a first coupler and a second coupler), a first bandpass filter, a second bandpass filter, an FPGA main controller, a D / A digital-to-analog converter (DAC), an A / D analog-to-digital converter (A / D converter), an SD memory card, and a VAE generation model. The output of the FPGA main controller is connected to the D / A DAC, and the output of the D / A DAC is connected to the first bandpass filter. The first bandpass filter, connected to the first coupler, sends signals to the power line, which receives the signals. The second coupler is connected to the second bandpass filter, which is connected to the A / D DAC. The A / D DAC is connected to the input of the FPGA main controller, which stores the acquired signals to the SD card. When the SD card is nearly full, the data is uploaded to a server. The D / A DAC converts the FPGA digital signals into differential analog signals and amplifies the power. The A / D DAC converts the received channel feature signals into digital signals and transmits them to the FPGA main controller. The first and second couplers isolate high-voltage and low-voltage signals, provide surge transient interference protection, and include a protective enclosure against electric shock. The first and second bandpass filters isolate out-of-band channel characteristics. The first bandpass filter performs impedance matching between the D / A converter and the FPGA controller output, and provides overvoltage protection. The second bandpass filter performs impedance matching between the A / D converter and the FPGA controller input, and provides overvoltage protection. The SD card stores the received power line channel signals.

[0042] The FPGA main controller (control chip) generates OFDM signals, outputs them through the D / A board (D / A digital-to-analog converter), receives and buffers data from the A / D board (A / D digital-to-analog converter), stores the buffered data in an SD card, uploads the data to the server, and provides a synchronization clock for each module. The stored data is used to construct a power line channel characteristic dataset, providing training data for the VAE generation network and achieving accurate channel modeling.

[0043] like Figure 1 , Figure 2 As shown, the device can be divided into a mounting section and a signal generation, acquisition, and storage section. The device receives and stores the input signal from the field power line. The FPGA controller generates a test signal, which is then transmitted to the power line via D / A conversion, amplification, filtering, and coupling. After coupling filtering, A / D conversion, and buffering, the FPGA stores the buffered data into an SD card via a communication protocol, thereby realizing the storage of power line channel characteristics.

[0044] like Figure 2As shown, the mounting system consists of a first coupler, a first bandpass filter, a second coupler, and a second bandpass filter. The coupler isolates low-voltage signals from high-voltage mains power, achieving an attenuation of over 140dB for low-frequency high-voltage signals, with ripple less than 1dB and attenuation less than 0.3dB in the high-frequency passband. A varistor element (MOV) is used at the power line contact point to protect the circuit from surges from the power line. A resistor (>1MΩ) is connected in parallel with a capacitor to reduce the accumulation of inter-electrode charge during prolonged hanging, which could lead to capacitance reduction and the danger of high-voltage peaks. An acrylic protective shell is added to the coupler section to protect operators from electric shock.

[0045] A 1:1 high-frequency transformer is used to connect the first coupler to the first bandpass filter, and the second coupler to the second bandpass filter, which reduces the module size and increases the portability of the device. The bandpass filter is a third-order π-type Butterworth filter designed according to the normalized filter design. The design bandwidth is 2-30MHz, the impedance is designed to be 50 ohms, and the out-of-band attenuation reaches more than 60dB. A bidirectional TVS diode is added at the signal end with a conduction voltage of ±5V to protect the preceding AD / DA circuit from overvoltage damage. A high-frequency coaxial cable with an SMA interface is used to connect to the preceding stage to ensure distortion-free signal transmission.

[0046] like Figure 3 As shown, the D / A board uses the AD9708 digital-to-analog converter chip; it supports a parallel update rate of up to 125MSPS. It features a flexible single-supply operating voltage range (2.7V to 5.5V) and low power consumption, making it ideal for portable and low-power applications, and meets current PLC communication specifications; the signal is differentially output, with the output at the SMA interface after being amplified by a subsequent power amplifier.

[0047] like Figure 4 The diagram shows the signal generation, acquisition, and storage section. The system uses an FPGA as its core, working in conjunction with an SD card, AD board, and DA board to form a storage unit, signal acquisition unit, and signal output unit. Internally, the FPGA can be divided into a clock management module, an SD card control module, an A / D receiver buffer module, and a DDS signal generation module. The clock management module divides the system clock and provides different frequency clocks to each module. The DDS module provides clock and data output signals to the D / A module. The receiver module provides the clock to the AD board and buffers the received data into a FIFO. The SD card stores the FIFO data into the SD card for subsequent processing.

[0048] like Figure 5The diagram shows the structure of the DDS module: Following the "Technical Specification for Interoperability of Low-Voltage Power Line Broadband Carrier Communication," the DDS module transmits a quantized preamble sequence. After transmission, the DA module generates an analog waveform. The preamble sequence consists of 10.5 SYNCPs and 2.5 SYNCMs. The definition of a SYNCP is: The P symbol is quantized to generate a MIF table; the required waveform is read from the ROM core of the DDS.

[0049] To address the discrepancy between the data speed, accuracy, and data volume required by the high-speed ADC and the timing of subsequent SD card storage, a data buffer module is needed to ensure that acquired data is not lost. The data buffer module is designed using a First-In-First-Out (FIFO) memory structure implemented on an FPGA, which can significantly increase the data flow rate and guarantee no data loss.

[0050] This device needs to be able to be mounted on the PLC for extended periods, so it requires a large storage capacity. Furthermore, to ensure subsequent data analysis and database establishment, the storage device also needs to be easily relocatable and installable.

[0051] SD memory cards are well-suited to device requirements due to their small size, high memory capacity, fast data transfer rate, good portability and high security.

[0052] like Figure 6 As shown, by analyzing the SD card control protocol specification, an FPGA-based SD card control system and its specific module division were designed. The SD card controller can be divided into six functional sub-areas: a clock manager module, a data receiving control module, a receiving indicator, an SD card initialization module, an SD card write data module, and an SD card read data module. Specifically, when the SD card storage is nearly full, the data is uploaded to the server via the SD card read data module, ensuring the module remains mounted for extended periods without data loss.

[0053] like Figure 7 As shown in this embodiment, after completing the power line channel acquisition, the system constructs an actual sampled PLC channel database for subsequent channel analysis and data generation. The currently acquired and stored data still needs to undergo numerical conversion, P-symbol partitioning, data augmentation, and labeling before a usable database can be constructed.

[0054] Because the received data stored on the SD card has voltage bias and a data format inconsistent with the subsequent neural network processing data format, it is necessary to convert the data on the SD card into actual numerical values. After obtaining the vector, the vector is divided into n n*1024 matrices composed of P (0,1,2,...n) symbols according to the length of the P symbol. The matrices are then sampled at m-step intervals to obtain multiple m*1024 matrices. The mean of one step is used to compress the m sets of data information. Since the mean is easily affected by extreme values, this method facilitates the identification of outlier data. The data is imported into MATLAB and labeled according to different sampling times. These labels are then used for subsequent neural network training.

[0055] like Figure 8 As shown, VAE uses latent variables to capture features of the training data, thereby generating new data with similar characteristics to the training data. In the VAE network, the average vector μ and the dispersion vector δ are first calculated from the input data by the Encoder. Then, the latent variable Z is obtained according to the normal distribution of the vectors. Finally, the original data is reproduced by the Decoder, thereby realizing channel generation.

[0056] The trained VAE neural network can be deployed on FPGA, server, or other devices to achieve integrated communication and measurement functions, enabling online learning using measurement data and improving communication quality.

[0057] In summary, the FPGA-based power line channel feature acquisition device described in this embodiment of the invention generates OFDM signals through an FPGA main controller, sends and couples the received and stored channel signals to the power line, uses the stored signals to provide a general method for constructing a power line channel feature dataset, and completes the verification of the VAE generation model, thereby accurately building a low-voltage power line channel model; it can realize long-term mounting of power line channel features and accurate modeling of on-site channel features, and has the characteristics of long-term mounting, portability, security, and high flexibility.

[0058] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, based on the technical solutions disclosed in the present invention, various modifications or variations that can be made by those skilled in the art without creative effort should be included within the scope of protection of the present invention.

Claims

1. A power line channel feature generation method based on a power line channel feature collection device, the power line channel feature collection device is based on FPGA, characterized in that, The power line channel feature acquisition device includes: an FPGA main controller, an A / D analog-to-digital converter, a D / A digital-to-analog converter, a first bandpass filter, a second bandpass filter, a first coupler, a second coupler, an SD card, and a VAE generation model; The FPGA master controller is used to generate test signals for the incoming power line and receive data from the buffered A / D analog-to-digital converter. The buffered data is stored in the SD card via a communication protocol to store the power line channel characteristics. The output of the FPGA main controller is connected to a D / A digital-to-analog converter, the output of the D / A digital-to-analog converter is connected to a first bandpass filter, the output of the first bandpass filter is connected to a first coupler, and the first coupler sends the test signal to the power line. The second coupler receives data returned from the power line. The output of the second coupler is connected to the second bandpass filter, and the output of the second bandpass filter is connected to the A / D converter. The A / D converter is connected to the input of the FPGA main controller. The FPGA main controller stores the acquired signal to an SD card. The stored data is used to construct a power line channel feature dataset, providing training data for the VAE network to train and obtain a VAE generation model. The VAE generation model is used to achieve accurate channel modeling. The FPGA controller includes a DDS signal generation module; the DDS signal generation module sends a quantized preamble sequence to the D / A digital-to-analog converter to generate an analog waveform; wherein the preamble sequence consists of 10.5 SYNCPs and 2.5 SYNCMs; wherein a SYNCP is defined as: The P symbol is quantized to generate a MIF table; the required waveform is read from the ROM core of the DDS signal generation module. Because the received data stored on the SD card has voltage bias and a data format inconsistent with the subsequent neural network processing data format, the data on the SD card is converted into actual numerical values. This data is then imported into MATLAB and labeled with different tags according to different sampling times to obtain training data. The VAE network captures the features of the training data through latent variables, thereby generating new data similar to the training data. After obtaining the vector of actual numerical values, it is divided into n n*1024 matrices composed of P (0,1,2,...n) symbols according to the length of the P symbol. These matrices are then sampled at m-step intervals to obtain multiple m*1024 matrices. The mean of one step is used to compress m sets of data information to identify abnormal data.

2. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 1, characterized in that, The FPGA controller also includes a clock management module, which generates a system clock signal and divides it to generate clocks of different frequencies.

3. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 2, characterized in that, The FPGA controller also includes an A / D receive buffer module, which provides a clock to the A / D analog-to-digital converter and buffers the received data into the data buffer FIFO.

4. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 3, characterized in that, The FPGA controller also includes an SD card control module, which is used to store FIFO data into the SD card for subsequent processing.

5. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 4, characterized in that, The SD card control module includes a clock manager module, a data receiving control module, a receiving indicator light, an SD card initialization module, an SD card writing data module, and an SD card reading data module.

6. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 5, characterized in that, The first coupler and the first bandpass filter, and the second coupler and the second bandpass filter are both connected by a 1:1 high-frequency transformer.

7. The method for generating power line channel features based on a power line channel feature acquisition device according to claim 1, characterized in that, In a VAE network, the average vector and dispersion vector are calculated from the input data by the Encoder. Then, the hidden variables are obtained according to the normal distribution of the average vector and dispersion vector. Finally, the original data is reproduced by the Decoder, thereby realizing channel generation.

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