Self-shielding encapsulation

Abstract

This disclosure relates to a self-shielding package. One method for preventing electromagnetic field leakage to the outside of a module is an electric wall. Embodiments of this disclosure relate to simulating an electric wall with vias. The vias may be arranged around cavities in a printed circuit board. The density of the vias may be selected based on the expected wavelength of the electromagnetic field. The printed circuit board may then self-isolate components within the cavity from the electromagnetic field.

Description

Technical Field

[0001] This invention generally relates to semiconductor packaging, and more specifically to protecting semiconductor packaging from electromagnetic fields (EMF). Background Technology

[0002] There is a consistent demand for reducing the physical size of solid-state modules in electronic products such as cellular phones, personal communication devices, and portable computers. Module size reduction is a driving factor in module design. Limiting factors affecting the height of solid-state modules include the printed circuit board (PCB) and the various dies mounted to either side of the PCB.

[0003] The module may include one or more dies. The dies may receive electromagnetic fields (EMF) that may contain electromagnetic interference (EMI) from the dies. The module may include shielding for the dies. For example, the module may be covered on the top layer of a PCB using a mold (e.g., an epoxy mold). The mold may then be covered with a sputtered shield. The sputtered shield may also be coupled to the PCB via one or more solder lines. The solder lines provide grounding to the sputtered shield, allowing the sputtered shield to act as an electromagnetic shield for the dies. Forming the mold, sputtered shield, and solder lines may require multiple processing steps, thus affecting the module's complexity and cost. Additionally, because the module occupies a considerable amount of PCB space, the overall thickness of the module is relatively high. In view of the above, one or more embodiments of this disclosure provide a module with a shield and reduced height. Summary of the Invention

[0004] According to one or more embodiments of the present disclosure, a printed circuit board is provided. In some embodiments, the printed circuit board includes a plurality of metal layers. In some embodiments, the plurality of metal layers includes a first metal layer, a second metal layer, and one or more intermediate metal layers. In some embodiments, the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer. In some embodiments, the first metal layer includes metal traces. In some embodiments, the printed circuit board includes one or more dielectric layers. In some embodiments, the one or more dielectric layers include a first dielectric layer disposed between the first metal layer and the one or more intermediate metal layers. In some embodiments, the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and the second metal layer. In some embodiments, the printed circuit board defines a first cavity recessed from the second metal layer. In some embodiments, the one or more intermediate metal layers include a metal layer disposed in the cavity. In some embodiments, the printed circuit board includes a plurality of vias. In some embodiments, the plurality of vias are coupled between the first metal layer and the second metal layer. In some embodiments, the plurality of vias are arranged around the periphery of the first cavity. In some embodiments, each of the plurality of vias is spaced apart from adjacent vias of the plurality of vias. In some embodiments, the metal traces are coupled to the plurality of vias.

[0005] According to one or more embodiments of this disclosure, an apparatus is described. In some embodiments, the apparatus includes a printed circuit board. In some embodiments, the printed circuit board includes a plurality of metal layers. In some embodiments, the plurality of metal layers includes a first metal layer, a second metal layer, and one or more intermediate metal layers. In some embodiments, the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer. In some embodiments, the first metal layer includes metal traces. In some embodiments, the printed circuit board includes one or more dielectric layers. In some embodiments, the one or more dielectric layers include a first dielectric layer disposed between the first metal layer and the one or more intermediate metal layers. In some embodiments, the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and the second metal layer. In some embodiments, a first cavity is defined in the second metal layer. In some embodiments, the one or more intermediate metal layers include a metal layer disposed in the cavity. In some embodiments, the printed circuit board includes a plurality of vias. In some embodiments, the plurality of vias are coupled between the first metal layer and the second metal layer. In some embodiments, the plurality of vias are arranged around the periphery of the first cavity. In some embodiments, each of the plurality of vias is spaced apart from its adjacent via. In some embodiments, the metal traces couple the plurality of vias. In some embodiments, the device includes a die. In some embodiments, the die is coupled to the metal layer disposed in the cavity.

[0006] According to one or more embodiments of this disclosure, an apparatus is described. In some embodiments, the apparatus includes a printed circuit board. In some embodiments, the printed circuit board includes a plurality of metal layers. In some embodiments, the plurality of metal layers includes a first metal layer, a second metal layer, and one or more intermediate metal layers. In some embodiments, the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer. In some embodiments, the first metal layer includes metal traces. In some embodiments, the printed circuit board includes one or more dielectric layers. In some embodiments, the one or more dielectric layers include a first dielectric layer disposed between the first metal layer and the one or more intermediate metal layers. In some embodiments, the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and the second metal layer. In some embodiments, a first cavity is defined in the second metal layer. In some embodiments, the one or more intermediate metal layers include a metal layer disposed in the first cavity. In some embodiments, the printed circuit board includes a plurality of vias. In some embodiments, the plurality of vias are coupled between the first metal layer and the second metal layer. In some embodiments, the plurality of vias are arranged in a rectangular pattern around the periphery of the first cavity. In some embodiments, the periphery of the first cavity is rectangular. In some embodiments, the metal traces are coupled to the plurality of vias according to a grid pattern. In some embodiments, the grid pattern includes a first portion of the metal traces disposed outside the rectangular pattern. In some embodiments, the grid pattern includes a second portion of the metal traces disposed inside the rectangular pattern. Attached Figure Description

[0007] A better understanding of the embodiments of the concepts disclosed herein will be achieved by considering the following detailed description. This description refers to included diagrams, which are not necessarily drawn to scale, and some features may be enlarged, omitted, or schematically represented for clarity. The same reference numerals in the diagrams may represent and refer to the same or similar elements, features, or functions. In the diagrams:

[0008] Figure 1A A side view depicting a module comprising a printed circuit board having cavities according to one or more embodiments of the present disclosure.

[0009] Figure 1B A top view depicting a module comprising a printed circuit board having cavities according to one or more embodiments of the present disclosure.

[0010] Figure 2A A side view depicting a module comprising a printed circuit board having multiple cavities according to one or more embodiments of the present disclosure.

[0011] Figure 2B A top view depicting a module comprising a printed circuit board having multiple cavities according to one or more embodiments of the present disclosure.

[0012] Figure 3 A side view depicting a module including a first printed circuit board and a second printed circuit board according to one or more embodiments of the present disclosure. Detailed Implementation

[0013] Before explaining one or more embodiments of this disclosure in detail, it should be understood that the embodiments are not limited in their application to the construction and arrangement of the components, steps, or methods set forth in the following description or illustrated in the drawings. In the following detailed description of the embodiments, numerous specific details are set forth to provide a more thorough understanding of this disclosure. However, those skilled in the art to which this disclosure pertains will understand that the embodiments disclosed herein can be practiced without some of these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating this disclosure.

[0014] As used herein, the letters following reference numerals are intended to refer to embodiments of features or elements that may be similar to (but not necessarily the same as) previously described elements or features having the same reference numerals (e.g., 1, 1a, 1b). Such shorthand symbols are used for convenience only and should not be construed as limiting this disclosure in any way unless expressly stated otherwise.

[0015] Furthermore, unless explicitly stated otherwise, "or" refers to inclusive "or" rather than exclusive "or". For example, condition A or B is satisfied by either of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0016] Additionally, the use of “a” can be used to describe an element or component of the embodiments disclosed herein. This is done for convenience only and “a” is intended to include “one” or “at least one”, and unless clearly indicated otherwise, the singular also includes the plural.

[0017] Ultimately, as used herein, any reference to “one embodiment” or “some embodiments” means that a particular element, feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment disclosed herein. The phrase “in some embodiments” appearing in different places in this specification does not necessarily refer to the same embodiment in all instances, and an embodiment may include one or more of the features expressly described or inherent in this document, or any combination or sub-combination of two or more such features, as well as any other features that are not necessarily expressly described or inherent in this disclosure.

[0018] It should be noted herein that, for the purposes of this disclosure, "coupling" can mean one or more of communicative coupling, electrical coupling, and / or physical coupling. When an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element may be directly connected to the other element, or that there may be an intermediary element between the elements. In contrast, when an element is referred to herein as "directly connected" or "directly coupled" to another element, it should be understood that there is no intermediary element in the "direct" connection between the elements. However, the presence of a direct connection does not preclude other connections in which intermediary elements may be present. It should be noted herein that "coupled between" can be understood as the movement or flow of a signal relative to two or more components, and may additionally include intermediary components therein. Similarly, descriptions of a particular component as "manufactured above another component," "located on another component," or "placed on another component" indicate the relative position of such components but do not necessarily indicate physical contact between such components. Such components may be in physical contact or may alternatively include intermediary elements. Electrical coupling or electrical connection can refer to the ability to allow electrical energy to flow between components. Mechanical coupling or mechanical attachment can refer to the physical support of a component.

[0019] The entire contents of U.S. Patent No. 10,827,617 entitled “Printed circuit board with cavity”, which lists Dingyou Zhang, Nitesh Kumbhat, Li Sun, Sarah Haney, and Chang Kyu Choi as inventors, are incorporated herein by reference.

[0020] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. Embodiments of this disclosure generally relate to modules. A module may include one or more printed circuit boards (PCBs) and one or more dies. The dies of the module may generate electromagnetic fields (EMF) that induce electromagnetic interference (EMI). The PCB may include shielding for reducing or blocking the EMF. The shielding may be implemented internally within the PCB. The ability to implement shielding internally allows for modules with a thinner profile compared to modules with sputtered shielding on a molded compound. An operational principle for EMF shielding may be to provide a conductive material connected to ground. The EMF may then induce a current in the conductive material, thereby reducing the intensity of the EMF.

[0021] For reference Figures 1A to 1BModule 100 is described according to one or more embodiments of this disclosure. Module 100 may also be referred to as a device. In embodiments, module 100 may be referred to as a radio frequency (RF) front-end module (FEM). Module 100 may be shielded from electromagnetic interference (EMI) for RF applications. Module 100 may be used in a variety of radio frequency (RF) applications, such as, but not limited to, radio frequency (RF) modules for mobile phones or other communication devices. In such RF applications, the design of module 100 may be sensitive to size and cost requirements. Module 100 may further include one or more filters, amplifiers, oscillators, etc. In some examples, the RF front-end is placed on the motherboard of the communication device. The RF front-end may be placed on the motherboard for filtering or amplifying signals from the communication device. It is also contemplated that module 100 may include applications other than as an RF module or RF front-end.

[0022] Module 100 may include one or more components, including but not limited to a printed circuit board 102 (PCB). The total height of module 100 may be determined by factors such as the thickness of the printed circuit board 102. Module 100 may also include one or more dies 104, molds 106, interconnects 108, metal layers 110, insulating layers 112, through-holes 114, annular rings 116, cavities 118, and / or interconnects 120. In embodiments, the printed circuit board 102 may include, be coupled to, or define one or more of the dies 104, molds 106, interconnects 108, metal layers 110, insulating layers 112, through-holes 114, annular rings 116, cavities 118, and / or interconnects 120.

[0023] Printed circuit board 102 may include a metal layer 110. The metal layer 110 may carry electrical signals or current. The metal layer 110 may be manufactured using any printed circuit board process. The metal layer 110 may be formed from any conductive material compatible with the manufacturing of the printed circuit board. For example, the material may include, but is not limited to, copper (Cu), gold (Au), silver (Ag), and / or aluminum (Al). The metal layer 110 may also be referred to as a metallization layer, a signal layer, and / or a conductive layer. The metal layer 110 may contain metal patterned to form paths (e.g., traces), components, etc. Components may include, but are not limited to, resistors (e.g., thin-film resistors (TFRs), etc.), capacitors (e.g., metal-insulator-metal (MIM) capacitors, deep trench capacitors (TC), metal-oxide-semiconductor (MOS) capacitors, metal edge capacitors, etc.), inductors (e.g., planar spiral inductors), transistors, etc. Components may be considered as being "integrated" by being formed from the metal layer 110. Integrating components into the printed circuit board 102 can help reduce the in-plane dimensions of the printed circuit board 102. Paths and / or components may be fabricated as patterned layers. Patterned layers can be formed using any suitable process, such as, but not limited to, photolithography. For illustration, a patterned layer can be formed by depositing a photoresist, exposing the photoresist with a pattern, etching the photoresist and one or more underlying materials to create a patterned structure.

[0024] Printed circuit board 102 may also include a dielectric layer 112. The dielectric layer 112 may be manufactured using any printed circuit board process. The dielectric layer 112 may be formed of any electrically insulating material compatible with the manufacture of the printed circuit board, such as, but not limited to, prepreg, resin-based dielectric materials (e.g., FR-4), phenylcyclobutene (BCB), etc. The dielectric layer 112 may also be referred to as an isolation layer, prepreg, core layer, etc. The dielectric layer 112 may be disposed between metal layers 110. Therefore, printed circuit board 102 may include metal layers 110 separated by the dielectric layer 112. The dielectric layer 112 may then electrically insulate the metal layers 110 to prevent unwanted signal leakage.

[0025] In this embodiment, the printed circuit board 102 can be considered as a multilayer PCB. The printed circuit board 102 may include multiple metal layers 110 and multiple dielectric layers 112. The metal layers 110 may include a first metal layer 110a, a second metal layer 110b, and one or more intermediate metal layers 110c. The intermediate metal layers 110c may be disposed between the first metal layer 110a and the second metal layer 110b. The first metal layer 110a may also be referred to as the top metal layer. The second metal layer 110b may also be referred to as the bottom metal layer. The metal layer 110 may be referred to based on its location. The dielectric layer 112 may be disposed between each of the first metal layer 110a, the intermediate metal layer 110c, and the second metal layer 110b, thereby insulating the layers. The dielectric layer 112 may include a first dielectric layer 112a, a second dielectric layer 112b, and one or more intermediate dielectric layers 112c. An intermediate dielectric layer 112c may be disposed between the first dielectric layer 112a and the second dielectric layer 112b. In an embodiment, a first metal layer 110a may be disposed above the first dielectric layer 112b. In an embodiment, a second metal layer 110b may be disposed below the second dielectric layer 112b. In an embodiment, the metal layers 110 may or may not have the same thickness.

[0026] For example, printed circuit board 102 is depicted as comprising seven metal layers 110, each separated by a dielectric layer 112, but this is not intended to be limiting. For the example depicted with seven metal layers, the first metal layer 110a may be referred to as metal layer 1 (M1) and the second metal layer 110b may be referred to as metal layer 7 (M7), wherein the intermediate metal layers 110c are referred to as metal layers 2 to 6 (M2 to M6). The concept can be extended to PCBs containing any number (n) of layers (e.g., Mn).

[0027] The printed circuit board 102 may further include one or more circuits formed across one or more of the metal layers 110. For example, the metal layers may be coupled by one or more vias (e.g., blind vias, buried vias, through-holes 114, etc.). The one or more vias may form one or more circuits across the metal layers via coupling paths, components, etc. The circuits may be arranged to achieve the desired function of the printed circuit board 102, such as, but not limited to, I / O circuitry systems for radio frequency (RF) modules. As can be understood, specific wiring may be coupled based on the desired circuitry, so the various diagrams provided herein are not intended to be limiting. In this way, single-layer or multi-layer circuits may be formed based on one or more patterned layers.

[0028] Although the printed circuit board 102 is described as including a metal layer 110 and a dielectric layer 112, this is not intended to limit the present disclosure. The printed circuit board 102 may further include a plurality of other layers for printed circuit board manufacturing, such as, but not limited to, a solder mask layer. For example, a solder mask layer (not depicted) may be applied over the first metal layer 110a and / or the second metal layer 110b.

[0029] In an embodiment, a printed circuit board 102 may define one or more cavities 118. In this regard, the printed circuit board 102 may be referred to as a cavity PCB. The cavity 118 may be defined by a second metal layer 110b. The cavity 118 may be recessed from the second metal layer 110b. A recess may refer to the formation of the cavity 118 in the surface of the printed circuit board 102 such that the surface does not flatten across the entire printed circuit board 102. The cavity may also be defined by one or more dielectric layers of the printed circuit board 102. The cavity 118 may refer to a hole in the surface of the printed circuit board through one or more intermediate metal layers 110c. As depicted, the cavity 118 is formed on the bottom surface, but this is not intended to be limiting. The cavity 118 may be formed from the printed circuit board 102 by any suitable process (e.g., etching, laser lift-off) or using a patternable photosensitive material. The intermediate metal layer 110c may contain a metal layer disposed within the cavity 118. The depth of cavity 118 can be selected based on the distance to the desired intermediate metal layer. Cavity 118 may contain one or more layers of cavity depth. For the illustrated example, cavity 118 contains a cavity depth of three layers from metallization layer M7, thereby exposing metallization layer M4, but this is not intended to be limiting. Therefore, cavity 118 exposes one of the one or more intermediate metal layers 110c.

[0030] In an embodiment, printed circuit board 102 includes one or more interconnects 120. Interconnects 120 may be disposed within a cavity 118. A metal layer disposed within the cavity 118 may include one or more interconnects 120. Interconnects may be coupled to an intermediate metal layer exposed by the cavity 118 (e.g., M4, for the depicted example). Interconnects 120 may include, but are not limited to, bumps, pads, lead pads, solder balls, etc. Interconnects 120 may be configured to be electrically coupled to die 104. For example, the metal layer disposed within the cavity 118 may include pads for coupling die 104. The metal layer disposed within the cavity 118 may be patterned to allow solder bumps to lead into the cavity 118. The solder bumps may be melted and wetted into the metal layer of printed circuit board 102 during reflow soldering, and then cooled to form solid joints with the interconnects 120.

[0031] In an embodiment, module 100 includes one or more dies 104. Cavity 118 may be configured to receive die 104. Receiving die 104 may mean that cavity 118 is sized sufficiently such that die 104 is at least partially disposed within cavity 118. In an embodiment, die 104 may be disposed within cavity 118. Disposing die 104 within cavity 118 reduces the pitch height of die 104 relative to printed circuit board 102 compared to attaching die 104 to the surface of printed circuit board 102. Reducing the pitch height of die 104 may benefit from reducing the overall height of module 100. The reduction in the height of module 100 may correspond to the cavity depth. In an embodiment, die 104 may be electrically coupled to a metal layer disposed within cavity 118 via interconnect 120, but this is not intended to be limiting.

[0032] Die 104 may contain any die suitable for printed circuit board manufacturing. For example, die 104 may contain, but is not limited to, power amplifier cores, multiplexers, switches, low-noise amplifiers, CMOS dies, silicon-on-insulator (SOI) dies, integrated passive device (IPD) dies, filter dies (e.g., diaphragm bulk acoustic resonator (FBAR) filters, surface acoustic wave (SAW) filters, a row of silicon capacitors, discrete passive components, etc. As used herein, passive may refer to inductors, resistors, capacitors, etc. Die 104 may be selected from any of the above to achieve the desired function of module 100.

[0033] In this embodiment, die 104 may emit and / or receive electromagnetic fields (EMF). EMF can unintentionally induce currents, also known as electromagnetic interference (EMI). EMF emitted by die 104 can induce EMI in electronic components surrounding die 104. Similarly, EMF received by die 104 can induce EMI within die 104. In some examples, die 104 and / or surrounding components may be sensitive to EMI, making EMF reduction desirable. EMF may contain both frequency and wavelength. For example, EMF may contain frequencies between 1 MHz and 10 GHz. As another example, EMF may contain wavelengths between 3 cm and 300 m.

[0034] In an embodiment, the printed circuit board 102 includes a shielding structure. The shielding structure reduces or blocks the intensity of EMF transmitted to and from the cavity 118. For example, the shielding structure may include measures to reduce the shielding efficiency or gain of the EMF. The shielding structure may include, but is not limited to, vias 114, annular rings 116, and / or metal traces 122. The vias 114, annular rings 116, and / or metal traces 122 may be configured to reduce or block the intensity of EMF transmitted to and from the cavity 118. The vias 114, annular rings 116, and / or metal traces 122 may be internal to the printed circuit board 102. Implementing a shielding structure via the printed circuit board 102 provides several advantages, including reducing the thickness of the module 100 and / or reducing the number of manufacturing steps in the module 100.

[0035] In an embodiment, the printed circuit board 102 includes a via 114. The via 114 can be manufactured using any printed circuit board process, such as, but not limited to, front-end or back-end processes. The via 114 can be formed of any conductive material compatible with the fabrication of the printed circuit board, such as the metal described with reference to metal layer 110. The via 114 can be coupled between a first metal layer 110a and a second metal layer 110b (e.g., through the printed circuit board 102, from top to bottom). The metal of the via 114 can then electrically couple the first metal layer 110a to the second metal layer 110b. This electrical coupling between the first metal layer 110a and the second metal layer 110b can be used to ground the first metal layer 110a. Grounding can refer to causing a voltage difference between the component and a reference point to approach zero. The via 114 can therefore act as a loop for electrical energy induced by the EMF.

[0036] In one embodiment, the through hole 114 is arranged around the cavity 118 (see...). Figure 1B For example, via 114 may be arranged around the periphery of cavity 118. Arranged around the periphery can refer to placing the via in a pattern that is spaced from the periphery and suitable for forming a via wall. Via 114 can be considered as forming a via wall through arrangement. The term via wall can indicate that electromagnetic waves will not leak outside of module 100. The via wall can isolate cavity 118 from the EMF around the sides of printed circuit board 102. Advantageously, via 114 can provide this isolation within printed circuit board 102. Via 114 can provide isolation and shielding to the outside and other components that may be present within printed circuit board 102. In an embodiment, the periphery of cavity 118 is rectangular. In an embodiment, via 114 may be arranged around cavity 118 according to a pattern. The pattern can define the location of via 114. For example, vias may be arranged around cavity 118 according to a rectangular pattern. In this regard, when arranged around the periphery of cavity 118, the periphery of the pattern of via 114 may also be rectangular. The through hole can be connected according to the pattern and spaced 128 from the adjacent through hole.

[0037] In an embodiment, via 114 may be spaced apart from adjacent vias by a gap or distance 128. Each of the adjacent vias in the pattern may be spaced apart by distance 128. The distance 128 between adjacent vias (e.g., gap distance) may be selected based on the expected wavelength of the EMF. Vias 114 may be considered as forming a via wall with the spacing between vias being sufficiently small relative to the wavelength. For example, the distance 128 between vias 114 may be approximately one-quarter of the wavelength or less. In an embodiment, the distance 128 between adjacent vias 114 may be selected based on the wavelength of the electromagnetic field received by the via 114. The distance 128 may be selected to be less than or equal to one-quarter of the received wavelength. Furthermore, the distance 128 between vias may or may not be the same as the diameter of the via. A distance 128 between vias the same as the diameter of the via can provide effective shielding. Die 104 may emit an electromagnetic field at a certain frequency. The electromagnetic field in the dielectric layer 112 may contain a frequency different from the frequency of the electromagnetic field in free space. In some examples, via 114 can receive electromagnetic fields from dielectric layer 112, with wavelengths in the high frequency (HF), very high frequency (VHF), ultra-high frequency (UHF), very high frequency (SHF), and extremely high frequency (EHF) bands. In this regard, the electromagnetic fields received by via 114 can contain frequencies up to GHz or higher. The distance 128 between adjacent vias can therefore be selected to shield against electromagnetic fields with frequencies up to GHz or higher. The distance 128 can be further reduced as the wavelength of the module decreases (e.g., as the component operates at higher frequencies). In embodiments, the distance 128 between vias can also be based on the diameter of via 114. The minimum gap distance between vias 114 can also be based on the technique used to manufacture the PCB. In embodiments, the distance 128 between vias can be between 20 mils and 50 mils. For example, the distance 128 between vias can be between 20 mils and 30 mils. As another example, the distance 128 between vias can be between 40 mils and 50 mils. The diameter of the via can similarly range from 20 mils to 50 mils. The spacing 128 can be selected based on the module, technology, and frequency of interest. PCB manufacturing may include design rules for the spacing between vias. Design rules may include minimum clearances. For example, the spacing 128 between adjacent vias can be between 20 mils and 30 mils (e.g., .002 to .003 inches, 0.0508 cm to 0.0762 cm), but this is not intended to be limiting. A spacing 128 between 20 and 30 mils can shield the cavity from electromagnetic fields with frequencies within the EHF band. For example, 30 mils may correspond to 0.762 mm, or one-quarter of a wavelength of 3.048 mm (e.g., 98.357 GHz). As another example, 20 mils may correspond to 0.508 mm, or one-quarter of a wavelength of 2.032 mm (e.g., 147.535 GHz). Therefore, the distance 128 between adjacent vias can accommodate bare dies operating at higher frequencies and lower wavelengths for EMF.

[0038] In an embodiment, the first metal layer 110a may include a metal trace 122. The metal trace 122 may be manufactured using any printed circuit board process. The metal trace 122 may typically contain any metal suitable for printed circuit board manufacturing, such as, but not limited to, the metal described with reference to metal layer 110. The metal trace 122 of the first metal layer 110a may act as an EMF shield on top of the printed circuit board 102. The metal trace 122 may couple each of the vias 114 to an adjacent via. The metal trace 122 may conduct signals between the vias. In this regard, the vias 114 may be electrically coupled by the metal trace 122. The metal trace 122 may then provide EMF shielding. The metal trace 122 and the vias 114 may be configured to reduce the intensity of the electromagnetic field (EMF) transmitted to and from the cavity 118.

[0039] In an embodiment, the metal trace 122 couples the via 114 according to a grid pattern. The grid pattern of the metal trace 122 may include a first portion 126a of the metal trace 122 disposed outside the pattern defining the via 114. The first portion 126a surrounding the outside of the pattern may be the largest rectangle touching each of the vias 114. The grid pattern of the metal trace 122 may also include a second portion 126b of the metal trace 122 disposed within the pattern defining the via 114. The second portion 126b may be the smallest rectangle touching each of the vias 114. The first portion 126a may be coupled to the second portion 126b at a via 114 located at a corner of the rectangular pattern. In an embodiment, the metal trace 122 is a rectangular grid pattern, wherein the pattern surrounding the cavity 118 and defining the location of the via 114 is rectangular. Each of the vias 114 is thus coupled to the metal trace 122. The grid pattern may also include coupling of the first portion 126a and the second portion 126b at the corner via. The grid pattern ensures that the area above the cavity 118 is not covered by the metal trace 122.

[0040] In an embodiment, metal layer 110 may include one or more of annular rings 116. Annular ring 116 may also be referred to as a copper pad or ground ring. In an embodiment, each of the metal layers 110 includes annular ring 116. For example, each of the metal layers 110 may include annular ring 116 for each of the vias 114. Vias 114 may then be each coupled to annular ring 116 in each layer of metal layer 110. Annular ring 116 may then couple vias 114 to one or more traces within metal layer 110. Annular rings 116 not coupled to traces within metal layer 110 may be referred to as unused annular rings or unused pads. It is further contemplated that each of the metal layers 110 may not include annular ring 116 for each of the vias 114.

[0041] In an embodiment, the printed circuit board 102 may include one or more interconnects 108. The interconnects 108 may be disposed beneath the second metal layer 110b. The interconnects 108 may be coupled to the second metal layer 110b of the printed circuit board 102. The interconnects 108 may include, but are not limited to, bumps, pads, lead pads, solder balls, etc. The interconnects 108 provide coupling between the printed circuit board 102 and an external ground reference. For example, the interconnects 108 may be coupled to another structure (e.g., external ground). In an embodiment, a via 114 may be coupled to one or more of the interconnects 108. The via 114 may then ground the first metal layer 110a, the metal trace 122, and / or the annular ring 116 to the interconnect 108. The via 114 coupled to the interconnect 108 serves to ground the first metal layer 110a, the via 114, and / or the annular ring 116. Coupling to the ground reference can result in the shielding structure having zero potential relative to the ground reference.

[0042] In an embodiment, the second metal layer 110b includes a metal trace 124. The metal trace 124 may be similar to the metal trace 122. The metal trace 124 may generally contain any metal suitable for printed circuit board fabrication, such as, but not limited to, the metal described with reference to metal layer 110. The metal trace 124 may serve as an EMF shield for the bottom of the printed circuit board 102. The metal trace 124 may couple each of the vias 114 to an adjacent via. The metal trace 124 may also couple to interconnect 108. The metal trace 124 may then serve as an EMF shield for the bottom of cavity 118. For example, the metal trace 124 may couple the vias 114 according to a grid pattern. The grid pattern of the metal trace 124 may be around and / or within the periphery of the vias 114 (e.g., see...). Figure 1B Although the second metal layer 110b is described as containing metal traces 124, this is not intended to limit the present disclosure. It is further contemplated that the bottom shielding of the cavity 118 may be provided by another structure, as will be referred to below. Figure 3 Further description.

[0043] In an embodiment, module 100 includes a mold 106. Mold 106 may also be referred to as a mold mask. Mold 106 may be formed of reinforced or unreinforced epoxy resin, epoxy molding compound (EMC), etc. Mold 106 may protect one or more portions of module 100 (e.g., die 104, cavity 118, bottom side of printed circuit board 102). Mold 106 may be disposed on the bottom side of printed circuit board 102. For example, mold 106 may be formed over and fill cavity 118. Mold 106 may then hermetically seal die 104. The hermetically sealed seal provides protection against environmental elements such as temperature and humidity. Although module 100 is described as including mold 106, this is not intended to limit the disclosure.

[0044] As depicted, the printed circuit board 102 does not include a mold coupled over the first metal layer 110a, a sputtered metal layer coupled over the mold, or bond wires coupled from the first metal layer 110a to the sputtered layer. Advantageously, the printed circuit board 102 can be EMI shielded without a mold, sputtered metal, and bond wires. Although the printed circuit board 102 is described as not requiring a mold coupled over the first metal layer 110a, this is not intended to limit the disclosure. It is contemplated that the module 100 may include a mold coupled over the first metal layer 110a to protect the first metal layer 110a.

[0045] For reference Figures 2A to 2B Further description: the printed circuit board 102 may define one or more additional cavities recessed from the second metal layer 110b. Vias 114 may also be arranged around the periphery of the one or more additional cavities. Vias 114 may then form via walls around the one or more additional cavities. Metal traces 122 may also be coupled to the vias around the periphery of the cavities (e.g., according to a grid pattern). The metal traces 122 and vias 114 may then be configured to reduce the intensity of the electromagnetic field transmitted between the cavity 118 and the one or more additional cavities.

[0046] For reference Figures 2A to 2B Module 200 is described according to one or more embodiments of this disclosure. The embodiments and implementation techniques previously described in the background of module 100 herein should be interpreted as extending to module 200. Module 200 may depict the wall of holes inside printed circuit board 102 to provide shielding between multiple cavities.

[0047] Module 200 may contain any number of cavities 202. Each cavity 202 may contain one or more dies 104. The number of cavities 202 may be selected based on the desired number of dies 104. In one example, cavity 202a may contain a power amplifier (PA) core, cavity 202b may contain a multiplexer and / or a switch, and cavity 202c may contain a low-noise amplifier (LNA). The dies may be selected based on the module architecture, such that the power amplifier core, multiplexer, switch, and low-noise amplifier are not intended to be limited.

[0048] In an embodiment, module 200 may provide EMF shielding between cavities 202. EMF shielding may be provided between dies 104 disposed within cavities 118 of printed circuit board 102. EMF shielding can facilitate increased functionality of module 100. Therefore, additional dies 104 may be added to module 200 to increase the functionality of module 100 without increasing EMF / EMI between dies.

[0049] In embodiments, vias 114 may be arranged in one or more rows 204. In embodiments, rows 204 may act as bore walls or internal shielding between cavities 202. Vias 114 may be located between cavities 202. Therefore, vias 114 provide shielding not only to and from the external EMF, but also to the interior and between dies 104, and from the interior and between dies 104. For example, module 200 is depicted as including cavities 202a to 202c and rows 204a to 204b. Rows 204a of vias may be disposed between cavities 202a and 202b. Rows 204b of vias may be disposed between cavities 202b and 202c. As will be understood, the term row may also refer to a column in which vias are applied depending on the orientation of the viewed module 200. Each of the cavities 202 may include a first portion 126a of a metal trace 122 disposed outside the pattern defining the via 114 and a second portion 126b of a metal trace 122 disposed within the pattern defining the via 114. The grid pattern may also include the first portion 126a and the second portion 126b coupled at corner vias in each of the cavities 202. The metal trace 122 for each of the cavities 202 may also be coupled at corner vias.

[0050] In this embodiment, the spacing between the vias 114 can be varied. The spacing between the vias 114 can vary between rows 204. The spacing can be selected based on the die within the respective cavity 202. Specifically, the via spacing can be decreased at higher frequencies and increased at lower frequencies. The spacing can be selected such that the spacing is approximately a quarter wavelength or less. This spacing of approximately a quarter wavelength or less is expected to provide sufficient attenuation for the EMF. However, increasing the spacing may be desirable to reduce the number of manufacturing steps required to manufacture module 200 (e.g., the number of drill holes used to create the vias). For example, row 204a may contain a first spacing between adjacent vias, and row 204b may contain a second spacing between adjacent vias, wherein the first spacing is greater than the second spacing.

[0051] For reference Figure 3 Module 300 is described according to one or more embodiments of this disclosure. The embodiments and implementation techniques previously described in the background of modules 100 and 200 should be interpreted as extending to module 300. Module 300 may depict a stacked PCB configuration. Module 300 may include printed circuit board 102 and printed circuit board 302. Printed circuit board 102 may be stacked on printed circuit board 302. The stacked PCB configuration may provide both external and internal shielding as will be described.

[0052] In embodiments, printed circuit board 302 may include, be coupled to, or define one or more of the following: dies 104, die 106, interconnects 108, metal layers 110 (e.g., metal layer 304), insulating layers 112, vias 114 (e.g., via 306), annular rings 116, cavities 118 (e.g., cavity 308), interconnects 120, and / or metal traces 122 (e.g., metal trace 310). Discussion of printed circuit board 102 is incorporated herein by reference to printed circuit board 302. For example, metal layer 304 may include a first metal layer 304a, a second metal layer 304b, and one or more intermediate metal layers 304c. As another example, printed circuit board 302 may define one or more cavities 308 recessed from the second metal layer 304b.

[0053] In this embodiment, the printed circuit board 302 can be considered as a multilayer PCB. The printed circuit board 302 may include multiple metal layers 304 and multiple dielectric layers. The metal layers 304 may include a first metal layer 304a, a second metal layer 304b, and one or more intermediate metal layers 304c. For example, the printed circuit board 302 is depicted as comprising four metal layers 304, each separated from the dielectric layer, but this is not intended to be limiting. For the example depicted with four metal layers, the first metal layer 304a may be referred to as metal layer 1 (M1) and the second metal layer 304b may be referred to as metal layer 4 (M4), wherein the intermediate metal layers 304c are referred to as metal layers 2 to 3 (M2 to M3). The concept can be extended to PCBs comprising any number (n) of layers (e.g., Mn).

[0054] In an embodiment, a printed circuit board 302 may define one or more of the cavities 308. In this regard, the printed circuit board 302 may be referred to as a cavity PCB. The cavity 308 may be recessed from the second metal layer 304b. As depicted, the cavity 308 is formed on the top surface, but this is not intended to be limiting. An intermediate metal layer 304c may contain a metal layer disposed within the cavity 308. The depth of the cavity 308 may be selected based on the distance to the desired intermediate metal layer. For the depicted example, cavity 308a has a cavity depth of two layers from the metallization layer M4, thereby exposing the metallization layer M2, and cavity 308b has a cavity depth of one layer from the metallization layer M4, thereby exposing the metallization layer M3, but this is not intended to be limiting. Therefore, cavity 118 exposes one or more of the intermediate metal layers 110c.

[0055] In an embodiment, module 300 includes one or more of dies 104. Cavity 308 may be configured to receive die 104. In an embodiment, die 104 may be disposed within cavity 308. Disposing die 104 within cavity 308 reduces the pitch height of die 104 relative to printed circuit board 302 compared to attaching die 104 to the surface of printed circuit board 302. In an embodiment, die 104 may be electrically coupled to an intermediate metal layer via interconnect 120, but this is not intended to be limiting.

[0056] In one embodiment, the printed circuit board 302 includes a shielding structure. The shielding structure reduces or blocks the intensity of EMF transmitted to and from the cavity 308. The shielding structure may include, but is not limited to, vias 306, annular rings 116, and / or metal traces 310. The vias 306, annular rings 116, and / or metal traces 310 may be configured to reduce or block the intensity of EMF transmitted to and from the cavity 308. The vias 306, annular rings 116, and / or metal traces 310 may be internal to the printed circuit board 102.

[0057] Through-hole 306 may be coupled between the first metal layer 304a and the second metal layer 304b (e.g., through the printed circuit board 302, from the top surface to the bottom surface). In an embodiment, through-hole 306 is arranged around the periphery of cavity 308. Through-hole 306 can be considered as forming hole walls at intervals. Through-hole 306 can isolate cavity 308 from the EMF around the sides of printed circuit board 302. Advantageously, through-hole 306 can provide this isolation within printed circuit board 302. In an embodiment, the periphery of cavity 308 is rectangular. In this regard, the periphery of through-hole 306 may also be rectangular when arranged around the periphery of cavity 308.

[0058] In an embodiment, the first metal layer 304a may include metal traces 310. The metal traces 310 of the first metal layer 304a may serve as an EMF shield for the bottom of the printed circuit board 302. The metal traces 310 may couple each of the vias 306 to an adjacent via. The metal traces 310 may then provide EMF shielding. In an embodiment, the metal traces 310 are coupled to the vias 306 according to a grid pattern. The grid pattern of the metal traces 310 may be around and / or within the periphery of the vias 306 (e.g., see...). Figure 1A , Figure 2A In this embodiment, the metal trace 310 has a rectangular grid pattern, wherein the periphery of the cavity 308 and the periphery of the via 306 are rectangular. Therefore, the metal trace 310 can provide EMF shielding for the bottom of the printed circuit board 302.

[0059] In an embodiment, one or more of the vias 114 of the printed circuit board 102 may be coupled to one or more of the vias 306 of the printed circuit board 302. For example, the vias 114 may be coupled to the vias 306 via the second metal layer 110b, the interconnect 108, and the second metal layer 304b.

[0060] In one embodiment, the metal trace 122 of the printed circuit board 102 may provide EMF shielding for the top of the module 300. In another embodiment, vias 114 and 306 may provide EMF shielding for the sides of the module 300. In yet another embodiment, the metal trace 310 may provide EMF shielding for the bottom of the module 300. Therefore, the printed circuit board 102 need not include the metal trace 124 to provide EMF shielding from the bottom of the module 300. Similarly, the printed circuit board 302 need not include a metal trace in the metal layer 304b for EMF shielding of the top of the module 300.

[0061] As depicted, module 300 includes four dies 104 (e.g., die 104a, die 104b, die 104c, die 104d), but this is not intended to be limiting. Die 104a may be electrically coupled to printed circuit board 102 within cavity 118a and to printed circuit board 302 within cavity 308a. Die 104b may be partially disposed within cavity 118a and electrically coupled to a second metal layer 304b (e.g., the top surface of printed circuit board 302). Die 104c may be received within cavity 118b and electrically coupled to printed circuit board 302 within cavity 308b (e.g., intermediate metal layer 304c or M3). Die 104d may be electrically coupled to printed circuit board 102 within cavity 118c (e.g., intermediate metal layer 304c or M4). Printed circuit board 102 and printed circuit board 302 may both be included in or coupled to one or more of the bare die 104.

[0062] In one embodiment, dies 104a, 104b, and 104c are placed on and coupled to printed circuit board 302. In another embodiment, die 104d is placed on and coupled to printed circuit board 102. Printed circuit board 102 may then be flipped and stacked on printed circuit board 302. The printed circuit boards may then be soldered or assembled together. Die 104 may then be packaged to provide EMF shielding.

[0063] Generally speaking, refer to again Figures 1A to 3 .

[0064] As used herein, directional terms such as “top,” “bottom,” “above,” “below,” “up,” “down,” “under,” and “downward” are intended to provide relative positions for descriptive purposes and are not intended to specify an absolute frame of reference. Those skilled in the art will appreciate various modifications to the described embodiments, and that the general principles defined herein may be applied to other embodiments.

[0065] It should be understood that the specific order or hierarchy of steps in the disclosed methods, operations, and / or functions are examples of exemplary methods. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the methods, operations, and / or functions may be rearranged while remaining within the scope of the inventive concepts disclosed herein. The accompanying drawings may present elements of various steps in an exemplary order and are not necessarily intended to limit the specific order or hierarchy presented. It should be understood that embodiments of the methods according to the inventive concepts disclosed herein may include one or more of the steps described herein. Furthermore, such steps may be performed in any desired order, and two or more of the steps may be performed simultaneously with each other. Two or more of the steps disclosed herein may be combined in a single step, and in some embodiments, one or more of the steps may be performed as two or more sub-steps. Furthermore, other steps or sub-steps may be performed as supplements to or alternatives to one or more of the steps disclosed herein.

[0066] As is clear from the above description, the inventive concepts disclosed herein are well-suited to achieving the objectives and obtaining the inherent advantages of the inventive concepts mentioned and disclosed herein. While presently preferred embodiments of the inventive concepts disclosed herein have been described for the purposes of this disclosure, it should be understood that numerous modifications may be made that will readily conceive of those skilled in the art and will be implemented within the broad scope and coverage of the inventive concepts disclosed and claimed herein.

Claims

1. A printed circuit board, comprising: Multiple metal layers, the multiple metal layers including a first metal layer, a second metal layer and one or more intermediate metal layers, wherein the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer, wherein the first metal layer includes metal traces; One or more dielectric layers, wherein the one or more dielectric layers include a first dielectric layer disposed between the first metal layer and the one or more intermediate metal layers, wherein the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and the second metal layer, wherein the first cavity is defined in the second metal layer; and A plurality of vias are coupled between the first metal layer and the second metal layer, wherein the plurality of vias are arranged around the periphery of the first cavity, wherein metal traces couple the plurality of vias, wherein each of the plurality of metal layers includes a plurality of annular rings, wherein each of the plurality of vias is coupled to one of the plurality of annular rings in each of the plurality of metal layers.

2. The printed circuit board according to claim 1, wherein the metal traces are coupled to the plurality of through holes according to a grid pattern.

3. The printed circuit board according to claim 2, wherein the periphery of the first cavity is rectangular, and wherein the plurality of through holes are arranged around the periphery of the first cavity in a rectangular pattern.

4. The printed circuit board of claim 3, wherein the second metal layer includes additional metal traces, wherein the additional metal traces are coupled to the plurality of vias according to the grid pattern.

5. The printed circuit board of claim 3, wherein the distance between adjacent vias of the plurality of vias arranged according to the rectangular pattern is between 20 mils and 50 mils.

6. The printed circuit board of claim 1, wherein the metal traces and the plurality of vias are configured to reduce the intensity of the electromagnetic field transmitted to and from the first cavity.

7. The printed circuit board of claim 1, wherein one or more additional cavities are defined in the second metal layer, wherein the plurality of vias are arranged around the periphery of the one or more additional cavities, wherein the metal traces and the plurality of vias are configured to reduce the intensity of the electromagnetic field transmitted between the first cavity and the one or more additional cavities.

8. The printed circuit board of claim 1, wherein the one or more intermediate metal layers include metal layers disposed in the first cavity, wherein the metal layers disposed in the first cavity include one or more interconnects.

9. The printed circuit board of claim 1, further comprising one or more interconnects, wherein the one or more interconnects are disposed beneath the second metal layer, wherein the plurality of vias are coupled to the one or more interconnects to ground the metal traces and the plurality of vias to the one or more interconnects.

10. The printed circuit board of claim 9, wherein the one or more interconnects comprise at least one of bumps, pads, or solder balls.

11. An apparatus comprising: Printed circuit boards, comprising: Multiple metal layers, the multiple metal layers including a first metal layer, a second metal layer and one or more intermediate metal layers, wherein the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer, wherein the first metal layer includes metal traces; One or more dielectric layers, wherein the one or more dielectric layers include a first dielectric layer disposed between a first metal layer and the one or more intermediate metal layers, wherein the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and a second metal layer, wherein a first cavity is defined in the second metal layer, wherein the one or more intermediate metal layers include a metal layer disposed in the first cavity; and A plurality of vias, wherein the plurality of vias are coupled between the first metal layer and the second metal layer, wherein the plurality of vias are arranged around the periphery of the first cavity, wherein metal traces couple the plurality of vias; and A bare die, wherein the bare die is coupled to the metal layer disposed in the first cavity, wherein the metal traces are coupled to the plurality of vias according to a grid pattern, wherein the periphery of the first cavity is rectangular, wherein the plurality of vias are arranged around the cavity according to a rectangular pattern, and wherein the distance between adjacent vias arranged according to the rectangular pattern is between 20 mils and 50 mils.

12. The apparatus of claim 11, wherein the printed circuit board is a first printed circuit board, the apparatus comprising: A second printed circuit board, the second printed circuit board including a plurality of additional vias, wherein the second metal layer of the first printed circuit board is coupled to the second printed circuit board, wherein the plurality of vias are coupled to the plurality of additional vias.

13. The device of claim 12, wherein the second printed circuit board comprises a plurality of metal layers, the plurality of metal layers of the second printed circuit board comprising a first metal layer, a second metal layer and one or more intermediate metal layers, wherein the second metal layer of the first printed circuit board is coupled to the second metal layer of the second printed circuit board.

14. The device of claim 13, wherein the second metal layer defines an additional cavity, wherein the plurality of additional vias are arranged around the periphery of the additional cavity.

15. The device of claim 14, wherein the die is electrically coupled to the first printed circuit board within the first cavity and electrically coupled to the second printed circuit board within the additional cavity.

16. The device of claim 14, further comprising an additional die, wherein the additional die is partially disposed within the first cavity and electrically coupled to the second metal layer of the second printed circuit board.

17. An apparatus comprising: Printed circuit boards, comprising: Multiple metal layers, the multiple metal layers including a first metal layer, a second metal layer and one or more intermediate metal layers, wherein the one or more intermediate metal layers are disposed between the first metal layer and the second metal layer, wherein the first metal layer includes metal traces; One or more dielectric layers, wherein the one or more dielectric layers include a first dielectric layer disposed between a first metal layer and the one or more intermediate metal layers, wherein the one or more dielectric layers include a second dielectric layer disposed between the one or more intermediate metal layers and a second metal layer, wherein a first cavity is defined in the second metal layer, wherein the one or more intermediate metal layers include a metal layer disposed in the first cavity; and A plurality of vias are coupled between a first metal layer and a second metal layer. The plurality of vias are arranged in a rectangular pattern around the periphery of a first cavity, wherein the periphery of the first cavity is rectangular. The plurality of vias are coupled in a grid pattern, wherein the grid pattern includes a first portion of the metal traces arranged outside the rectangular pattern and a second portion of the metal traces arranged inside the rectangular pattern. Each of the plurality of metal layers includes a plurality of annular rings, and each of the plurality of vias is coupled to one of the plurality of annular rings in each of the plurality of metal layers.

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