A phase-locked loop circuit with anti-interference function and corresponding electronic equipment

Abstract

The present invention discloses a phase-locked loop circuit with anti-interference function and corresponding electronic equipment. The phase-locked loop circuit includes a frequency detector, a charge pump, a low-pass filter, a frequency divider and a voltage-controlled oscillator; the voltage-controlled oscillator includes a first NMOS tube, a first PMOS tube, a second PMOS tube, a frequency generation unit, a frequency change rate compensation unit and a calibration logic unit. Among them, the calibration logic unit generates a calibration control signal after comparing the control voltage with the reference voltage, and provides it to the frequency change rate compensation unit; the frequency change rate compensation unit generates a corresponding compensation current according to the calibration control signal, and provides it to the frequency generation unit. When the control voltage is less than the reference voltage, the calibration control signal output by the calibration logic unit changes, and controls the size of the compensation current output by the frequency change rate compensation unit, so that the control voltage finally reaches a value greater than or equal to the reference voltage, thereby improving the anti-interference ability of the phase-locked loop circuit.

Description

Technical Field

[0001] The invention relates to a phase-locked loop circuit with anti-interference function, and also to an electronic device comprising the phase-locked loop, belonging to the technical field of integrated circuits. Background Art

[0002] Phase-locked loop (PLL) is a technology that uses feedback control principle to achieve frequency and phase synchronization. Its function is to synchronize the clock signal output by the circuit with its external reference clock signal. With the continuous development of integrated circuit technology, the quality requirements for clock frequency signals are getting higher and higher. Therefore, phase-locked loop circuits are widely used in many technical fields such as wireless communication and frequency synthesis.

[0003] In the prior art, Figure 1 As shown in the figure, a typical phase-locked loop circuit mainly includes a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (DIV). Among them, the phase frequency detector is used to compare the clock signal output by the VCO and divided by the frequency divider with the reference clock signal (Fref), and use the frequency difference and phase difference between the two to generate a control signal, and the charge pump controls the low-pass filter to generate a control voltage, and controls the frequency of the VCO output clock signal so that it can automatically keep synchronization with the frequency of the reference clock signal at any time; among them, the voltage-controlled oscillator is the core functional module in the phase-locked loop circuit.

[0004] like Figure 2 As shown, a typical voltage-controlled oscillator circuit mainly includes an NMOS tube NM0, a PMOS tube PM0, a PMOS tube PM1 and a frequency generation unit (vco_core). When the control voltage Vc increases or decreases, the current I0 flowing through the NMOS tube NM0 and the PMOS tube PM0 and the current I1 flowing through the PMOS tube PM1 increase or decrease accordingly, and further, the frequency of the clock signal output by the frequency generation unit increases or decreases accordingly. When the interference signal on the ground line is relatively large and the control voltage Vc is relatively small, the interference signal causes the current detal I generated by the NMOS tube NM0 to be relatively large relative to the current I0 when there is no disturbance, and the NMOS tube NM0 is easily in a subthreshold or even off state, resulting in the voltage-controlled oscillator circuit being unable to output a frequency signal. Therefore, the disturbance on the ground line will cause the PLL to lose lock. When the interference signal on the ground line is relatively large and the control voltage Vc is also relatively large, the interference signal causes the current detal I generated by the NMOS tube NM0 to be relatively small relative to the current I0 when there is no disturbance. At this time, the disturbance on the ground line will not easily cause the PLL to lose lock.

[0005] In the PCT international patent with patent number ZL 201080017266.7, a phase-locked loop PLL with supply regulation and a method of use are disclosed. The phase-locked loop includes a supply regulation loop, a voltage-controlled oscillator VCO, and a programmable decoupling capacitor array for the VCO. The capacitance of the decoupling capacitor array of the VCO can be adjusted to be equal to N times C UNIT , where N is the current value of the multiplication factor divided by N circuit, and C UNIT The unit capacitance is specific to the process technology selected for manufacturing the decoupling capacitor array. When the PLL switches from one frequency band to another, the higher order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operating stability. Summary of the invention

[0006] The primary technical problem to be solved by the present invention is to provide a phase-locked loop circuit with anti-interference function.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the phase-locked loop circuit.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a phase-locked loop circuit with an anti-interference function is provided, comprising a frequency detector, a charge pump, a low-pass filter, a frequency divider and a voltage-controlled oscillator; the voltage-controlled oscillator comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a frequency generation unit, a frequency change rate compensation unit and a calibration logic unit; wherein,

[0010] The first NMOS tube, the first PMOS tube and the second PMOS tube form a current mirror structure, which is used to convert the input control voltage into a current signal and copy it to the branch where the second PMOS tube is located, and then provide it to the frequency generating unit;

[0011] The calibration logic unit is used to generate a calibration control signal after comparing the input control voltage with a reference voltage, and provide the calibration control signal to the frequency change rate compensation unit;

[0012] The frequency change rate compensation unit is used to generate a corresponding compensation current according to the input calibration control signal, and provide the compensation current to the frequency generation unit;

[0013] The frequency generating unit is used to generate and output a clock signal of corresponding frequency according to the input current;

[0014] When the control voltage is less than the reference voltage, the calibration control signal output by the calibration logic unit changes, controlling the magnitude of the compensation current output by the frequency change rate compensation unit so that the control voltage eventually reaches a value greater than or equal to the reference voltage, thereby improving the anti-interference capability of the phase-locked loop circuit.

[0015] Preferably, the gate terminal of the first NMOS tube is connected to the control voltage terminal, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the drain terminal of the first PMOS tube; the drain terminal and the gate terminal of the first PMOS tube are short-circuited and then connected to the gate terminal of the second PMOS tube on the one hand, and to the first input terminal of the frequency change rate compensation unit on the other hand; the source terminal of the first PMOS tube and the source terminal of the second PMOS tube are both connected to the power supply terminal; the drain terminal of the second PMOS tube and the output terminal of the frequency change rate compensation unit are commonly connected to the input terminal of the frequency generation unit; the first input terminal of the calibration logic unit is connected to the reference voltage terminal, the second input terminal is connected to the control voltage terminal, and the output terminal is connected to the second input terminal of the frequency change rate compensation unit.

[0016] Preferably, the calibration logic unit includes a comparator and a logic module; wherein,

[0017] The first input terminal of the comparator is connected to the reference voltage terminal, the second input terminal is connected to the control voltage terminal, the output terminal is connected to the input terminal of the logic module, and the output terminal of the logic module is connected to the output terminal of the calibration logic unit.

[0018] Preferably, when the control voltage is less than the reference voltage, the comparator outputs a digital signal 1 to the logic module, and after logic operation, the calibration control signal Sel is output. <n:0>The low bit of is added by 1; where n is a positive integer.

[0019] Preferably, when the control voltage is greater than or equal to the reference voltage, the comparator outputs a digital signal 0 to the logic module, and after logic operation, the calibration control signal Sel is output. <n:0>Remain unchanged; where n is a positive integer.

[0020] Preferably, the frequency change rate compensation unit is composed of n+1 current branches connected in parallel; each current branch is composed of a PMOS tube and a switch tube connected in series; wherein,

[0021] The drain end of the PMOS tube is connected to one end of the switch tube, the source end of the PMOS tube is connected to the power supply end, the gate end of the PMOS tube serves as the first input end, the control end of the switch tube serves as the second input end, and the other end of the switch tube serves as the output end;

[0022] The first input ends of the n+1 current branches are connected in parallel to the gate end of the second PMOS tube; the output ends of the n+1 current branches are connected in parallel to the drain end of the second PMOS tube; the second input ends of the n+1 current branches are connected in sequence to the calibration control signal Sel output by the calibration logic unit. <n:0>The digital signal ends from low to high are connected correspondingly; wherein n is a positive integer.

[0023] Preferably, the weight ratio relationship of the compensation currents output by the n+1 current branches is a ratio relationship that increases successively in order from the low position to the high position of the branch control signal, ie, the calibration control signal.

[0024] Preferably, the weight ratio relationship of the n+1 current branches outputting the compensation currents is set to increase in sequence according to the exponential order of 2 in the order from the low position to the high position of the branch control signal, ie, the calibration control signal.

[0025] Preferably, the calibration control signal Sel <n:0>The initial default value of is that all the low bits to the high bits are 0. At this time, the switch tubes of the n+1 current branches in the frequency change rate compensation unit are all turned on, and the n+1 current branches all output compensation currents.

[0026] According to a second aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned phase-locked loop circuit with anti-interference function.

[0027] Compared with the prior art, the phase-locked loop circuit with anti-interference function provided by the present invention adopts a calibration logic unit to generate a calibration control signal, and controls the technical solution of the magnitude of the compensation current output by the frequency change rate compensation unit, so that when the voltage-controlled oscillator outputs a clock signal with a lower frequency, the input control voltage is increased to above the reference voltage, and the influence of the disturbance existing on the ground line on the phase-locked loop circuit is effectively avoided. Therefore, the phase-locked loop circuit with anti-interference function provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, strong anti-interference ability and excellent circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a typical phase-locked loop circuit in the prior art;

[0029] Figure 2 It is a schematic diagram of the structure of a typical voltage-controlled oscillator circuit in the prior art;

[0030] Figure 3 A circuit schematic diagram of a voltage-controlled oscillator in a PLL circuit in an embodiment of the present invention;

[0031] Figure 4 The present invention is a schematic diagram of an electronic device using the phase-locked loop circuit with anti-interference function provided by the present invention. DETAILED DESCRIPTION

[0032] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] The embodiment of the present invention provides a phase-locked loop circuit with anti-interference function, including a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a frequency divider (DIV). The phase frequency detector is used to compare the clock signal output by the VCO and divided by the frequency divider with the reference clock signal, and use the frequency difference and phase difference between the two to generate a control signal, and control the low-pass filter to generate a control voltage Vc through the charge pump, thereby controlling the frequency of the VCO output clock signal so that it can automatically keep synchronization with the frequency of the reference clock signal at any time.

[0034] like Figure 3 As shown, in one embodiment of the present invention, the voltage controlled oscillator circuit includes a first NMOS transistor NM0, a first PMOS transistor PM0, a second PMOS transistor PM1, a frequency generation unit (VCO core), a frequency change rate compensation unit (Kvcocurrent) and a calibration logic unit (Cal logic). Among them, the gate end of the first NMOS transistor NM0 is connected to the control voltage Vc end, the source end is connected to the ground potential end, and the drain end is connected to the drain end of the first PMOS transistor PM0; the drain end and the gate end of the first PMOS transistor PM0 are short-circuited and connected to the gate end of the second PMOS transistor PM1 on one hand, and connected to the first input end of the frequency change rate compensation unit on the other hand; the source end of the first PMOS transistor PM0 and the source end of the second PMOS transistor PM1 are both connected to the power supply Vdd end; the drain end of the second PMOS transistor PM1 and the output end of the frequency change rate compensation unit are commonly connected to the input end of the frequency generation unit; the first input end of the calibration logic unit is connected to the reference voltage Vref end, the second input end is connected to the control voltage Vc end, and the output end is connected to the second input end of the frequency change rate compensation unit.

[0035] Among them, the reference voltage Vref is a settable reference voltage, and its size can be set and adjusted; the control voltage Vc is the output voltage of the low-pass filter in the phase-locked loop circuit. When the control voltage Vc is small, the frequency of the VCO output clock signal is relatively low; when the control voltage Vc is large, the frequency of the VCO output clock signal is relatively high.

[0036] The first NMOS transistor NM0, the first PMOS transistor PM0 and the second PMOS transistor PM1 form a current mirror structure for converting the control voltage Vc into a current signal and copying it to the branch where the second PMOS transistor PM1 is located, and then providing it to the frequency generating unit.

[0037] The calibration logic unit is used to generate a calibration control signal after comparing the input control voltage Vc with the reference voltage Vref, and provide the calibration control signal to the frequency change rate compensation unit.

[0038] The frequency change rate compensation unit is used to generate a corresponding compensation current according to an input calibration control signal, and provide the compensation current to the frequency generation unit.

[0039] The frequency generating unit is used to generate and output a clock signal of a corresponding frequency according to the input current.

[0040] When the control voltage is less than the reference voltage, the calibration logic unit outputs a calibration control signal Sel <n:0>The frequency change rate compensation unit controls the magnitude of the compensation current output by the frequency change rate compensation unit, so that the control voltage eventually reaches a value greater than or equal to the reference voltage, thereby improving the anti-interference ability of the phase-locked loop circuit.

[0041] In one embodiment of the present invention, the calibration logic unit includes a comparator comp and a logic module logic, wherein the first input terminal of the comparator comp is connected to the reference voltage Vref terminal, the second input terminal is connected to the control voltage Vc terminal, the output terminal is connected to the input terminal of the logic module logic, and the output terminal of the logic module logic is connected to the output terminal of the calibration logic unit.

[0042] The calibration control signal output by the calibration logic unit is the n+1bit control word Sel <n:0>, where n is a positive integer. Control word Sel <n:0>Each bit of the digital signal (Sel <0> 、Sel <1> 、Sel <2> ……Sel <n>) are used to individually control the on / off of a current branch in the frequency change rate compensation unit. <n:0>The initial default value is that the digital signal of each bit is zero, that is, Sel <n:0>=00……00. When the control voltage Vc input to the calibration logic unit is less than the reference voltage Vref, the comparator comp outputs a digital signal 1 to the logic module logic, and the control signal Sel is calibrated after logic operation. <n:0>The low bit is increased by 1. For example, the first low bit is increased by 1 to become Sel <n:0>=00...01; the second low bit is increased by 1 to become Sel <n:0>=00……10. When the control voltage Vc input to the calibration logic unit is greater than or equal to the reference voltage Vref, the comparator comp outputs a digital signal 0 to the logic module logic, and the control signal Sel is calibrated after the logic operation. <n:0>Keep the original state unchanged. The calibration logic unit controls the word Sel <n:0>The frequency change rate compensation unit generates a compensation current by controlling the frequency change rate compensation unit.

[0043] In one embodiment of the present invention, the frequency change rate compensation unit is composed of n+1 current branches connected in parallel; each current branch is composed of a PMOS tube and a switch tube connected in series. Among them, the drain end of the PMOS tube is connected to one end of the switch tube, the source end of the PMOS tube is connected to the power supply Vdd end, the gate end of the PMOS tube serves as the first input end, the control end of the switch tube serves as the second input end, and the other end of the switch tube serves as the output end. Further, the first input ends of the n+1 current branches are connected in parallel to the gate end of the second PMOS tube PM1; the output ends of the n+1 current branches are connected in parallel to the drain end of the second PMOS tube PM1; the second input ends of the n+1 current branches are respectively connected in sequence to the calibration control signal Sel output by the calibration logic unit. <n:0>The digital signal ends of a bit from low to high are connected accordingly.

[0044] For example, the first current branch is composed of a third PMOS transistor PM2 and a first switch transistor SW0; wherein the source end of the third PMOS transistor PM2 is connected to the power supply Vdd end, the gate end is connected to the gate end of the second PMOS transistor PM1 as a first input end, and the drain end is connected to the first switch transistor SW0; the other end of the first switch transistor SW0 is connected to the drain end of the second PMOS transistor PM1 as an output end, and the control end of the first switch transistor SW0 is connected to the calibration control signal Sel output by the calibration logic unit as a second input end. <n:0>The first low-order digital signal Sel <0> End connection.

[0045] The main working purpose of the calibration logic unit and the frequency change rate compensation unit is to increase the control voltage Vc to above or equal to the reference voltage Vref when the VCO circuit outputs clock signals of different frequencies, so as to ensure that when there is a large interference signal on the ground line, the PLL circuit will not be locked and unable to output the clock signal. The specific working principle of the voltage controlled oscillator circuit is described in detail below.

[0046] The calibration control signal Sel output by the calibration logic unit <n:0>The initial default value is Sel <n:0>=00……00, that is, n+1 bits are all 0. At this time, the second input terminals of all current branches in the frequency change rate compensation unit are low-level signals 0, so that the switch tubes of all current branches are turned on, and all current branches have compensation current output. The compensation current of each branch is copied by the current mirror structure according to the weight ratio of each branch. The frequency generation unit generates and outputs a clock signal of the corresponding frequency according to the sum of the drain current I1 of the second PMOS tube PM1 and the total compensation current.

[0047] It should be noted that, usually, the weight ratio relationship of the compensation current output by the n+1 current branches is a sequentially increasing ratio relationship according to the order from the low bit to the high bit of the branch control signal, i.e., the calibration control signal. In this embodiment, the weight ratio relationship of the compensation current output by the n+1 current branches is sequentially increased according to the order from the low bit to the high bit of the branch control signal, i.e., the calibration control signal, according to the exponential level of 2. Specifically, the weight ratio relationship of the corresponding current branches controlled by the low bit digital signal to the high bit digital signal of the calibration control signal is 1:2:4:8:16...2 n For example, assuming that the control signal Sel <0> The compensation current output by the first current branch controlled is I11, then the control signal Sel <1> The compensation current output by the second current branch controlled is 2I11, and the control signal Sel <2> The compensation current output by the controlled third current branch is 4I11, and the same applies to other branches.

[0048] In the frequency change rate compensation unit, since all current branches are fully turned on, the input current of the frequency generation unit (I1+I11+2I11+4I11+……+2 n I11) is relatively large, and the frequency of its output clock signal increases accordingly. Therefore, the phase-locked loop circuit automatically adjusts the clock signal after the clock signal is divided and the reference clock signal to reduce the control voltage Vc, thereby maintaining the original locked frequency value.

[0049] When the control voltage Vc is less than the reference voltage Vref, the comparator comp in the calibration logic unit outputs a digital signal 1 to the logic module logic, and the control signal Sel is calibrated after logical operation. <n:0>The low bit of the calibration control signal becomes Sel <n:0>=00...01, and is provided to the frequency change rate compensation unit. In the frequency change rate compensation unit, the second input end of the first current branch receives the control signal Sel <0> =1, the first switch tube SW0 is turned off, the first current branch is disconnected and no current is output, therefore, the total compensation current output by the frequency change rate compensation unit is reduced by I11, and the frequency generation unit generates and outputs a clock signal of a corresponding frequency according to the sum of the drain current I1 of the second PMOS tube PM1 and the reduced total compensation current, and the frequency of the clock signal is reduced compared with the previous one. The phase-locked loop circuit continues to automatically adjust the magnitude of the control voltage Vc.

[0050] When the control voltage Vc is still less than the reference voltage Vref, the comparator comp in the calibration logic unit outputs a digital signal 1 to the logic module logic for the second time, and the control signal Sel is calibrated after the logic operation. <n:0>The low bit of the calibration control signal becomes Sel <n:0>=00...10, and is provided to the frequency change rate compensation unit. In the frequency change rate compensation unit, the second input end of the first current branch receives the control signal Sel <0> =0, the first switch tube SW0 is turned on, the first current branch starts to output the compensation current I11; the second input end of the second current branch receives the control signal Sel <1> =1, the second switch tube SW1 is turned off, the second current branch is disconnected and no current is output; therefore, the total compensation current output by the frequency change rate compensation unit is reduced by 2I11, and the frequency generation unit generates and outputs a clock signal of a corresponding frequency according to the sum of the drain current I1 of the second PMOS tube PM1 and the reduced total compensation current, and the frequency of the clock signal is reduced compared with the previous one. The phase-locked loop circuit continues to automatically adjust the size of the control voltage Vc.

[0051] By analogy, the calibration logic unit cyclically compares the control voltage Vc and the reference voltage Vref. When the control voltage Vc is less than the reference voltage Vref, the calibration control signal Sel is gradually changed. <n:0>, and then control the magnitude of the compensation current output by the frequency change rate compensation unit. When the control voltage Vc is greater than or equal to the reference voltage Vref, the comparator comp outputs a digital signal 0 to the logic module logic, and the control signal Sel is calibrated after logical operation. <n:0>Therefore, the calibration logic unit and the frequency change rate compensation unit cooperate to increase the control voltage Vc to above or equal to the reference voltage Vref when the VCO circuit outputs clock signals of different frequencies, so that the voltage difference between the control voltage Vc and the ground line is relatively large, thereby avoiding the influence of the disturbance on the ground line on the output of the VCO.

[0052] For example, see Attachment Figure 2 In the voltage-controlled oscillator circuit of the prior art, if the VCO output frequency is relatively low at 315 MHz, the control voltage Vc is 450 mv; the threshold voltage Vth of the NMOS tube NM0 is 400 mv, then the gate-source voltage Vgs of the NMOS tube NM0 is Vc-0=450 mv, where 0 mv is the potential on the ground line.

[0053] If there is no interference signal on the ground line, since Vgs>Vth, the NMOS tube NM0 can be effectively turned on and provide current, so that the frequency generation unit (vco_core) outputs a clock signal of a certain frequency. When there is an interference signal on the ground line, and the amplitude of the interference signal is greater than 50mv, making Vgs≤Vth, the NMOS tube NM0 is likely to be in a subthreshold or even off state, and cannot be effectively turned on, resulting in the frequency generation unit being unable to reliably output a clock signal.

[0054] Reference Figure 3 In the voltage-controlled oscillator circuit provided by the embodiment of the present invention, since a calibration logic unit and a frequency change rate compensation unit are provided, when the VCO output frequency is relatively low at 315MHz, the reference voltage Vref is set at 650mv, and the magnitude of the reference voltage Vref can be adjusted. In the VCO circuit, the control voltage Vc can eventually be greater than or equal to the reference voltage Vref through the automatic control adjustment of the calibration logic unit and the frequency change rate compensation unit, that is, the control voltage Vc is not less than 650mv. When there is an interference signal on the ground line, as long as the interference signal is less than 250mv, so that Vgs>400mv (650mv-250mv), that is, Vgs>Vth, the NMOS tube NM0 can be effectively turned on and provide current, so that the frequency generation unit can normally output a clock signal of a certain frequency. Therefore, the phase-locked loop circuit has anti-interference ability, ensuring that the interference signal on the ground line will not cause a loss of lock. Furthermore, when the interference signal on the ground line is greater than 250mv, the control voltage Vc can be increased by increasing the setting value of the reference voltage Vref, thereby further improving the anti-interference capability of the phase-locked loop circuit.

[0055] In summary, the voltage-controlled oscillator circuit provided in the embodiment of the present invention is provided with a calibration logic unit and a frequency change rate compensation unit, which outputs a lower frequency clock signal for the VCO, and when the control voltage Vc in the circuit is less than the reference voltage Vref, the calibration control signal Sel output by the calibration logic unit is <n:0>The frequency change rate compensation unit controls the magnitude of the compensation current output by the frequency change rate compensation unit, so that the control voltage Vc can eventually be greater than or equal to the reference voltage Vref, thereby improving the anti-interference ability of the PLL circuit. When the VCO outputs a clock signal with a higher frequency and the control voltage Vc in the circuit is greater than or equal to the reference voltage Vref, the calibration control signal Sel output by the calibration logic unit is <n:0>The higher control voltage Vc makes the PLL circuit itself have anti-interference ability.

[0056] The above is a detailed description of the phase-locked loop circuit with anti-interference function provided by the embodiment of the present invention. Based on the above phase-locked loop circuit with anti-interference function, the embodiment of the present invention further provides an electronic device, which includes the above phase-locked loop circuit with anti-interference function, and the phase-locked loop circuit can be used as an important component of the clock circuit to automatically synchronize the frequency of the application circuit clock signal in the electronic device with the frequency of the reference clock signal at any time. The specific structure of the phase-locked loop circuit with anti-interference function in the electronic device will not be described in detail here.

[0057] The electronic devices mentioned here refer to computer devices that can be used in mobile environments and support multiple communication formats, including mobile phones, laptops, tablet computers, car computers, etc., as well as electronic devices in other integrated circuit application scenarios, such as communication base stations, smart connected cars, etc. Figure 4 As shown, the electronic device at least includes a processor, a memory and a clock circuit, and may further include a communication component, a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power component, the multimedia component and the input / output interface are all connected to the processor. The memory may be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. may all be implemented using general components, which will not be specifically described here.

[0058] Compared with the prior art, the phase-locked loop circuit with anti-interference function provided by the present invention adopts a calibration logic unit to generate a calibration control signal, and controls the technical solution of the magnitude of the compensation current output by the frequency change rate compensation unit, so that when the VCO outputs a clock signal with a lower frequency, the input control voltage is increased to above the reference voltage, and the influence of the disturbance existing on the ground line on the phase-locked loop circuit is effectively avoided. Therefore, the phase-locked loop circuit with anti-interference function provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, strong anti-interference ability and excellent circuit performance.

[0059] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0060] The above is a detailed description of the phase-locked loop circuit with anti-interference function and the corresponding electronic equipment provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear the corresponding legal liability. < / n>

Claims

1. A phase-locked loop circuit with anti-interference function, comprising a frequency detector, a charge pump, a low-pass filter, and a frequency divider, characterized in that It includes a voltage-controlled oscillator; the voltage-controlled oscillator includes a first NMOS tube, a first PMOS tube, a second PMOS tube, a frequency generation unit, a frequency change rate compensation unit and a calibration logic unit; wherein, The first NMOS tube, the first PMOS tube and the second PMOS tube form a current mirror structure, which is used to convert the input control voltage into a current signal and copy it to the branch where the second PMOS tube is located, and then provide it to the frequency generating unit; The calibration logic unit is used to generate a calibration control signal after comparing the input control voltage with a reference voltage, and provide the calibration control signal to the frequency change rate compensation unit; wherein the calibration logic unit includes a comparator and a logic module; the first input terminal of the comparator is connected to the reference voltage terminal, the second input terminal is connected to the control voltage terminal, the output terminal is connected to the input terminal of the logic module, and the output terminal of the logic module is connected to the output terminal of the calibration logic unit; The frequency change rate compensation unit is used to generate a corresponding compensation current according to the input calibration control signal, and provide the compensation current to the frequency generation unit; The frequency generating unit is used to generate and output a clock signal of corresponding frequency according to the input current; When the control voltage is less than the reference voltage, the comparator outputs a digital signal 1 to the logic module. After the logic operation, the low bit of the output calibration control signal is increased by 1, and the magnitude of the compensation current output by the frequency change rate compensation unit changes accordingly; when the control voltage is greater than or equal to the reference voltage, the comparator outputs a digital signal 0 to the logic module. After the logic operation, the output calibration control signal remains unchanged.

2. The phase-locked loop circuit with anti-interference function as claimed in claim 1, characterized in that: The gate terminal of the first NMOS tube is connected to the control voltage terminal, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the drain terminal of the first PMOS tube; the drain terminal and the gate terminal of the first PMOS tube are short-circuited and connected to the gate terminal of the second PMOS tube on the one hand, and connected to the first input terminal of the frequency change rate compensation unit on the other hand; the source terminal of the first PMOS tube and the source terminal of the second PMOS tube are both connected to the power supply terminal; the drain terminal of the second PMOS tube and the output terminal of the frequency change rate compensation unit are commonly connected to the input terminal of the frequency generation unit; the first input terminal of the calibration logic unit is connected to the reference voltage terminal, the second input terminal is connected to the control voltage terminal, and the output terminal is connected to the second input terminal of the frequency change rate compensation unit.

3. The phase-locked loop circuit with anti-interference function as claimed in claim 1, characterized in that: The frequency change rate compensation unit is composed of n+1 current branches connected in parallel; each current branch is composed of a PMOS tube and a switch tube connected in series; wherein, The drain end of the PMOS tube is connected to one end of the switch tube, the source end of the PMOS tube is connected to the power supply end, the gate end of the PMOS tube serves as the first input end, the control end of the switch tube serves as the second input end, and the other end of the switch tube serves as the output end; The first input ends of the n+1 current branches are connected in parallel to the gate end of the second PMOS tube; the output ends of the n+1 current branches are connected in parallel to the drain end of the second PMOS tube; the second input ends of the n+1 current branches are respectively connected in sequence to the corresponding digital signal ends of the calibration control signal output by the calibration logic unit from low to high; wherein n is a positive integer.

4. The phase-locked loop circuit with anti-interference function as claimed in claim 3, characterized in that: The weight ratio relationship of the compensation current output by the n+1 current branches is a ratio relationship that increases successively according to the order from the low position to the high position of the control signal of the branch, ie, the calibration control signal.

5. The phase-locked loop circuit with anti-interference function as claimed in claim 4, characterized in that: The weight ratio relationship of the n+1 current branches outputting the compensation current is set to increase in sequence according to the exponential of 2 in the order from the low position to the high position of the branch control signal, ie, the calibration control signal.

6. The phase-locked loop circuit with anti-interference function as claimed in claim 3, characterized in that: The initial default value of the calibration control signal is that all the low bits to the high bits are 0. At this time, the switch tubes of the n+1 current branches in the frequency change rate compensation unit are all turned on, and the n+1 current branches all output compensation currents.

7. An electronic device, characterized in that A phase-locked loop circuit with anti-interference function comprising any one of claims 1 to 6.

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