Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate; a vertical stack structure comprising a channel region and source-drain regions on both sides of the channel region, the channel region comprising a first stack region, an isolation region and a second stack region on the substrate, the first stack region comprising a plurality of first channel layers, the second stack region comprising a plurality of second channel layers; a first isolation layer in the isolation region; a gate structure surrounding the first channel layers and the second channel layers on the substrate; a first source-drain doped region in the source-drain regions on both sides of the first stack region; a first contact layer on a surface of the first source-drain doped region having a first projection on a surface of the substrate; a second source-drain doped region on the first contact layer; a second contact layer on a surface of the second source-drain doped region having a second projection on the surface of the substrate, an area of the first projection being greater than or equal to an area of the second projection; a second connection layer on both sides of the gate structure; and a first connection layer in the second source-drain doped region. The semiconductor structure has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the channel current control capability of traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) has weakened, resulting in severe leakage current. FinFETs are a new type of multi-gate device that typically includes fins protruding from the semiconductor substrate surface, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure. Compared to planar MOSFETs, FETs have stronger short-channel rejection capability and higher operating current.

[0003] With the further development of semiconductor technology, the size of integrated circuit devices is becoming smaller and smaller, and traditional fin field-effect transistors (FETs) face limitations in further increasing their operating current. Specifically, since only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the channel region within the fin is small, which limits the increase in the operating current of the FET. Therefore, a gate-all-around (GAA) FET structure has been proposed, which increases the volume of the channel region and further increases the operating current of the GAA FET.

[0004] However, the performance of fin field-effect transistors with channel gate surround structure in the prior art needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the channel gate surround structure fin field-effect transistor.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a vertically stacked structure on the substrate, the vertically stacked structure including a channel region and source / drain regions located on both sides of the channel region, the arrangement direction of the channel region and the source / drain regions being perpendicular to the extension direction of the vertically stacked structure, the channel region including a first stacked region on the substrate, an isolation region on the first stacked region, and a second stacked region on the isolation region, the first stacked region including a plurality of discrete first channel layers, with first grooves between adjacent first channel layers and between the first channel layers and the isolation region, the second stacked region including a plurality of discrete second channel layers, with second grooves between adjacent second channel layers and between the second channel layers and the isolation region; a first isolation layer located within the isolation region; and a gate structure located on the substrate, the gate structure surrounding the first channel layer. The gate structure is further located within the first and second trenches, and includes a second channel layer; a first source / drain doped region located within the source / drain regions on both sides of the first stacked region; a first contact layer located on the surface of the first source / drain doped region, the first contact layer having a first projection on the substrate surface; a second source / drain doped region located on the first contact layer, the second source / drain doped region being located within the source / drain regions on both sides of the second stacked region; a second contact layer located on the surface of the second source / drain doped region, the second contact layer having a second projection on the substrate surface, the area of ​​the first projection being greater than or equal to the area of ​​the second projection; a second connection layer located on both sides of the gate structure, the second connection layer being electrically connected to the second source / drain doped region through the second contact layer; and a first connection layer located within the second source / drain doped region on both sides of the gate structure, the first connection layer being electrically connected to the first source / drain doped region through the first contact layer.

[0007] Optionally, there are multiple vertical stacked structures, which are arranged parallel to a first direction and along a second direction. The first and second directions are parallel to the substrate surface, and the first direction is perpendicular to the second direction. The gate structure spans a plurality of the channel regions and is parallel to the second direction.

[0008] Optionally, it may also include a second isolation layer located between the first contact layer and the second source / drain doped region, wherein the top surface of the second isolation layer is lower than or flush with the top surface of the first isolation layer.

[0009] Optionally, it may also include: a first insulating layer located on the sidewall surface of the first connecting layer, and a second insulating layer located on the sidewall surface of the second connecting layer.

[0010] Optionally, the central axis of the first interconnecting layer located on the same side of the gate structure, parallel to the extension direction of the gate structure, coincides with the central axis of the second interconnecting layer, which is also parallel to the extension direction of the gate structure.

[0011] Optionally, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction, and the second connection layer located on both sides of the gate structure coincides with the central axis of the first direction; or, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction and the second connection layer coincides with the central axis of the first direction.

[0012] Optionally, it further includes: a first sidewall located on the sidewall of the gate structure within the first recess, the first sidewall being located between adjacent first channel layers and between the first channel layer and the first isolation layer, and the first sidewall being flush with the sidewall of the first channel layer; and a second sidewall located on the sidewall of the gate structure within the second recess, the second sidewall being located between adjacent second channel layers and between the second channel layer and the first isolation layer, and the second sidewall being flush with the sidewall of the second channel layer.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a vertically stacked structure on the substrate, the vertically stacked structure including a channel region and source / drain regions located on both sides of the channel region, the arrangement direction of the channel region and the source / drain regions being perpendicular to the extension direction of the vertically stacked structure, the channel region including a first stacked region on the substrate, an isolation region on the first stacked region, and a second stacked region on the isolation region, the first stacked region including a plurality of discrete first channel layers, a first groove being formed between adjacent first channel layers and between the first channel layer and the isolation region, the second stacked region including a plurality of discrete second channel layers, a second groove being formed between adjacent second channel layers and between the second channel layer and the isolation region; forming a first isolation layer within the isolation region; and forming a gate structure on the substrate, the gate structure surrounding the first channel layer and the first isolation layer. The dual-channel layer includes a gate structure located within the first and second trenches; first source / drain doped regions formed within the source / drain regions on both sides of the first stacked region; a first contact layer formed on the surface of the first source / drain doped region, the first contact layer having a first projection on the substrate surface; a second source / drain doped region formed on the first contact layer, the second source / drain doped region located within the source / drain regions on both sides of the second stacked region; a second contact layer formed on part or all of the surface of the second source / drain doped region, the second contact layer having a second projection on the substrate surface, the area of ​​the first projection being greater than or equal to the area of ​​the second projection; a first connection layer formed within the second source / drain doped regions on both sides of the gate structure, the first connection layer being electrically connected to the first source / drain doped region through the first contact layer; and a second connection layer formed on both sides of the gate structure, the second connection layer being electrically connected to the second source / drain doped region through the second contact layer.

[0014] Optionally, the method for forming the vertical stacked structure, the first isolation layer, and the first source / drain doped region includes: forming a first composite material layer on a substrate, the first composite material layer including a plurality of first stacked structures, the first stacked structure including an initial first sacrificial layer and an initial first channel layer located on the initial first sacrificial layer; forming a second composite material layer on the first composite material layer, the second composite material layer including a plurality of second stacked structures, the second stacked structure including an initial second sacrificial layer and an initial second channel layer located on the initial second sacrificial layer; forming a dummy gate structure on the substrate, the dummy gate structure spanning the first composite material layer and the second composite material layer; removing portions of the second composite material layer on both sides of the dummy gate structure until the surface of the first composite material layer is exposed, and forming a second composite material layer on the substrate. A first opening is formed within the material layer, causing the initial second sacrificial layer to become a second sacrificial layer and the initial second channel layer to become a second channel layer, forming the second stacked region; the portion of the initial first channel layer exposed by the first opening is removed, and a second opening is formed at the bottom of the first opening, the second opening also located at the bottom of the second sacrificial layer, forming the isolation region; a first isolation layer is formed within the second opening at the bottom of the second sacrificial layer; after forming the first isolation layer, the first composite material layer exposed by the second opening is removed until the substrate surface is exposed, a third opening is formed within the first composite material layer, and the initial first sacrificial layer is formed as a first sacrificial layer, causing the initial first channel layer to become a first channel layer, forming the first stacked region; a first source / drain doped region is formed within the third opening.

[0015] Optionally, the method of forming the first contact layer includes: forming a first metal layer on the surface of the first source / drain doped region; and performing heat treatment on the first metal layer to form the first contact layer on the surface of the first source / drain doped region.

[0016] Optionally, before removing the portion of the initial first trench layer exposed by the first opening, the method further includes: forming an initial second sidewall on the sidewall of the second sacrificial layer, a portion of the initial second sidewall being located between adjacent second trench layers and a portion of the initial second sidewall being located on the sidewall of the second trench layer.

[0017] Optionally, after forming the first contact layer on the surface of the first source / drain doped region, the method further includes: forming a second isolation layer on the first contact layer, wherein the top surface of the second isolation layer is lower than or flush with the top surface of the first isolation layer.

[0018] Optionally, after forming the second isolation layer, the method further includes: removing the initial second sidewall located on the sidewall of the second channel layer, forming a second sidewall on the sidewall of the second sacrificial layer, the second sidewall being located between adjacent second channel layers and flush with the sidewall of the second channel layer.

[0019] Optionally, the method for forming the second source / drain doped region includes: forming the second source / drain doped region within the first opening after forming the second sidewall.

[0020] Optionally, the method for forming the vertical stacked structure and the gate structure includes: after forming a second source / drain doped region, forming a dielectric structure on a substrate, wherein the dummy gate structure is located within the dielectric structure; removing the dummy gate structure, forming a gate opening within the dielectric structure, wherein the gate opening exposes a second sacrificial layer, a second channel layer, a first sacrificial layer, and the sidewall surface of the first channel layer; removing the second sacrificial layer and the first sacrificial layer exposed by the gate opening, forming a first groove between adjacent first channel layers and between the first channel layer and the first isolation layer, forming a second groove between adjacent second channel layers and between the second channel layer and the first isolation layer, and forming the vertical stacked structure; forming a gate structure within the gate opening, within the first groove, and within the second groove.

[0021] Optionally, the method for forming the first interconnect layer, the second interconnect layer, and the second contact layer includes: forming a third groove in the dielectric structure on both sides of the gate structure, the third groove exposing a portion of the surface of the second source / drain doped region; forming a second contact layer on the surface of the second source / drain doped region exposed by the third groove; after forming the second contact layer, forming a fill layer in the third groove; after forming the fill layer in the third groove, forming a fourth groove in the dielectric structure on both sides of the gate structure and in the second source / drain doped region, the fourth groove exposing a portion of the surface of the first contact layer; removing the fill layer, forming an insulating layer on the sidewalls of the third groove and the sidewalls of the fourth groove; after forming the insulating layer, forming a second interconnect layer in the third groove and forming a first interconnect layer in the fourth groove.

[0022] Optionally, the method for forming the second contact layer includes: forming a second metal layer on the surface of the second source / drain doped region; and performing heat treatment on the second metal layer to form the second contact layer.

[0023] Optionally, the method for forming the gate structure includes: after forming a second contact layer, forming a dielectric structure on a substrate, wherein the dummy gate structure is located within the dielectric structure; removing the dummy gate structure and forming a gate structure within the dielectric structure.

[0024] Optionally, the method for forming the first interconnect layer and the second interconnect layer includes: forming a third groove in the dielectric structure on both sides of the gate structure, the third groove exposing a portion of the surface of the second contact layer; forming a fourth groove in the dielectric structure on both sides of the gate structure and in the second source / drain doped region, the fourth groove exposing a portion of the surface of the first contact layer; forming a second insulating layer on the sidewall of the third groove and forming a first insulating layer on the sidewall of the fourth groove; after forming the second insulating layer and the first insulating layer, forming a second interconnect layer in the third groove and forming a first interconnect layer in the fourth groove.

[0025] Optionally, there are multiple first composite material layers, which are arranged parallel to a first direction and along a second direction. The first and second directions are parallel to the substrate surface, and the first direction is perpendicular to the second direction. There are multiple second composite material layers, and any one of the second composite material layers is located on the first composite material layer. The dummy gate structure spans several first and second composite material layers, and the dummy gate structure is parallel to the second direction.

[0026] Optionally, the central axis of the first interconnecting layer located on the same side of the gate structure, parallel to the extension direction of the gate structure, coincides with the central axis of the second interconnecting layer, which is also parallel to the extension direction of the gate structure.

[0027] Optionally, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction, and the second connection layer located on both sides of the gate structure coincides with the central axis of the first direction; or, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction and the second connection layer coincides with the central axis of the first direction.

[0028] Optionally, before forming the first source / drain doped region within the third opening, the method further includes: forming a first sidewall on the sidewall of the first sacrificial layer, the first sidewall being located between adjacent first channel layers and flush with the sidewall of the first channel layer.

[0029] Optionally, the method of forming the first sidewall includes: forming an initial first sidewall on the sidewall of the first sacrificial layer, wherein a portion of the initial first sidewall is located between adjacent first trench layers and a portion of the initial first sidewall is located on the sidewall of the first trench layer; removing the initial first sidewall from the sidewall of the first trench layer, forming a first sidewall on the sidewall of the first sacrificial layer, wherein the first sidewall is located between adjacent first trench layers and is flush with the sidewall of the first trench layer.

[0030] Optionally, the method for forming the second contact layer includes: forming a second metal layer on the surface of the second source / drain doped region exposed by the third groove; and performing heat treatment on the second metal layer to form the second contact layer on the surface of the second source / drain doped region.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] The semiconductor structure formation method of the present invention involves forming a first contact layer on the surface of a first source / drain doped region after forming a first source / drain doped region. The first contact layer has a first projection on the substrate surface. Then, after forming a second source / drain doped region, a second contact layer is formed on the surface of the second source / drain doped region. The second contact layer has a second projection on the substrate surface, and the area of ​​the first projection is greater than or equal to the area of ​​the second projection. The first and second contact layers are not formed simultaneously. Since the first contact layer is located on the entire surface of the first source / drain doped region, and the area of ​​the first projection of the first contact layer is greater than or equal to the area of ​​the second projection of the second contact layer, the overall area of ​​the first and second contact layers within the semiconductor structure is large. The first and second contact layers are conductive, thereby reducing the resistance of the semiconductor structure.

[0033] Furthermore, the central axis of the first interconnect layer parallel to the gate extension direction on the same side of the gate structure coincides with the central axis of the second interconnect layer parallel to the gate structure extension direction. The first and second interconnect layers on the same side of the gate structure are arranged parallel to the gate structure extension direction, thus requiring less space in the first direction while achieving electrical isolation, which is beneficial for further miniaturization of the semiconductor structure.

[0034] Furthermore, the first connection layers located on both sides of the gate structure coincide with the central axis parallel to the first direction, and the second connection layers located on both sides of the gate structure coincide with the central axis parallel to the first direction; or, the first connection layers on both sides of the gate structure coincide with the central axis parallel to the first direction, and the second connection layers coincide with the central axis parallel to the first direction. This provides good flexibility in the arrangement of the first and second connection layers on both sides of the gate structure, allowing for adjustments based on the design and performance requirements of the semiconductor structure. Simultaneously, when the first connection layers and the second connection layers on both sides of the gate structure coincide with the central axis parallel to the first direction, the first connection layer is electrically connected to the first source / drain doped region, and the second connection layer is electrically connected to the second source / drain doped region, resulting in good uniformity of the circuit current output from the first and second connection layers.

[0035] Furthermore, the sidewall of the fourth groove has an insulating layer, so that the first connecting layer located in the fourth groove can be electrically isolated from the second source / drain doped region, avoiding a short circuit when the first connecting layer and the second source / drain doped region are in direct contact. Attached Figure Description

[0036] Figure 1and Figure 2 This is a schematic diagram of the semiconductor structure in one embodiment;

[0037] Figures 3 to 21 This is a cross-sectional structural schematic diagram of the semiconductor structure formation process in an embodiment of the present invention;

[0038] Figures 22 to 24 This is a cross-sectional structural schematic diagram of the semiconductor structure formation process in another embodiment of the present invention;

[0039] Figure 25 This is a cross-sectional schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0040] As described in the background section, the performance of existing channel-gate-around fin field-effect transistors needs improvement. This will now be analyzed and explained with reference to specific embodiments.

[0041] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment.

[0042] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 Top view, Figure 1 for Figure 2A schematic diagram along section line AA1 shows the semiconductor structure comprising: a substrate 100; a first nanostructure on the substrate 100, the first nanostructure including a plurality of discrete first channel layers 101; an isolation structure 104 on the first nanostructure; a second nanostructure on the isolation structure 104, the second nanostructure including a plurality of discrete second channel layers 102; a third groove located between adjacent first channel layers 101 and between the first channel layers 101 and the isolation structure 104; a fourth groove located between adjacent second channel layers 102 and between the second channel layers 102 and the isolation structure 104; a gate structure 106 on the substrate 100, the gate structure 106 surrounding the first and second nanostructures, the gate structure 106 also located within the third and fourth grooves; and first source / drain doped regions located within the first nanostructures on both sides of the gate structure 106. 103; a first contact layer 109 located on the surface of the first source / drain doped region 103; a second source / drain doped region 105 located on the isolation structure 104, the second source / drain doped region 105 being located within the second nanostructures on both sides of the gate structure 106; a second contact layer 107 located on the second source / drain doped region 105; a dielectric structure 113 located on the second source / drain doped region 105; a second connection layer 108 located within the dielectric structures 113 on both sides of the gate structure 106, the second connection layer 108 being electrically connected to the second source / drain doped region 105 through the second contact layer 107; a first connection layer 110 located within the dielectric structures 113 on both sides of the gate structure 106 and the second source / drain doped region 105, the first connection layer 110 being electrically connected to the first source / drain doped region 103 through the first contact layer 109, the first connection layer 110 and the second connection layer 108 being parallel to the extension direction of the gate structure 106.

[0043] During the formation of the semiconductor structure, the first interconnect layer 110 and the second interconnect layer 108 are typically formed simultaneously after the formation of the second source / drain doped region 105. The first interconnect layer 110 and the second interconnect layer 108 are parallel to the extension direction of the gate structure 106. The method for forming the first interconnect layer 110 and the second interconnect layer 108 includes: forming a first groove (not shown) in the dielectric structure 113 on both sides of the gate structure 106 and in the second source / drain doped region 105, the first groove exposing a portion of the surface of the first source / drain doped region 103; forming a second groove (not shown) in the dielectric structure 113 on both sides of the gate structure 106, the second groove exposing a portion of the surface of the second source / drain doped region 105; forming a first contact layer 109 on the surface of the first source / drain doped region 103 exposed in the first groove, and forming a second contact layer 107 on the surface of the second source / drain doped region 105 exposed in the second groove; forming the first interconnect layer 110 in the first groove, and forming the second interconnect layer 108 in the second groove.

[0044] The first connecting layer 110 and the second connecting layer 108 are formed simultaneously. The first contact layer 109 is located at the bottom of the first groove, and the second contact layer 107 is located at the bottom of the second groove. As a result, the areas of the first contact layer 109 and the second contact layer 107 are both small. The contact resistance between the first connecting layer 110 and the first source / drain doped region 103 is relatively large, and the contact resistance between the second connecting layer 108 and the second source / drain doped region 105 is also relatively large.

[0045] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. After forming a first source / drain doped region, a first contact layer is formed on the surface of the first source / drain doped region. The first contact layer has a first projection on the substrate surface. Then, after forming a second source / drain doped region, a second contact layer is formed on the surface of the second source / drain doped region. The second contact layer has a second projection on the substrate surface. The area of ​​the first projection is greater than or equal to the area of ​​the second projection. The first and second contact layers are not formed simultaneously. Since the first contact layer is located on the entire surface of the first source / drain doped region, and the area of ​​the first projection of the first contact layer is greater than or equal to the area of ​​the second projection of the second contact layer, the overall area of ​​the first and second contact layers within the semiconductor structure is relatively large. The first and second contact layers are conductive, thereby reducing the resistance of the semiconductor structure.

[0046] Figures 3 to 21 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0047] Please refer to Figure 3 Substrate 200 is provided.

[0048] The substrate 200 includes an effective region A and ineffective regions B located on both sides of the effective region A.

[0049] In this embodiment, the substrate 200 is made of silicon.

[0050] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0051] Next, a vertical stacked structure is formed on the substrate. The vertical stacked structure on the effective region A includes a channel region and source / drain regions located on both sides of the channel region. The arrangement direction of the channel region and the source / drain regions is perpendicular to the extension direction of the vertical stacked structure. The channel region includes a first stacked region on the substrate, an isolation region on the first stacked region, and a second stacked region on the isolation region. The first stacked region includes a plurality of discrete first channel layers, with first grooves between adjacent first channel layers and between the first channel layers and the isolation region. The second stacked region includes a plurality of discrete second channel layers, with second grooves between adjacent second channel layers and between the second channel layers and the isolation region. Please refer to the process of forming the vertical stacked structure. Figures 4 to 14 .

[0052] In this embodiment, there are multiple vertical stacked structures, which are arranged parallel to a first direction and along a second direction. The first and second directions are parallel to the substrate surface, and the first direction is perpendicular to the second direction.

[0053] Please refer to Figure 4 A first composite material layer is formed on a substrate 200. The first composite material layer includes a plurality of first stacked structures. The first stacked structures include an initial first sacrificial layer 201 and an initial first channel layer 202 located on the initial first sacrificial layer 201. A second composite material layer is formed on the first composite material layer. The second composite material layer includes a plurality of second stacked structures. The second stacked structures include an initial second sacrificial layer 203 and an initial second channel layer 204 located on the initial second sacrificial layer 203.

[0054] In this embodiment, there are multiple first composite material layers, which are arranged parallel to a first direction and along a second direction. The first and second directions are parallel to the surface of the substrate 200, and the first direction is perpendicular to the second direction. There are also multiple second composite material layers, with any one of the second composite material layers located on the first composite material layer.

[0055] The material of the initial first sacrificial layer 201 is different from the material of the initial first channel layer 202, so that the removal process causes less damage to the initial first channel layer 202 when the initial first sacrificial layer 201 is removed; the material of the initial second sacrificial layer 203 is different from the material of the initial second channel layer 204, so that the removal process causes less damage to the initial second channel layer 204 when the initial second sacrificial layer 203 is removed.

[0056] In this embodiment, the materials of the initial first sacrificial layer 201 and the initial second sacrificial layer 203 include silicon and germanium; the materials of the initial first channel layer 202 and the initial second channel layer 204 include silicon.

[0057] In this embodiment, the initial first channel layer 202 has a P-type conductivity and the initial second channel layer 204 has an N-type conductivity.

[0058] In other embodiments, the initial first channel layer is of N-type conductivity and the initial second channel layer is of P-type conductivity.

[0059] Please continue to refer to this. Figure 4 A pseudo-gate structure 205 is formed on the substrate 200, the pseudo-gate structure 205 spanning the first composite material layer and the second composite material layer on the effective region A, and the pseudo-gate structure 205 also spanning the first composite material layer and the second composite material layer on the ineffective region B.

[0060] In this embodiment, the dummy gate structure 205 is parallel to the second direction.

[0061] The dummy gate structure 205 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer. The material of the dummy gate dielectric layer includes silicon oxide or a low-k (K less than 3.9) material; the material of the dummy gate layer includes polysilicon.

[0062] Please refer to Figure 5 Remove a portion of the second composite material layer on both sides of the dummy gate structure 205 on the effective region A until the surface of the initial first channel layer 202 of the first composite material layer is exposed. Form a first opening 206 in the second composite material layer, so that the initial second sacrificial layer 203 is formed into a second sacrificial layer 207, so that the initial second channel layer 204 is formed into a second channel layer 208, and form the second stacked region.

[0063] Please refer to Figure 6 An initial second sidewall 209 is formed on the sidewall of the second sacrificial layer 207, a portion of the initial second sidewall 209 being located between adjacent second channel layers 208, and a portion of the initial second sidewall 209 being located on the sidewall of the second channel layer 208.

[0064] The method for forming the initial second sidewall 209 includes: removing a portion of the second sacrificial layer 207 exposed by the first opening 206, forming a groove (not shown) between adjacent second channel layers 208; forming a sidewall material layer (not shown) on the sidewall of the second channel layer 208, in the groove, and on the surface of the initial first channel layer 202; and etching back the sidewall material layer until the surface of the initial first channel layer 202 is exposed to form the initial second sidewall 209.

[0065] The material of the initial second sidewall 209 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0066] In this embodiment, the material of the initial second sidewall 209 includes silicon nitride.

[0067] Please refer to Figure 7 After forming the initial second sidewall 209, the portion of the initial first channel layer 202 exposed by the first opening 206 is removed, and a second opening 210 is formed at the bottom of the first opening 206. The second opening 210 is also located at the bottom of the second sacrificial layer 207, forming the isolation zone.

[0068] The method for forming the second opening 210 includes: using the initial second sidewall 209 as a mask, etching the initial first trench layer 202 until the surface of the initial first sacrificial layer 201 is exposed to form an initial second opening (not shown); and laterally etching away the initial first trench layer 202 at the bottom of the second sacrificial layer 207 to form the second opening 210.

[0069] In this embodiment, a portion of the second opening 210 is also located on the invalid region B.

[0070] Please refer to Figure 8 A first isolation layer 211 is formed in the second opening 210 at the bottom of the second sacrificial layer 207, and the first isolation layer 211 is located in the isolation area.

[0071] The method for forming the first isolation layer 211 includes: forming an isolation material layer (not shown) in the second opening 210; removing the isolation material layer at the bottom of the first opening 206; and forming the first isolation layer 211 in the second opening 210 at the bottom of the second sacrificial layer 207.

[0072] In this embodiment, a portion of the first isolation layer 211 is also located on the invalid region B.

[0073] The material of the first isolation layer 211 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0074] In this embodiment, the material of the first isolation layer 211 includes silicon oxide.

[0075] Please refer to Figure 9After forming the first isolation layer 211, the first composite material layer exposed by the second opening 210 is removed until the surface of the substrate 200 is exposed. A third opening 212 is formed in the first composite material layer, and the initial first sacrificial layer 201 is formed as the first sacrificial layer 213, and the initial first channel layer 202 is formed as the first channel layer 214, thus forming the first stacked region.

[0076] The method for removing the first composite material layer exposed by the second opening 210 includes: etching the first composite material layer using the initial second sidewall 209 as a mask.

[0077] Please refer to Figure 10 A first sidewall 215 is formed on the sidewall of the first sacrificial layer 213. The first sidewall 215 is located between adjacent first channel layers 214 and is flush with the sidewall of the first channel layer 214.

[0078] The method of forming the first sidewall 215 includes: removing a portion of the first sacrificial layer 213 exposed by the third opening 212, forming a groove (not shown) on the sidewall of the first sacrificial layer 213; forming an initial first sidewall (not shown) in the groove on the sidewall of the first sacrificial layer 213, a portion of the initial first sidewall being located between adjacent first channel layers 214, and a portion of the initial first sidewall being located on the sidewall of the first channel layer 214; removing the initial first sidewall from the sidewall of the first channel layer 214, forming a first sidewall 215 on the sidewall of the first sacrificial layer 213, the first sidewall 215 being located between adjacent first channel layers 214, and the first sidewall 215 being flush with the sidewall of the first channel layer 214.

[0079] The material of the first sidewall 215 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0080] In this embodiment, the material of the first sidewall 215 includes silicon nitride.

[0081] Please refer to Figure 11 A first source / drain doped region 216 is formed within the third opening 212, and the first source / drain doped region 216 is located within the source / drain regions on both sides of the first stacked region.

[0082] The material of the first source / drain doped region 216 includes silicon-germanium or silicon-phosphorus. In this embodiment, the material of the first source / drain doped region 216 includes silicon-germanium, and the first source / drain doped region 216 is used to form a P-type device.

[0083] Please refer to Figure 12A first contact layer 217 is formed on the surface of the first source / drain doped region 216, and the first contact layer 217 has a first projection on the surface of the substrate 200.

[0084] The method of forming the first contact layer 217 includes: forming a first metal layer (not shown) on the surface of the first source / drain doped region 216; performing heat treatment on the first metal layer to form the first contact layer 217 on the surface of the first source / drain doped region 216.

[0085] Since the material of the first source / drain doped region 216 includes silicon and germanium, the first metal layer and the surface of the first source / drain doped region 216 are heat-treated to form the first contact layer 217.

[0086] The material of the first contact layer 217 includes a metal silicide, which includes tungsten silicide.

[0087] Please continue to refer to this. Figure 12 A second isolation layer 218 is formed on the first contact layer 217, and the top surface of the second isolation layer 218 is lower than or flush with the top surface of the first isolation layer 211.

[0088] The method for forming the second isolation layer 218 includes: forming an isolation material layer (not shown) on the first contact layer 217; and etching back the isolation material layer to form the second isolation layer 218.

[0089] The material of the second isolation layer 218 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0090] In this embodiment, the material of the second isolation layer 218 includes silicon oxide.

[0091] Please refer to Figure 13 The initial second sidewall 209 located on the sidewall of the second channel layer 208 is removed, and a second sidewall 219 is formed on the sidewall of the second sacrificial layer 207. The second sidewall 219 is located between adjacent second channel layers 208 and is flush with the sidewall of the second channel layer 208.

[0092] Please continue to refer to this. Figure 13 After the second sidewall 219 is formed, a second source / drain doped region 220 is formed in the first opening 206 on the second isolation layer 218, and the second source / drain doped region 220 is located in the source / drain regions on both sides of the second stacked region.

[0093] The material of the second source / drain doped region 220 includes silicon-germanium or silicon-phosphorus. In this embodiment, the material of the second source / drain doped region 220 includes silicon-phosphorus, and the second source / drain doped region 220 is used to form an N-type device.

[0094] Please refer to Figure 14 A gate structure 221 is formed on the substrate, the gate structure 221 surrounds the first channel layer 214 and the second channel layer 208, and the gate structure 221 is also located in the first groove and the second groove.

[0095] The method for forming the vertical stacked structure and the gate structure includes: after forming a second source / drain doped region 220, forming a dielectric structure 222 on a substrate 200, wherein the dummy gate structure 205 is located within the dielectric structure 222; removing the dummy gate structure 205, forming a gate opening (not shown) within the dielectric structure 222, wherein the gate opening exposes the sidewall surfaces of a second sacrificial layer 207, a second channel layer 208, a first sacrificial layer 213, and a first channel layer 214; removing the second sacrificial layer 207 and the first sacrificial layer 213 exposed by the gate opening, forming a first groove (not shown) between adjacent first channel layers 214 and between the first channel layer 214 and the first isolation layer 211, forming a second groove (not shown) between adjacent second channel layers 208 and between the second channel layer 208 and the first isolation layer 211, and forming the vertical stacked structure; forming a gate structure 221 within the gate opening, the first groove, and the second groove.

[0096] Please refer to Figure 15 and Figure 16 , Figure 15 for Figure 16 Top view, Figure 16 for Figure 15 A cross-sectional structural schematic diagram along the CC1 direction shows that a second contact layer 224 is formed on part or all of the surface of the second source / drain doped region 220. The second contact layer 224 has a second projection on the surface of the substrate 200, and the area of ​​the first projection is greater than or equal to the area of ​​the second projection.

[0097] The method of forming the second contact layer 224 includes: forming a third groove (not shown) in the dielectric structure 222 on both sides of the gate structure 221, the third groove exposing a portion of the surface of the second source / drain doped region 220; forming a second metal layer (not shown) on the surface of the second source / drain doped region 220 exposed by the third groove; and performing heat treatment on the second metal layer to form the second contact layer 224 on the surface of the second source / drain doped region 220.

[0098] Since the material of the second source / drain doped region 220 includes phosphorus silicon, the second metal layer and the surface of the second source / drain doped region 220 are heat-treated to form a second contact layer 224.

[0099] The material of the second contact layer 224 includes a metal silicide, which includes tungsten silicide.

[0100] The first contact layer 217 and the second contact layer 224 are not formed simultaneously. Since the first contact layer 217 is located on the entire surface of the first source / drain doped region 216, the area of ​​the first projection of the first contact layer 217 is greater than or equal to the area of ​​the second projection of the second contact layer 224. As a result, the overall area of ​​the first contact layer 217 and the second contact layer 224 in the semiconductor structure is large. The first contact layer 217 and the second contact layer 224 are conductive, thereby reducing the resistance of the semiconductor structure.

[0101] Please continue to refer to this. Figure 15 and Figure 16 After the second contact layer 224 is formed, a filling layer 225 is formed in the third groove.

[0102] The filler layer 225 is made of an amorphous material, including amorphous carbon or amorphous silicon, so that it can be easily removed later.

[0103] Next, a second connection layer is formed on both sides of the gate structure 221. The second connection layer is electrically connected to the second source / drain doped region 220 through the second contact layer 224. A first connection layer is formed within the second source / drain doped region 220 on both sides of the gate structure 221. The first connection layer is electrically connected to the first source / drain doped region 216 through the first contact layer 217. Please refer to [link to documentation] for the formation process of the first and second connection layers. Figures 17 to 21 .

[0104] Please refer to Figure 17 and Figure 18 , Figure 17 for Figure 18 Top view, Figure 18 for Figure 17 A cross-sectional view along the DD1 direction shows that after the filling layer 225 is formed, a fourth groove 226 is formed in the dielectric structure 222 on both sides of the gate structure 221 and in the second source / drain doped region 220. The fourth groove 226 exposes part of the surface of the first contact layer 217.

[0105] The method for forming the fourth groove 226 includes: forming a patterned layer (not shown) on the dielectric structure 222; etching the dielectric structure 222, the second source / drain doped region 220, and the second isolation layer 218 using the patterned layer as a mask until the surface of the first contact layer 217 is exposed, thereby forming the fourth groove 226.

[0106] The etching process for the dielectric structure 222, the second source / drain doped region 220, and the second isolation layer 218 includes a dry etching process.

[0107] Please refer to Figures 19 to 21 , Figure 19 for Figure 20 and Figure 21 Top view, Figure 20 for Figure 18 A schematic diagram of the cross-sectional structure along the section line CC1. Figure 21 for Figure 18 A cross-sectional structural diagram along the DD1 direction, showing the removal of the filler layer 225; after removing the filler layer 225, a second insulating layer 227 is formed on the sidewall of the third groove, and a first insulating layer 229 is formed on the sidewall of the fourth groove 226; after forming the second insulating layer 227 and the first insulating layer 229, a second connecting layer 228 is formed in the third groove, and a first connecting layer 230 is formed in the fourth groove 226.

[0108] The method for forming the second insulating layer 227 and the first insulating layer 229 includes: forming a sidewall material layer (not shown) on the sidewall surface and bottom surface of the third groove, and the sidewall surface and bottom surface of the fourth groove 226; etching back the sidewall material layer until the sidewall material layer on the bottom surface of the third groove and the bottom surface of the fourth groove 226 is removed; forming the second insulating layer 227 on the sidewall of the third groove and forming the first insulating layer 229 on the sidewall of the fourth groove 226.

[0109] The materials of the second insulating layer 227 and the first insulating layer 229 include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0110] In this embodiment, the materials of the second insulating layer 227 and the first insulating layer 229 include silicon nitride.

[0111] The sidewall of the fourth groove 226 has a first insulating layer 229, so that the first connecting layer 230 located in the fourth groove 226 can be electrically isolated from the second source / drain doped region 220, avoiding a short circuit when the first connecting layer 230 and the second source / drain doped region 220 are in direct contact.

[0112] In this embodiment, the first connection layer 230 located on both sides of the gate structure 221 coincides with the central axis of the first direction, and the second connection layer 228 located on both sides of the gate structure 221 coincides with the central axis of the first direction.

[0113] In other embodiments, the central axis of the first interconnect layer located on both sides of the gate structure is parallel to the central axis of the first direction and coincides with the central axis of the second interconnect layer located parallel to the first direction.

[0114] The first interconnect layers located on both sides of the gate structure coincide with the central axis of the first direction, and the second interconnect layers located on both sides of the gate structure coincide with the central axis of the first direction; or, the first interconnect layers on both sides of the gate structure coincide with the central axis of the first direction, and the second interconnect layers coincide with the central axis of the first direction. Therefore, the arrangement of the first interconnect layers 230 and the second interconnect layers 228 on both sides of the gate structure 221 offers good flexibility and can be adjusted at any time according to the design and performance requirements of the semiconductor structure.

[0115] In this embodiment, the central axis of the first connection layer 230, which is located on the same side of the gate structure 221 and is parallel to the extension direction of the gate structure 221, coincides with the central axis of the second connection layer 228, which is parallel to the extension direction of the gate structure 221.

[0116] The first connection layer 230 and the second connection layer 228 on the same side of the gate structure 221 are arranged parallel to the extension direction of the gate structure 221. Thus, the first connection layer 230 and the second connection layer 228 require less space in the first direction while achieving electrical isolation, which is beneficial for further miniaturization of the semiconductor structure.

[0117] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 19 to 21 ,include:

[0118] Substrate 200;

[0119] A vertical stacked structure located on a substrate 200 includes a channel region and source / drain regions located on both sides of the channel region. The arrangement direction of the channel region and the source / drain regions is perpendicular to the extension direction of the vertical stacked structure. The channel region includes a first stacked region on the substrate, an isolation region on the first stacked region, and a second stacked region on the isolation region. The first stacked region includes a plurality of discrete first channel layers 214, and a first groove is provided between adjacent first channel layers 214 and between the first channel layer 214 and the isolation region. The second stacked region includes a plurality of discrete second channel layers 208, and a second groove is provided between adjacent second channel layers 208 and between the second channel layer 208 and the isolation region.

[0120] The first isolation layer 211 is located within the isolation zone;

[0121] A gate structure 221 is located on the substrate 200, the gate structure 221 surrounds the first channel layer 214 and the second channel layer 208, and the gate structure 221 is also located in the first groove and the second groove.

[0122] The first source / drain doped region 216 is located in the source / drain regions on both sides of the first stacked region;

[0123] A first contact layer 217 is located on the surface of the first source / drain doped region 216, and the first contact layer 217 has a first projection on the surface of the substrate 200.

[0124] The second source / drain doped region 220 is located on the first contact layer 217 and is located in the source / drain regions on both sides of the second stacked region.

[0125] A second contact layer 224 is located on the surface of the second source / drain doped region 220. The second contact layer 224 has a second projection on the surface of the substrate 200, and the area of ​​the first projection is greater than or equal to the area of ​​the second projection.

[0126] The second connection layer 228 is located on both sides of the gate structure 221, and the second connection layer 228 is electrically connected to the second source / drain doped region 220 through the second contact layer 224;

[0127] The first connection layer 230 is located in the second source / drain doped region 220 on both sides of the gate structure 221. The first connection layer 230 is electrically connected to the first source / drain doped region 216 through the first contact layer 217.

[0128] In this embodiment, there are multiple vertical stacked structures, which are arranged parallel to a first direction and along a second direction. The first and second directions are parallel to the surface of the substrate 200, and the first direction is perpendicular to the second direction. The gate structure 221 spans a plurality of the channel regions and is parallel to the second direction.

[0129] In this embodiment, a second isolation layer 218 is also included, located between the first contact layer 217 and the second source / drain doped region 220, wherein the top surface of the second isolation layer 218 is lower than or flush with the top surface of the first isolation layer 211.

[0130] In this embodiment, it further includes: a first insulating layer 229 located on the sidewall surface of the first connecting layer 230, and a second insulating layer 227 located on the sidewall surface of the second connecting layer 228.

[0131] In this embodiment, the central axis of the first connection layer 230, which is located on the same side of the gate structure 221 and is parallel to the extension direction of the gate structure 221, coincides with the central axis of the second connection layer 228, which is parallel to the extension direction of the gate structure 221.

[0132] In this embodiment, the first connection layer 230 located on both sides of the gate structure 221 coincides with the central axis of the first direction, and the second connection layer 228 located on both sides of the gate structure 221 coincides with the central axis of the first direction.

[0133] In other embodiments, the central axis of the first interconnect layer located on both sides of the gate structure is parallel to the central axis of the first direction and coincides with the central axis of the second interconnect layer located parallel to the first direction.

[0134] In this embodiment, it further includes: a first sidewall 215 located on the sidewall of the gate structure 221 in the first recess, the first sidewall 215 being located between adjacent first channel layers 214 and between the first channel layer 214 and the first isolation layer 211, and the first sidewall 215 being flush with the sidewall of the first channel layer 214; and a second sidewall 219 located on the sidewall of the gate structure 221 in the second recess, the second sidewall 219 being located between adjacent second channel layers 208 and between the second channel layer 208 and the first isolation layer 211, and the second sidewall 219 being flush with the sidewall of the second channel layer 208.

[0135] In this embodiment, the first channel layer 214 has an N-type conductivity and the second channel layer 208 has a P-type conductivity; or, the first channel layer 214 has a P-type conductivity and the second channel layer 208 has an N-type conductivity.

[0136] Figures 22 to 24 This is a cross-sectional schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0137] Please refer to Figures 22 to 24 , Figure 22 for Figure 23 and Figure 24 Top view, Figure 23 for Figure 22 A schematic diagram of the cross-sectional structure along the section line CC1. Figure 24 for Figure 22 A schematic diagram of the cross-sectional structure along section line DD1. Figures 22 to 24 Structure and Figures 19 to 21 The structural difference is that the first connection layer 328 located on both sides of the gate structure 221 is parallel to the central axis of the first direction and coincides with the second connection layer 329 which is parallel to the central axis of the first direction.

[0138] That is, the first connection layers 330 on both sides of the gate structure 221 are located diagonally, and the second connection layers 328 on both sides of the gate structure 221 are located diagonally. The first connection layer 330 is electrically connected to the first source / drain doped region 216, and the second connection layer 328 is electrically connected to the second source / drain doped region 220, so that the circuit current from the first connection layer 330 and the circuit current from the second connection layer 328 have good uniformity.

[0139] Figure 25 This is a cross-sectional schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0140] Please refer to Figure 25 , Figure 25 In order to be in Figure 13 Based on the structural schematic diagram, a second metal layer (not shown) is formed on the surface of the second source / drain doped region; the second metal layer is heat-treated to form the second contact layer 424.

[0141] In this embodiment, the second contact layer 424 is located on the entire surface of the second source / drain doped region 220, so the overall area of ​​the first contact layer 217 and the second contact layer 424 in the semiconductor structure is large. The first contact layer 217 and the second contact layer 424 are conductive, thereby reducing the resistance of the semiconductor structure.

[0142] Please refer to the process of forming the first and second connection layers. Figures 14 to 21 This will not be elaborated upon here.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A vertically stacked structure located on a substrate, the vertically stacked structure including a channel region and source / drain regions located on both sides of the channel region, the arrangement direction of the channel region and the source / drain regions being perpendicular to the extension direction of the vertically stacked structure, the channel region including a first stacked region located on the substrate, an isolation region located on the first stacked region, and a second stacked region located on the isolation region, the first stacked region including a plurality of vertically stacked first channel layers, with a first groove between adjacent first channel layers and between the first channel layer and the isolation region, the second stacked region including a plurality of discrete second channel layers, with a second groove between adjacent second channel layers and between the second channel layer and the isolation region; The first isolation layer located within the isolation zone; A gate structure located on a substrate, the gate structure surrounding the first channel layer and the second channel layer, and the gate structure also located within the first groove and the second groove; A first sidewall located on the sidewall of the gate structure within the first recess, the first sidewall being located between adjacent first channel layers and between the first channel layer and the first isolation layer, and the first sidewall being flush with the sidewall of the first channel layer; The second sidewall is located on the sidewall of the gate structure in the second recess. The second sidewall is located between adjacent second channel layers and between the second channel layer and the first isolation layer, and the second sidewall is flush with the sidewall of the second channel layer. The first source / drain doped region is located within the source / drain regions on both sides of the first stacked region; A first contact layer located on the surface of a first source / drain doped region, the first contact layer having a first projection on the substrate surface; The second source / drain doped region is located on the first contact layer, and the second source / drain doped region is located in the source / drain regions on both sides of the second stacked region; A second contact layer located on the surface of the second source / drain doped region, the second contact layer having a second projection on the substrate surface, the area of ​​the first projection being greater than or equal to the area of ​​the second projection; A second connection layer is located on both sides of the gate structure, and the second connection layer is electrically connected to the second source / drain doped region through a second contact layer; The first connection layer is located in the second source / drain doped region on both sides of the gate structure. The first connection layer is electrically connected to the first source / drain doped region through the first contact layer.

2. The semiconductor structure as described in claim 1, characterized in that, The number of vertical stacked structures is multiple, and the multiple vertical stacked structures are arranged parallel to a first direction and along a second direction. The first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction. The gate structure spans a plurality of the channel regions, and the gate structure is parallel to the second direction.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second isolation layer is located between the first contact layer and the second source / drain doped region, wherein the top surface of the second isolation layer is lower than or flush with the top surface of the first isolation layer.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first insulating layer located on the sidewall surface of the first connecting layer, and a second insulating layer located on the sidewall surface of the second connecting layer.

5. The semiconductor structure as described in claim 1, characterized in that, The central axis of the first interconnect layer, located on the same side of the gate structure and parallel to the extension direction of the gate structure, coincides with the central axis of the second interconnect layer, which is also parallel to the extension direction of the gate structure.

6. The semiconductor structure as described in claim 5, characterized in that, The first connection layer located on both sides of the gate structure coincides with the central axis of the first direction, and the second connection layer located on both sides of the gate structure coincides with the central axis of the first direction; or, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction and the second connection layer coincides with the central axis of the first direction.

7. The semiconductor structure as described in claim 1, characterized in that, The first channel layer has an N-type conductivity and the second channel layer has a P-type conductivity; or, the first channel layer has a P-type conductivity and the second channel layer has an N-type conductivity.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A vertical stacked structure is formed on a substrate. The vertical stacked structure includes a channel region and source / drain regions located on both sides of the channel region. The arrangement direction of the channel region and the source / drain regions is perpendicular to the extension direction of the vertical stacked structure. The channel region includes a first stacked region on the substrate, an isolation region on the first stacked region, and a second stacked region on the isolation region. The first stacked region includes a plurality of discrete first channel layers. A first groove is provided between adjacent first channel layers and between the first channel layer and the isolation region. The second stacked region includes a plurality of discrete second channel layers. A second groove is provided between adjacent second channel layers and between the second channel layer and the isolation region. A first isolation layer is formed within the isolation zone; A gate structure is formed on a substrate, the gate structure surrounding the first channel layer and the second channel layer, and the gate structure is also located within the first groove and the second groove; First source / drain doped regions are formed in the source / drain regions on both sides of the first stacked region; A first contact layer is formed on the surface of the first source / drain doped region, and the first contact layer has a first projection on the substrate surface; A second source / drain doped region is formed on the first contact layer, and the second source / drain doped region is located in the source / drain regions on both sides of the second stacked region; A second contact layer is formed on the surface of part or all of the second source / drain doped regions, the second contact layer having a second projection on the substrate surface, the area of ​​the first projection being greater than or equal to the area of ​​the second projection; A first connection layer is formed in the second source / drain doped regions on both sides of the gate structure, and the first connection layer is electrically connected to the first source / drain doped regions through a first contact layer. A second connection layer is formed on both sides of the gate structure, and the second connection layer is electrically connected to the second source / drain doped region through a second contact layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the vertical stacked structure, the first isolation layer, and the first source / drain doped region includes: forming a first composite material layer on a substrate, the first composite material layer including a plurality of first stacked structures, the first stacked structure including an initial first sacrificial layer and an initial first channel layer located on the initial first sacrificial layer; forming a second composite material layer on the first composite material layer, the second composite material layer including a plurality of second stacked structures, the second stacked structure including an initial second sacrificial layer and an initial second channel layer located on the initial second sacrificial layer; forming a dummy gate structure on the substrate, the dummy gate structure spanning the first composite material layer and the second composite material layer; removing portions of the second composite material layer on both sides of the dummy gate structure until the surface of the first composite material layer is exposed, and then forming a second composite material layer... A first opening is formed within the first opening, causing the initial second sacrificial layer to become a second sacrificial layer and the initial second channel layer to become a second channel layer, forming the second stacked region; the portion of the initial first channel layer exposed by the first opening is removed, and a second opening is formed at the bottom of the first opening, the second opening also located at the bottom of the second sacrificial layer, forming the isolation region; a first isolation layer is formed within the second opening at the bottom of the second sacrificial layer; after forming the first isolation layer, the first composite material layer exposed by the second opening is removed until the substrate surface is exposed, a third opening is formed within the first composite material layer, and the initial first sacrificial layer is formed as a first sacrificial layer, causing the initial first channel layer to become a first channel layer, forming the first stacked region; a first source / drain doped region is formed within the third opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first contact layer includes: forming a first metal layer on the surface of a first source / drain doped region; and performing heat treatment on the first metal layer to form the first contact layer on the surface of the first source / drain doped region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before removing the portion of the initial first channel layer exposed by the first opening, the method further includes: forming an initial second sidewall on the sidewall of the second sacrificial layer, a portion of the initial second sidewall being located between adjacent second channel layers and a portion of the initial second sidewall being located on the sidewall of the second channel layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming a first contact layer on the surface of the first source / drain doped region, the method further includes: forming a second isolation layer on the first contact layer, wherein the top surface of the second isolation layer is lower than or flush with the top surface of the first isolation layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the second isolation layer, the process further includes: removing the initial second sidewall located on the sidewall of the second channel layer, forming a second sidewall on the sidewall of the second sacrificial layer, the second sidewall being located between adjacent second channel layers and flush with the sidewall of the second channel layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the second source / drain doped region includes: after forming the second sidewall, forming the second source / drain doped region within the first opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the vertical stacked structure and the gate structure includes: after forming a second source / drain doped region, forming a dielectric structure on a substrate, wherein the dummy gate structure is located within the dielectric structure; removing the dummy gate structure, forming a gate opening within the dielectric structure, wherein the gate opening exposes a second sacrificial layer, a second channel layer, a first sacrificial layer, and the sidewall surface of the first channel layer; removing the second sacrificial layer and the first sacrificial layer exposed by the gate opening, forming a first groove between adjacent first channel layers and between the first channel layer and the first isolation layer, forming a second groove between adjacent second channel layers and between the second channel layer and the first isolation layer, and forming the vertical stacked structure; and forming a gate structure within the gate opening, the first groove, and the second groove.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming a first interconnect layer, a second interconnect layer, and a second contact layer includes: forming a third groove in a dielectric structure on both sides of a gate structure, the third groove exposing a portion of the surface of the second source / drain doped region; forming a second contact layer on the surface of the second source / drain doped region exposed by the third groove; after forming the second contact layer, forming a fill layer in the third groove; after forming the fill layer in the third groove, forming a fourth groove in the dielectric structure on both sides of the gate structure and in the second source / drain doped region, the fourth groove exposing a portion of the surface of the first contact layer; removing the fill layer; forming an insulating layer on the sidewalls of the third groove and the fourth groove; after forming the insulating layer, forming a second interconnect layer in the third groove and forming a first interconnect layer in the fourth groove.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the second contact layer includes: forming a second metal layer on the surface of the second source / drain doped region; and performing heat treatment on the second metal layer to form the second contact layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the gate structure includes: after forming a second contact layer, forming a dielectric structure on a substrate, wherein the dummy gate structure is located within the dielectric structure; removing the dummy gate structure, and forming a gate structure within the dielectric structure.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method for forming the first interconnect layer and the second interconnect layer includes: forming a third groove in the dielectric structure on both sides of the gate structure, the third groove exposing a portion of the surface of the second contact layer; forming a fourth groove in the dielectric structure on both sides of the gate structure and in the second source / drain doped region, the fourth groove exposing a portion of the surface of the first contact layer; forming a second insulating layer on the sidewall of the third groove and forming a first insulating layer on the sidewall of the fourth groove; after forming the second insulating layer and the first insulating layer, forming a second interconnect layer in the third groove and forming a first interconnect layer in the fourth groove.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, The number of the first composite material layers is multiple, and the multiple first composite material layers are arranged parallel to the first direction and along the second direction. The first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction. The number of the second composite material layers is multiple, and any one of the second composite material layers is located on the first composite material layer. The pseudo-gate structure spans several first composite material layers and second composite material layers, and the pseudo-gate structure is parallel to the second direction.

21. The method for forming a semiconductor structure as described in claim 9, characterized in that, The central axis of the first interconnect layer, located on the same side of the gate structure and parallel to the extension direction of the gate structure, coincides with the central axis of the second interconnect layer, which is also parallel to the extension direction of the gate structure.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The first connection layer located on both sides of the gate structure coincides with the central axis of the first direction, and the second connection layer located on both sides of the gate structure coincides with the central axis of the first direction; or, the first connection layer located on both sides of the gate structure coincides with the central axis of the first direction and the second connection layer coincides with the central axis of the first direction.

23. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the first source / drain doped region within the third opening, the method further includes: forming a first sidewall on the sidewall of the first sacrificial layer, the first sidewall being located between adjacent first channel layers and flush with the sidewall of the first channel layer.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The method of forming the first sidewall includes: forming an initial first sidewall on the sidewall of the first sacrificial layer, wherein a portion of the initial first sidewall is located between adjacent first trench layers and a portion of the initial first sidewall is located on the sidewall of the first trench layer; removing the initial first sidewall from the sidewall of the first trench layer, forming a first sidewall on the sidewall of the first sacrificial layer, wherein the first sidewall is located between adjacent first trench layers and is flush with the sidewall of the first trench layer.

25. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the second contact layer includes: forming a second metal layer on the surface of the second source / drain doped region exposed by the third groove; and performing heat treatment on the second metal layer to form the second contact layer on the surface of the second source / drain doped region.

Images