A bias voltage temperature coefficient adjusting circuit

Abstract

The application provides a bias voltage temperature coefficient adjusting circuit, which comprises a first current branch, a voltage adjusting branch and a second current branch. The first current branch is used for providing a first zero-temperature-coefficient current with adjustable size and a first node voltage. The voltage adjusting branch is used for providing a zero-temperature-coefficient voltage. The second current branch is used for providing a second zero-temperature-coefficient current with adjustable size and generating a bias voltage according to the first node voltage and the zero-temperature-coefficient voltage. The temperature coefficient of the bias voltage is adjusted by the ratio of the first zero-temperature-coefficient current to the second zero-temperature-coefficient current. The application can ensure that a transistor is kept in a saturation region and the performance of a chip is ensured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to a bias voltage temperature coefficient adjustment circuit. Background Technology

[0002] The tail current source array of a current-controlled DAC typically employs a two- or three-stage cascode structure to achieve high output impedance. With advancements in manufacturing processes, supply voltages have become increasingly smaller, thus reducing the voltage margin (V) available for the cascode-stage MOSFETs. DS The transistor's overdrive voltage V is decreasing in size, while the chip operates over a wide temperature range, from -55°C to 150°C. DSAT Changes in transistor density can easily cause transistors to enter the linear region, thereby affecting the overall performance of the chip. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes a bias voltage temperature coefficient adjustment circuit, which mainly solves the problem that the overdrive voltage of the transistor in the existing tail current source changes with temperature, thereby affecting the device performance.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides a bias voltage temperature coefficient adjustment circuit, comprising: a first current branch for providing an adjustable first zero temperature coefficient current and a first node voltage; a voltage adjustment branch for providing a zero temperature coefficient voltage; and a second current branch for providing an adjustable second zero temperature coefficient current, and generating a bias voltage based on the first node voltage and the zero temperature coefficient voltage, wherein the temperature coefficient of the bias voltage is adjusted by the ratio of the first zero temperature coefficient current to the second zero temperature coefficient current.

[0006] In one embodiment, the voltage regulation branch includes a first programmable current source, a second programmable current source, and an on-chip resistor; the input terminal of the first programmable current source is connected to the power supply voltage, and the output terminal is connected to one end of the on-chip resistor as the output terminal of the voltage regulation branch; the other end of the on-chip resistor is connected to the first node voltage and the input terminal of the second programmable current source, respectively, and the output terminal of the second programmable current source is grounded.

[0007] In one embodiment, the first current branch includes a third programmable current source and a first transistor. The input terminal of the third programmable current source is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the first transistor to output the first node voltage. The gate terminal and drain terminal of the first transistor are shorted together, and the source terminal of the first transistor is grounded.

[0008] In one embodiment, the second current branch includes a fourth programmable current source, a second transistor, and a fifth programmable current source. The input terminal of the fourth programmable current source is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the second transistor. The gate terminal and drain terminal of the second transistor are shorted together, and the gate terminal is connected to the output terminal of the voltage regulation branch. The source terminal of the second transistor is connected to the input terminal of the fifth programmable current source as the output terminal of the second current branch to output a bias voltage. The output terminal of the fifth programmable current source is grounded.

[0009] In one embodiment, a first buffer is further included, wherein the positive input terminal of the first buffer is connected to the output terminal of the second current branch, and the negative input terminal of the first buffer is shorted to the output terminal and then connected to the gate terminal of the second transistor.

[0010] In one embodiment, the output of the second current branch is connected to the tail current source array via a second buffer; the second buffer includes a comparator and a third transistor; the positive input of the comparator is connected to the bias voltage, and the negative input is connected to the source of the third transistor; the output of the comparator is connected to the gate of the third transistor. The tail current source array includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the drain of the fourth transistor is connected to the output of the first current branch, the gate of the fourth transistor is connected to the source of the third transistor, the source of the fourth transistor is connected to the source of the fifth transistor and the drain of the sixth transistor, the gate of the fifth transistor is connected to the drain of the third transistor, and the drain of the fifth transistor is connected to the output of the voltage regulation branch; the gate of the sixth transistor is connected to a preset first bias voltage, the source of the sixth transistor is connected to the drain of the seventh transistor, the gate of the seventh transistor is connected to the gate of the third transistor, the source of the seventh transistor is connected to the drain of the eighth transistor, the gate of the eighth transistor is connected to a preset second bias voltage, and the source of the eighth transistor is grounded.

[0011] In one embodiment, the first transistor and the second transistor have the same width-to-length ratio.

[0012] In one embodiment, the temperature coefficient of the bias voltage is adjusted by configuring the number of finger / multiples of the first transistor and the second transistor, respectively.

[0013] In one embodiment, the first programmable current source includes a positive temperature coefficient current source or a negative temperature coefficient current source; the second programmable current source includes a positive temperature coefficient current source or a negative temperature coefficient current source; and the third, fourth, and fifth programmable current sources are all zero temperature coefficient programmable current sources.

[0014] In one embodiment, the first programmable current source, the second programmable current source, the third programmable current source, the fourth programmable current source, and the fifth programmable current source adjust the current of their respective branches according to their respective switching devices.

[0015] As described above, the bias voltage temperature coefficient adjustment circuit proposed in this invention has the following beneficial effects.

[0016] Based on the adjustment circuit provided in this application, the temperature coefficient of the bias voltage can be programmed, thereby ensuring that the drain-source voltage of the transistor in the tail current source array maintains the same trend as the overdrive voltage at different temperatures, thus ensuring that the transistor remains in the saturation region and guaranteeing chip performance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a differential pair and a Cascode current source.

[0018] Figure 2 This is a schematic diagram of the circuit structure of the bias voltage temperature coefficient adjustment circuit in one embodiment of this application.

[0019] Explanation of icon numbers:

[0020] CS1 - First programmable current source, CS2 - Second programmable current source, CS3 - Third programmable current source, CS4 - Fourth programmable current source, CS5 - Fifth programmable current source, R - On-chip resistor, Buffer1 - First buffer, Bffer2 - Second buffer, MN1 - First transistor, MN2 - Second transistor, MN3 - Third transistor, M1 - Fourth transistor, M2 - Fifth transistor, M5 - Sixth transistor, M4 - Seventh transistor, M3 - Eighth transistor. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] The inventor discovered through research that:

[0024] like Figure 1 As shown, transistors M3, M4, and M5 constitute a three-stage Cascode current source. The tail current source typically uses a zero-temperature coefficient current. Since mobility and threshold voltage have negative temperature coefficients, and without considering channel modulation effects and other factors, the mobility voltage decreases as temperature increases. From formula (1.1), the Vthreshold of transistor M3 can be obtained. DSAT As temperature increases, if V DS Does not change with temperature or with V DSAT If the trend of change is opposite, then the M3 transistor may enter the linear region, and the output impedance will also change, resulting in a decrease in the performance of the DAC.

[0025]

[0026] In view of the problems existing in the prior art, this application provides a bias voltage temperature coefficient adjustment circuit. The circuit of this application will be described in detail below with reference to specific embodiments.

[0027] Please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a bias voltage temperature coefficient adjustment circuit according to an embodiment of this application. The circuit includes: a first current branch for providing an adjustable first zero temperature coefficient current and a first node voltage; a voltage adjustment branch for providing a zero temperature coefficient voltage; and a second current branch for providing an adjustable second zero temperature coefficient current and generating a bias voltage based on the first node voltage and the zero temperature coefficient voltage. The temperature coefficient of the bias voltage is adjusted by the ratio of the first zero temperature coefficient current to the second zero temperature coefficient current.

[0028] In one embodiment, the voltage regulation branch includes a first programmable current source CS1, a second programmable current source CS2, and an on-chip resistor R; the input terminal of the first programmable current source CS1 is connected to the power supply voltage, and the output terminal is connected to one end of the on-chip resistor R as the output terminal of the voltage regulation branch; the other end of the on-chip resistor R is connected to the first node voltage and the input terminal of the second programmable current source CS2, respectively, and the output terminal of the second programmable current source CS2 is grounded.

[0029] In one embodiment, the first current branch includes a third programmable current source CS3 and a first transistor MN1. The input terminal of the third programmable current source CS3 is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the first transistor MN1 to output the first node voltage. The gate terminal and drain terminal of the first transistor MN1 are shorted, and the source terminal of the first transistor MN1 is grounded.

[0030] In one embodiment, the second current branch includes a fourth programmable current source CS4, a second transistor MN2, and a fifth programmable current source CS5. The input terminal of the fourth programmable current source CS4 is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the second transistor MN2. The gate terminal and drain terminal of the second transistor MN2 are shorted, and the gate terminal is connected to the output terminal of the voltage regulation branch. The source terminal of the second transistor MN2 is connected to the input terminal of the fifth programmable current source CS5 as the output terminal of the second current branch to output a bias voltage. The output terminal of the fifth programmable current source is grounded.

[0031] In one embodiment, the circuit further includes a first buffer Buffer1, the positive input terminal of which is connected to the output terminal of the second current branch, and the negative input terminal of the first buffer Buffer1 is shorted to the output terminal and then connected to the gate terminal of the second transistor MN2.

[0032] In one embodiment, the output of the second current branch is connected to the tail current source array through a second buffer Buffer1; the second buffer Buffer1 includes a comparator and a third transistor MN3; the positive input of the comparator is connected to the bias voltage, and the negative input is connected to the source of the third transistor MN3; the output of the comparator is connected to the gate of the third transistor MN3. The tail current source array includes a fourth transistor M1, a fifth transistor M2, a sixth transistor M5, a seventh transistor M4, and an eighth transistor M3. The drain of the fourth transistor M1 is connected to the output of the first current branch, and the gate of the fourth transistor M1 is connected to the source of the third transistor MN3. The source of the fourth transistor M1 is connected to the source of the fifth transistor M2 and the drain of the sixth transistor M5. The gate of the fifth transistor M2 is connected to the drain of the third transistor MN3, and the drain of the fifth transistor M2 is connected to the output of the voltage regulation branch. The gate of the sixth transistor M5 is connected to a preset first bias voltage, and the source of the sixth transistor M5 is connected to the drain of the seventh transistor M4. The gate of the seventh transistor M4 is connected to the gate of the third transistor MN3. The source of the seventh transistor M4 is connected to the drain of the eighth transistor M3. The gate of the eighth transistor M3 is connected to a preset second bias voltage, and the source of the eighth transistor M3 is grounded.

[0033] In one embodiment, the first programmable current source CS1 includes a positive temperature coefficient (PTAT) current source or a negative temperature coefficient (CTAT) current source; the second programmable current source CS2 includes a positive temperature coefficient current source or a negative temperature coefficient current source, and CS1 and CS2 must both be positive or negative temperature coefficient current sources; the third programmable current source CS3, the fourth programmable current source CS4, and the fifth programmable current source CS5 are all zero temperature coefficient programmable current sources. The zero temperature coefficient programmable bias current sources CS3, CS4, and CS5 are used to program the first zero temperature coefficient current I1 and the second zero temperature coefficient current I3 flowing through transistors MN1 and MN2, respectively. The currents flowing through transistors MN1 and MN2 are zero temperature coefficient currents with magnitudes I1 and I3, respectively. Switches S4, S5, and S6 are used to program current source CS3 to generate the zero temperature coefficient current I1, and switches S7, S8, and S9 are used to program current sources CS4 and CS5 to generate the zero temperature coefficient current I3. The CS1 and CS2 current sources are bias currents generated by dividing the on-chip / external reference voltage by the on-chip resistor R. Since the temperature coefficients of different types of resistors under different processes are different, the bias currents generated may be CTAT or PTAT currents. By programming CS1, CS2 and S3, different magnitudes of current I2 with temperature coefficients can be generated. Then, the current I2 is multiplied by the on-chip resistor R to generate a zero temperature coefficient voltage I2R, which is used to generate an absolute voltage drop to finely adjust the magnitude of the bias voltage.

[0034] The ratio of the drain current of MN2 to the drain current of MN1 is N = I3 / I1. N varies depending on the programming result, and different N values ​​correspond to different temperature coefficients of the bias voltage. MN1 and MN2 have the same width-to-length ratio (W / L). MN1 has a finger / multiple count, and MN2 has a finger / multiple count, which is b. The ratio of the finger / multiple count of MN2 to that of MN1 is Q = b / a. Q varies depending on the programming result, and different Q values ​​correspond to different temperature coefficients of the bias voltage. The gain of the first buffer (Buffer1) and the second buffer (Buffer2) is 1, and the voltage of Node D is V. GS1 The voltage of Node E is V. GS1 +I2R, the output voltage of Buffer1 is V GS1 +I²R, the source voltage of Node F is V GS1 +I2R-V GS2 The gate bias of MN3 is used to generate the bias voltage of M4, so the voltage and temperature coefficient of Node A also change with Node F.

[0035] Specifically, the finger / multiple design of MN1 is a, and the finger / multiple design of MN2 is b. The ratio of the number of finger / multiples in MN2 to the number of finger / multiples in MN1 is Q = b / a. The programmed current of MN1 is I1, and the programmed current of MN2 is I3. The ratio of the current of MN2 to the current of MN1 is N = I3 / I1. Simplifying formula (1.3) from formula (1.2) and removing the sign, we get formula (1.4). Since the mobility of MN1 and MN2 changes with temperature in the same way and is a negative temperature coefficient, when the temperature is T, V GS1 -V TH1 =A,V GS1 =A+V TH1 When the temperature changes by ΔT, ΔV GS1 =A + ΔA + ΔV TH1 A+ΔA is a positive number, V GS1 The change follows V TH1 Change, ΔV GS2 = (A + ΔA) * P + ΔV TH2 Threshold voltages V of MN1 and MN2 TH The change with temperature is the same, i.e., ΔV TH2 =ΔV TH1 When P = 1, ΔV GS1 and ΔV GS2 The change in amount is the same, according to the formula V GS1 +I2R-V GS2 +ΔV GS1 -ΔV GS2 It can be concluded that the generated voltage bias has a zero temperature coefficient. When P is less than 1, that is, when Q is greater than N, ΔV GS2 = (A + ΔA) * P + ΔV TH2 That is, |ΔV GS2 ∣<∣ΔV GS1 The resulting voltage bias has a positive temperature coefficient. When P is greater than 1, i.e., Q is less than N, ΔV GS2 = (A + ΔA) * P + ΔV TH2 That is, |ΔV GS2 |>|ΔV GS1 | represents a negative temperature coefficient. By programming the values ​​of N and Q, the magnitude of the temperature coefficient can be determined until the desired temperature coefficient is obtained.

[0036]

[0037]

[0038]

[0039] Based on the technical solutions of the above embodiments of this application, the present invention designs the temperature coefficient of the bias voltage to be programmable, thereby enabling the V of the transistor to... DS Maintains the same as V at different temperatures DSAT The change trends are the same, thus ensuring that the transistor remains in the saturation region to guarantee chip performance.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bias voltage temperature coefficient adjustment circuit, characterized in that, include: The first current branch is used to provide an adjustable first zero-temperature coefficient current and a first node voltage; The voltage regulation branch is used to provide zero temperature coefficient voltage; The second current branch is used to provide a second zero temperature coefficient current with adjustable magnitude, and to generate a bias voltage based on the first node voltage and the zero temperature coefficient voltage. The temperature coefficient of the bias voltage is adjusted by the ratio of the first zero temperature coefficient current to the second zero temperature coefficient current. The voltage regulation branch includes a first programmable current source, a second programmable current source, and an on-chip resistor. The input terminal of the first programmable current source is connected to the power supply voltage, and the output terminal is connected to one end of the on-chip resistor as the output terminal of the voltage regulation branch. The other end of the on-chip resistor is connected to the first node voltage and the input terminal of the second programmable current source, respectively, and the output terminal of the second programmable current source is grounded. The first current branch includes a third programmable current source and a first transistor. The input terminal of the third programmable current source is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the first transistor to output the first node voltage. The gate terminal and drain terminal of the first transistor are shorted, and the source terminal of the first transistor is grounded. The second current branch includes a fourth programmable current source, a second transistor, and a fifth programmable current source. The input terminal of the fourth programmable current source is connected to the power supply voltage, and the output terminal is connected to the drain terminal of the second transistor. The gate terminal and drain terminal of the second transistor are shorted, and the gate terminal is connected to the output terminal of the voltage regulation branch. The source terminal of the second transistor is connected to the input terminal of the fifth programmable current source as the output terminal of the second current branch to output a bias voltage. The output terminal of the fifth programmable current source is grounded.

2. The bias voltage temperature coefficient adjustment circuit according to claim 1, characterized in that, It also includes a first buffer, the positive input terminal of which is connected to the output terminal of the second current branch, and the negative input terminal of the first buffer is shorted to the output terminal and then connected to the gate terminal of the second transistor.

3. The bias voltage temperature coefficient adjustment circuit according to claim 2, characterized in that, The output of the second current branch is connected to the tail current source array through a second buffer; the second buffer includes a comparator and a third transistor; the positive input of the comparator is connected to the bias voltage, and the negative input is connected to the source of the third transistor; the output of the comparator is connected to the gate of the third transistor. The tail current source array includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The drain of the fourth transistor is connected to the output of the first current branch, the gate of the fourth transistor is connected to the source of the third transistor, the source of the fourth transistor is connected to the source of the fifth transistor and the drain of the sixth transistor, the gate of the fifth transistor is connected to the drain of the third transistor, and the drain of the fifth transistor is connected to the output of the voltage regulation branch. The gate of the sixth transistor is connected to a preset first bias voltage, the source of the sixth transistor is connected to the drain of the seventh transistor, the gate of the seventh transistor is connected to the gate of the third transistor, the source of the seventh transistor is connected to the drain of the eighth transistor, the gate of the eighth transistor is connected to a preset second bias voltage, and the source of the eighth transistor is grounded.

4. The bias voltage temperature coefficient adjustment circuit according to claim 1, characterized in that, The first transistor and the second transistor have the same width-to-length ratio.

5. The bias voltage temperature coefficient adjustment circuit according to claim 4, characterized in that, The temperature coefficient of the bias voltage can be adjusted by configuring the number of finger / multiples for the first transistor and the second transistor, respectively.

6. The bias voltage temperature coefficient adjustment circuit according to claim 1, characterized in that, The first programmable current source includes a positive temperature coefficient current source or a negative temperature coefficient current source; the second programmable current source includes a positive temperature coefficient current source or a negative temperature coefficient current source; the third, fourth and fifth programmable current sources are all zero temperature coefficient programmable current sources, wherein the first programmable current source and the second programmable current source are both positive temperature coefficient or both negative temperature coefficient.

7. The bias voltage temperature coefficient adjustment circuit according to claim 6, characterized in that, The first, second, third, fourth, and fifth programmable current sources adjust the current of their respective branches according to their respective switching devices.

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