Bandgap reference circuit and analog chip

Abstract

The application provides a band gap reference circuit and an analog chip, the band gap reference circuit comprising a positive temperature coefficient current generation module, a reference voltage generation module and an enable start control module, on the basis of generating a band gap reference voltage with zero temperature coefficient through the positive temperature coefficient current generation module and the reference voltage generation module, the first bias voltage output to the reference voltage generation module is improved through a negative feedback loop in the positive temperature coefficient current generation module, the small signal coefficient required to be amplified by the subsequent reference voltage generation module is reduced, and then the power supply rejection ratio of the band gap reference voltage is effectively optimized; meanwhile, the second bias voltage of the reference voltage generation module is improved through the diode connection of the MOS tube inside the reference voltage generation module, and the power supply rejection ratio of the band gap reference voltage is further optimized. In this way, without using an operational amplifier, the power supply rejection ratio of the band gap reference voltage VBG can be obviously improved without too much increase in circuit complexity and energy consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bandgap reference circuit and analog chip. Background Technology

[0002] Bandgap references are the most common way to provide bias voltages for circuits that are weakly dependent on temperature in all analog chips. They are widely used in almost all analog chips. Bandgap references have two important metrics: temperature drift coefficient and power supply rejection ratio (PSRR). In many designs, PSRR can be improved by introducing operational amplifiers, but this undoubtedly increases circuit complexity and power consumption. Without introducing operational amplifiers, it is difficult to achieve a good PSRR.

[0003] Therefore, there is an urgent need for a bandgap reference technology that does not require operational amplifiers, which can achieve a good power supply rejection ratio without significantly increasing circuit complexity and power consumption. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a bandgap reference technology solution that does not require operational amplifiers. The bandgap reference circuit is designed by combining a positive temperature coefficient current generation module, a reference voltage generation module, and an enable / startup control module. Based on the generation of a zero-temperature coefficient bandgap reference voltage by the positive temperature coefficient current generation module and the reference voltage generation module, the first bias voltage output to the reference voltage generation module is boosted through the negative feedback loop in the positive temperature coefficient current generation module. This makes the small-signal coefficient that the subsequent reference voltage generation module needs to amplify smaller, thereby effectively optimizing the power supply rejection ratio of the bandgap reference voltage. It eliminates the need for operational amplifiers and does not increase circuit complexity or power consumption.

[0005] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0006] A bandgap reference circuit, comprising:

[0007] Positive temperature coefficient current generation module, which generates positive temperature coefficient current;

[0008] A reference voltage generation module is connected to the positive temperature coefficient current generation module. It mirrors the positive temperature coefficient current, generates a positive temperature coefficient voltage based on the mirrored positive temperature coefficient current, and then superimposes the positive temperature coefficient voltage with the provided negative temperature coefficient voltage to obtain a bandgap reference voltage with zero temperature coefficient.

[0009] An enable start control module is connected to the positive temperature coefficient current generation module and the reference voltage generation module respectively, receives a first enable signal and a second enable signal, and performs enable start control on the positive temperature coefficient current generation module and the reference voltage generation module respectively under the control of the first enable signal and the second enable signal.

[0010] The temperature coefficient current generation module has a negative feedback loop and a positive feedback loop, and the absolute value of the loop gain of the negative feedback loop is greater than the absolute value of the loop gain of the positive feedback loop. The negative feedback loop is used to boost the first bias voltage provided to the reference voltage generation module to optimize the power supply rejection ratio of the bandgap reference voltage.

[0011] Optionally, the positive temperature coefficient current generation module includes a positive temperature coefficient current generation unit and a negative feedback unit. The positive temperature coefficient current generation unit generates the positive temperature coefficient current, and the negative feedback unit is connected to the positive temperature coefficient current generation unit to form the negative feedback loop.

[0012] Optionally, the positive temperature coefficient current generation unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode and a second diode, a first resistor, a first capacitor and a second capacitor.

[0013] The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the anode of the first diode, and the cathode of the first diode is grounded.

[0014] The source of the second PMOS transistor is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor is also connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, the source of the second NMOS transistor is connected to the anode of the second diode through the first resistor connected in series, and the cathode of the second diode is grounded.

[0015] The first terminal of the first capacitor is connected to the power supply voltage, the second terminal of the first capacitor is connected to the gate of the first PMOS transistor, the first terminal of the second capacitor is connected to the gate of the second NMOS transistor, and the second terminal of the second capacitor is connected to the drain of the second NMOS transistor.

[0016] Specifically, when the positive temperature coefficient current generation module is enabled, the positive temperature coefficient current is generated across the first resistor.

[0017] Optionally, the negative feedback unit includes a third PMOS transistor, a third NMOS transistor, and a third diode.

[0018] The source of the third PMOS transistor is connected to the power supply voltage, the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the third PMOS transistor is connected to its gate, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the second NMOS transistor, the source of the third NMOS transistor is connected to the anode of the third diode, and the cathode of the third diode is grounded.

[0019] When the positive temperature coefficient current generation module is enabled, the gate of the third PMOS transistor outputs the first bias voltage.

[0020] Optionally, the second bias voltage of the reference voltage generation module can be increased by using the diode connection of the MOS transistor inside the reference voltage generation module, so as to optimize the power supply rejection ratio of the bandgap reference voltage.

[0021] Optionally, the reference voltage generation module includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a second resistor, a fourth diode, and a fifth diode.

[0022] The source of the fourth PMOS transistor is connected to the power supply voltage, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, the source of the fourth NMOS transistor is connected to the anode of the fourth diode, and the cathode of the fourth diode is grounded.

[0023] The source of the sixth PMOS transistor is connected to the power supply voltage, the gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the seventh PMOS transistor is connected to the anode of the fifth diode via the second resistor connected in series, and the cathode of the fifth diode is grounded.

[0024] The fourth PMOS transistor is configured with a diode connection. When the reference voltage generation module is enabled, the gate of the fifth PMOS transistor outputs the second bias voltage, and the drain of the seventh PMOS transistor outputs the bandgap reference voltage.

[0025] Optionally, the first enable signal and the second enable signal are complementary. The enable start control module includes a first enable start control unit and a second enable start control unit. The first enable start control unit is connected to the positive temperature coefficient current generation module, and the second enable start control unit is connected to the reference voltage generation module. The first enable start control unit and the second enable start control unit respectively receive the first enable signal and the second enable signal. Under the control of the first enable signal and the second enable signal, the first enable start control unit performs enable start control on the positive temperature coefficient current generation module, and the second enable start control unit performs enable start control on the reference voltage generation module.

[0026] Optionally, the first enable / start control unit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor.

[0027] The source of the eighth PMOS transistor is connected to the power supply voltage, the gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second enable signal, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the seventh NMOS transistor is grounded, the drain of the ninth PMOS transistor is grounded, and the gate of the ninth PMOS transistor is connected to the drain of the eighth PMOS transistor.

[0028] The source of the tenth PMOS transistor is connected to the power supply voltage, the gate of the tenth PMOS transistor is connected to the first enable signal, the drain of the tenth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the second PMOS transistor is also connected to the source of the ninth PMOS transistor.

[0029] The source of the eleventh PMOS transistor is connected to the power supply voltage, the gate of the eleventh PMOS transistor is connected to the first enable signal, and the drain of the eleventh PMOS transistor is connected to the gate of the third PMOS transistor. The source of the twelfth PMOS transistor is connected to the power supply voltage, the gate of the twelfth PMOS transistor is connected to the first enable signal, and the drain of the twelfth PMOS transistor is connected to the gate of the third PMOS transistor. The source of the thirteenth PMOS transistor is connected to the power supply voltage, the gate of the thirteenth PMOS transistor is connected to the first enable signal, and the drain of the thirteenth PMOS transistor is connected to the gate of the third PMOS transistor.

[0030] The drain of the eighth NMOS transistor is connected to the gate of the second NMOS transistor, the gate of the eighth NMOS transistor is connected to the second enable signal, and the source of the eighth NMOS transistor is grounded. The drain of the ninth NMOS transistor is connected to the anode of the first diode, the gate of the ninth NMOS transistor is connected to the second enable signal, and the source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the anode of the second diode, the gate of the tenth NMOS transistor is connected to the second enable signal, and the source of the tenth NMOS transistor is grounded. The drain of the eleventh NMOS transistor is connected to the anode of the third diode, the gate of the eleventh NMOS transistor is connected to the second enable signal, and the source of the eleventh NMOS transistor is grounded.

[0031] Optionally, the second enable / start control unit includes a fourteenth PMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor.

[0032] The source of the fourteenth PMOS transistor is connected to the power supply voltage, the gate of the fourteenth PMOS transistor is connected to the first enable signal, and the drain of the fourteenth PMOS transistor is connected to the gate of the seventh PMOS transistor.

[0033] The source of the twelfth NMOS transistor is grounded, the drain of the twelfth NMOS transistor is connected to the anode of the fourth diode, the gate of the twelfth NMOS transistor is connected to the second enable signal, the drain of the thirteenth NMOS transistor is connected to the anode of the fifth diode, the gate of the thirteenth NMOS transistor is connected to the second enable signal, and the source of the thirteenth NMOS transistor is grounded.

[0034] An analog chip includes a bandgap reference circuit as described in any one of the above descriptions.

[0035] As described above, the bandgap reference circuit and analog chip provided by the present invention have at least the following beneficial effects:

[0036] A bandgap reference circuit is designed by combining a positive temperature coefficient current generation module, a reference voltage generation module, and an enable / start control module. Based on the generation of a zero-temperature coefficient bandgap reference voltage by the positive temperature coefficient current generation module and the reference voltage generation module, the first bias voltage output to the reference voltage generation module is boosted through the negative feedback loop in the positive temperature coefficient current generation module. This makes the small-signal coefficient that the subsequent reference voltage generation module needs to amplify smaller, thereby effectively optimizing the power supply rejection ratio of the bandgap reference voltage. Compared with the prior art, no operational amplifier is required, and the temperature coefficient and power supply rejection ratio of the bandgap reference voltage are reduced without increasing circuit complexity and power consumption. Attached Figure Description

[0037] Figure 1 The diagram shown is a circuit diagram of an existing op-amp-less bandgap reference circuit.

[0038] Figure 2 The diagram shown is a circuit diagram of the bandgap reference circuit in this invention.

[0039] Figure 3 Displayed as Figure 2 Circuit diagram of the positive temperature coefficient current generation module.

[0040] Figure 4 Displayed as Figure 1 Circuit diagram of the positive temperature coefficient current generation module. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0043] In detail, such as Figure 1 The diagram shows a prior art bandgap reference circuit without operational amplifiers. It includes a positive temperature coefficient current generation module composed of PMOS transistors P1-P2, NMOS transistors N1-N2, diodes D1-D2, and resistor R1, used to generate a positive temperature coefficient current. It also includes a reference voltage generation module composed of PMOS transistors P4-P7, NMOS transistor N4, diodes D4-D5, and resistor R2. The reference voltage generation module is connected to the positive temperature coefficient current generation module, mirrors the positive temperature coefficient current, generates a positive temperature coefficient voltage based on the mirrored positive temperature coefficient current, and then superimposes the positive temperature coefficient voltage with the provided negative temperature coefficient voltage to obtain a zero temperature coefficient bandgap reference voltage VBG.

[0044] At the same time, such as Figure 1 As shown, the bandgap reference circuit also includes an enable / start control module composed of PMOS transistors P8 to P14 and NMOS transistors N5 to N13. The enable / start control module is connected to the positive temperature coefficient current generation module and the reference voltage generation module respectively. It receives the first enable signal ENP and the second enable signal ENN. Under the control of the first enable signal ENP and the second enable signal ENN, it enables / starts the positive temperature coefficient current generation module and the reference voltage generation module respectively.

[0045] As described in the background section, the inventors discovered that existing technologies generally improve power supply rejection ratio by introducing operational amplifiers into bandgap reference circuits. However, this increases circuit complexity and power consumption. If operational amplifiers are not introduced, the first bias voltage Vout output by the positive temperature coefficient current generation module and the second bias voltage V2 generated inside the reference voltage generation module are too low, resulting in higher power supply rejection ratio in the circuit.

[0046] Based on this, the present invention proposes a bandgap reference technology solution that reduces the power supply rejection ratio (PSRR) without the need for operational amplifiers: A bandgap reference circuit is designed by combining a positive temperature coefficient (PTC) current generation module, a reference voltage generation module, and an enable / startup control module. Based on the generation of a zero-temperature coefficient bandgap reference voltage by the PTC current generation module and the reference voltage generation module, the first bias voltage output to the reference voltage generation module is boosted through a negative feedback loop in the PTC current generation module. This reduces the small-signal coefficient that the subsequent reference voltage generation module needs to amplify, thereby optimizing the PSRR of the bandgap reference voltage. Simultaneously, the second bias voltage of the reference voltage generation module is boosted by using a diode connection of the MOS transistor inside the reference voltage generation module, further optimizing the PSRR of the bandgap reference voltage.

[0047] First, such as Figure 2 As shown, the present invention proposes a bandgap reference circuit, which includes:

[0048] Positive temperature coefficient current generation module, which generates positive temperature coefficient current;

[0049] The reference voltage generation module is connected to the positive temperature coefficient current generation module. It mirrors the positive temperature coefficient current, generates a positive temperature coefficient voltage based on the mirrored positive temperature coefficient current, and then superimposes the positive temperature coefficient voltage with the provided negative temperature coefficient voltage to obtain the zero temperature coefficient bandgap reference voltage VBG.

[0050] The enable start control module is connected to the positive temperature coefficient current generation module and the reference voltage generation module respectively. It receives the first enable signal ENP and the second enable signal ENN. Under the control of the first enable signal ENP and the second enable signal ENN, it performs enable start control on the positive temperature coefficient current generation module and the reference voltage generation module respectively.

[0051] The temperature coefficient current generation module has a negative feedback loop and a positive feedback loop, and the absolute value of the loop gain of the negative feedback loop is greater than the absolute value of the loop gain of the positive feedback loop. The negative feedback loop is used to boost the first bias voltage Vout provided to the reference voltage generation module, so as to optimize the power supply rejection ratio of the bandgap reference voltage VBG.

[0052] In detail, such as Figure 2 As shown, the positive temperature coefficient current generation module includes a positive temperature coefficient current generation unit and a negative feedback unit. The positive temperature coefficient current generation unit generates a positive temperature coefficient current, and the negative feedback unit is connected to the positive temperature coefficient current generation unit to form a negative feedback loop.

[0053] More in detail, such as Figure 2 As shown, the positive temperature coefficient current generation unit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a first diode D1 and a second diode D2, a first resistor R1, a first capacitor C1 and a second capacitor C2.

[0054] The source of the first PMOS transistor P1 is connected to the power supply voltage VDD, the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, the gate of the first NMOS transistor N1 is connected to the drain of the first NMOS transistor N1, the source of the first NMOS transistor N1 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is grounded.

[0055] The source of the second PMOS transistor P2 is connected to the power supply voltage VDD, and the drain of the second PMOS transistor P2 is connected to the gate of the first PMOS transistor P1. The drain of the second PMOS transistor P2 is also connected to the drain of the second NMOS transistor N2, and the gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1. The source of the second NMOS transistor N2 is connected to the anode of the second diode D2 through a first resistor R1 in series, and the cathode of the second diode D2 is grounded.

[0056] The first terminal of the first capacitor C1 is connected to the power supply voltage VDD, and the second terminal of the first capacitor C1 is connected to the gate of the first PMOS transistor P1. The first terminal of the second capacitor C2 is connected to the gate of the second NMOS transistor N2, and the second terminal of the second capacitor C2 is connected to the drain of the second NMOS transistor N2.

[0057] When the positive temperature coefficient current generation module is enabled, a positive temperature coefficient current is generated across the first resistor R1.

[0058] More in detail, such as Figure 2 As shown, the negative feedback unit includes a third PMOS transistor P3, a third NMOS transistor N3, and a third diode D3.

[0059] The source of the third PMOS transistor P3 is connected to the power supply voltage VDD. The gate of the third PMOS transistor P3 is connected to the gate of the second PMOS transistor P2. The drain of the third PMOS transistor P3 is connected to its gate. The drain of the third PMOS transistor P3 is connected to the drain of the third NMOS transistor N3. The gate of the third NMOS transistor N3 is connected to the gate of the second NMOS transistor N2. The source of the third NMOS transistor N3 is connected to the anode of the third diode D3. The cathode of the third diode D3 is grounded.

[0060] When the positive temperature coefficient current generation module is enabled, the gate of the third PMOS transistor P3 outputs the first bias voltage Vout.

[0061] In detail, such as Figure 2 As shown, by using the diode connection of the internal MOS transistor (i.e., the fourth PMOS transistor P4) of the reference voltage generation module, the second bias voltage V2 of the reference voltage generation module is increased to optimize the power supply rejection ratio of the bandgap reference voltage VBG.

[0062] More in detail, such as Figure 2 As shown, the reference voltage generation module includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a fourth NMOS transistor N4, a second resistor RR2, a fourth diode D4, and a fifth diode D5.

[0063] The source of the fourth PMOS transistor P4 is connected to the power supply voltage VDD. The gate of the fourth PMOS transistor P4 is connected to the drain of the fourth PMOS transistor P4. The drain of the fourth PMOS transistor P4 is connected to the source of the fifth PMOS transistor P5. The gate of the fifth PMOS transistor P5 is connected to the drain of the fifth PMOS transistor P5. The drain of the fifth PMOS transistor P5 is connected to the drain of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is connected to the gate of the second NMOS transistor N2. The source of the fourth NMOS transistor N4 is connected to the anode of the fourth diode D4. The cathode of the fourth diode D4 is grounded.

[0064] The source of the sixth PMOS transistor P6 is connected to the power supply voltage VDD. The gate of the sixth PMOS transistor P6 is connected to the gate of the third PMOS transistor P3. The drain of the sixth PMOS transistor P6 is connected to the source of the seventh PMOS transistor P7. The gate of the seventh PMOS transistor P7 is connected to the gate of the fifth PMOS transistor P5. The drain of the seventh PMOS transistor P7 is connected to the anode of the fifth diode D5 via a second resistor R2 connected in series. The cathode of the fifth diode D5 is grounded.

[0065] Among them, the fourth PMOS transistor P4 is set in a diode configuration. When the reference voltage generation module is enabled, the gate of the fifth PMOS transistor P5 outputs the second bias voltage V2, and the drain of the seventh PMOS transistor P7 outputs the bandgap reference voltage VBG.

[0066] In detail, such as Figure 2 As shown, the first enable signal ENP and the second enable signal ENN are complementary. The enable start control module includes a first enable start control unit and a second enable start control unit. The first enable start control unit is connected to the positive temperature coefficient current generation module, and the second enable start control unit is connected to the reference voltage generation module. The first enable start control unit and the second enable start control unit respectively receive the first enable signal ENP and the second enable signal ENN. Under the control of the first enable signal ENP and the second enable signal ENN, the first enable start control unit performs enable start control on the positive temperature coefficient current generation module, and the second enable start control unit performs enable start control on the reference voltage generation module.

[0067] More in detail, such as Figure 2 As shown, the first enable / start control unit includes the eighth PMOS transistor P8, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11.

[0068] The source of the eighth PMOS transistor P8 is connected to the power supply voltage VDD. The gate of the eighth PMOS transistor P8 is connected to the gate of the third PMOS transistor P3. The drain of the eighth PMOS transistor P8 is connected to the drain of the fifth NMOS transistor N5. The gate of the fifth NMOS transistor N5 is connected to the second enable signal ENN. The source of the fifth NMOS transistor N5 is connected to the drain of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is connected to the gate of the fifth NMOS transistor N5. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 is connected to the gate of the fifth NMOS transistor N5. The source of the seventh NMOS transistor N7 is grounded. The drain of the ninth PMOS transistor P9 is grounded. The gate of the ninth PMOS transistor P9 is connected to the drain of the eighth PMOS transistor P8.

[0069] The source of the tenth PMOS transistor P10 is connected to the power supply voltage VDD, the gate of the tenth PMOS transistor P10 is connected to the first enable signal ENP, the drain of the tenth PMOS transistor P10 is connected to the drain of the second PMOS transistor P2, and the drain of the second PMOS transistor P2 is also connected to the source of the ninth PMOS transistor P9.

[0070] The source of the eleventh PMOS transistor P11 is connected to the power supply voltage VDD, and its gate is connected to the first enable signal ENP. The drain of the eleventh PMOS transistor P11 is connected to the gate of the third PMOS transistor P3. The source of the twelfth PMOS transistor P12 is connected to the power supply voltage VDD, and its gate is connected to the first enable signal ENP. The drain of the twelfth PMOS transistor P12 is connected to the gate of the third PMOS transistor P3. The source of the thirteenth PMOS transistor P13 is connected to the power supply voltage VDD, and its gate is connected to the first enable signal ENP. The drain of the thirteenth PMOS transistor P13 is connected to the gate of the third PMOS transistor P3.

[0071] The drain of the eighth NMOS transistor N8 is connected to the gate of the second NMOS transistor N2. The gate of the eighth NMOS transistor N8 is connected to the second enable signal ENN. The source of the eighth NMOS transistor N8 is grounded. The drain of the ninth NMOS transistor N9 is connected to the anode of the first diode D1. The gate of the ninth NMOS transistor N9 is connected to the second enable signal ENN. The source of the ninth NMOS transistor N9 is grounded. The drain of the tenth NMOS transistor N10 is connected to the anode of the second diode D2. The gate of the tenth NMOS transistor N10 is connected to the second enable signal ENN. The source of the tenth NMOS transistor N10 is grounded. The drain of the eleventh NMOS transistor N11 is connected to the anode of the third diode D3. The gate of the eleventh NMOS transistor N11 is connected to the second enable signal ENN. The source of the eleventh NMOS transistor N11 is grounded.

[0072] More in detail, such as Figure 2As shown, the second enable / start control unit includes the fourteenth PMOS transistor P14, the twelfth NMOS transistor N12, and the thirteenth NMOS transistor N13.

[0073] The source of the fourteenth PMOS transistor P14 is connected to the power supply voltage VDD, the gate of the fourteenth PMOS transistor P14 is connected to the first enable signal ENP, and the drain of the fourteenth PMOS transistor P14 is connected to the gate of the seventh PMOS transistor P7.

[0074] The source of the twelfth NMOS transistor N12 is grounded, the drain of the twelfth NMOS transistor N12 is connected to the anode of the fourth diode D4, and the gate of the twelfth NMOS transistor N12 is connected to the second enable signal ENN. The drain of the thirteenth NMOS transistor N13 is connected to the anode of the fifth diode D5, the gate of the thirteenth NMOS transistor N13 is connected to the second enable signal ENN, and the source of the thirteenth NMOS transistor N13 is grounded.

[0075] More in detail, such as Figure 2 The working principle of the bandgap reference circuit shown is analyzed as follows.

[0076] 1) When the first enable signal ENP is 0 and the second enable signal ENN is 1, the gate voltage of all PMOS transistors in the positive temperature coefficient current generation module and the reference voltage generation module is pulled up to the power supply voltage VDD, and the gate voltage of all NMOS transistors in the positive temperature coefficient current generation module and the reference voltage generation module is pulled down to ground, so that the positive temperature coefficient current generation module and the reference voltage generation module are turned off and stopped respectively, and the output bandgap reference voltage VBG is pulled down to ground.

[0077] 2) When the first enable signal ENP is 1 and the second enable signal ENN is 0, the positive temperature coefficient current generation module and the reference voltage generation module are enabled and started respectively, the bandgap reference voltage VBG is pulled up, and the zero temperature coefficient bandgap reference voltage VBG is output.

[0078] Specifically, when the positive temperature coefficient current generation module is enabled, the change of the gate-source voltage of the second NMOS transistor N2 with temperature is ignored. The gate voltage of the second NMOS transistor N2 is the power supply voltage VDD, so that the source voltage of the second NMOS transistor N2 hardly changes with temperature. The forward conduction voltage drop of the second diode D2 has a negative temperature coefficient, which makes the voltage across the first resistor R1 have a positive temperature coefficient, thereby generating a positive temperature coefficient current across the first resistor R1.

[0079] The second NMOS transistor N2 and the fourth NMOS transistor N4 form a current mirror, and the fifth PMOS transistor P5 and the seventh PMOS transistor P7 form a current mirror, mirroring the positive temperature coefficient current on the first resistor R1 to the branch where the seventh PMOS transistor P7 is located. The mirrored positive temperature coefficient current flows through the second resistor R2. Based on the current-to-voltage conversion effect of the second resistor R2, a positive temperature coefficient voltage is obtained across the second resistor R2. Meanwhile, the forward voltage drop of the fifth diode D5 has a negative temperature coefficient. Through the adjustment and design of the circuit parameters, based on the superposition of the voltage across the second resistor R2 and the voltage across the fifth diode D5, a zero temperature coefficient bandgap reference voltage VBG is obtained at the drain of the seventh PMOS transistor P7.

[0080] At this point, for the positive temperature coefficient current generation module, compared to the positive temperature coefficient current generation circuit in the traditional WIDLAR bandgap reference, the positive temperature coefficient current generation module of this invention adds an extra branch, such as... Figures 3-4 As shown, this results in a negative feedback loop in the entire circuit. Figure 3 The loop on the right), a positive feedback loop ( Figure 3 (The loop on the left), and the absolute value of the loop gain of the negative feedback loop is larger. For the positive temperature coefficient current generation module, the following equation can be listed:

[0081]

[0082]

[0083]

[0084] Let g m =10 -5 A / V, R1=10KΩ, r o =10MΩ is helpful for estimating the final result.

[0085] Finally obtained in Among them, v dd The term refers to the small signal voltage. Node V1 corresponds to the drain of the fourth PMOS transistor P4, and node V2 corresponds to the drain and gate of the fifth PMOS transistor P5.

[0086] By inputting the relevant data, the first bias voltage V can be obtained. out Approximately 0.99v dd In the subsequent reference voltage generation module, there is 0.01V. dd The signal needs to be amplified, here is (v dd -V out ) / v dd = -40dB.

[0087] For example Figure 1 Or such as Figure 4 The conventional WIDLAR bandgap circuit shown can be represented by the following circuit equations:

[0088]

[0089]

[0090] Finally obtained in

[0091] After inputting the relevant data, the first bias voltage V can be obtained. out Approximately 0.972V dd In the subsequent reference voltage generation module, there is 0.028V. dd The signal needs to be amplified, here is (v dd -V out ) / v dd = -31dB.

[0092] Therefore, it is estimated that the positive temperature coefficient current generation module of the present invention can improve the power supply rejection ratio of the bandgap reference voltage VBG by at least 10dB.

[0093] Meanwhile, the reference voltage generation module of this invention adopts a common-source cascode output stage structure. However, compared with many traditional common-source cascode structures, this invention can achieve better optimization of the power supply rejection ratio in the output stage. The following equations can be derived for the reference voltage generation module:

[0094]

[0095]

[0096] Finally, we can obtain the result V2 = k × v dd , Slightly less than 1. Substituting the previously estimated data, the small-signal voltage at this point is approximately 0.98V. dd Next, consider node V3 (i.e., the drain of the sixth PMOS transistor P6). The small-signal voltage at this node is determined by the first bias voltage Vout and the second bias voltage V2. Analysis shows that the small-signal expression for this point is: Since the small-signal current flowing through the sixth PMOS transistor P6 can reflect the entire circuit's voltage at the bandgap reference voltage VBG, it is related to v. dd The gain of the small-signal expression.

[0097] The calculation formula for this node can be viewed as consisting of two parts, both of which are positive numbers. Adjusting g...mp9 This can make the small-signal voltage at that point greater than v. dd Slightly smaller (the width-to-length ratio of the fourth PMOS transistor P4 and the sixth PMOS transistor P6 in the circuit is much larger than that of the fifth PMOS transistor P5 and the seventh PMOS transistor P7), in a sense, reduces the current r flowing through the sixth PMOS transistor P6. ds The reduced current decreases the gain coefficient at the VBG node of the bandgap reference voltage, which in turn reduces the power supply rejection ratio (PSRR) and improves the circuit's PSRR.

[0098] Compared to the traditional cascode output stage, the key point of this invention is that the small-signal voltage of the second bias voltage V2 is larger than that of the traditional cascode output stage, thereby further improving the power supply rejection ratio of the entire circuit.

[0099] It should be noted that, in Figure 1 In the above, the second bias voltage V2 is affected by small signals on the power supply voltage VDD from two sources: one is the first bias voltage Vout, and the other is the signal received by the gate of the fourth NMOS transistor N4. Based on observation, the latter can be optimized. The optimization method is as follows: Figure 2 As shown, replacing the fourth PMOS transistor P4 with a diode connection reduces the output impedance of the drain of the fifth PMOS transistor P5, thereby reducing the signal strength and further improving the power supply rejection ratio.

[0100] Based on the above analysis, this invention designs a bandgap reference circuit by combining a positive temperature coefficient current generation module, a reference voltage generation module, and an enable / startup control module. After generating a zero-temperature coefficient bandgap reference voltage through the positive temperature coefficient current generation module and the reference voltage generation module, the negative feedback loop in the positive temperature coefficient current generation module boosts the first bias voltage output to the reference voltage generation module, reducing the small-signal coefficient that the subsequent reference voltage generation module needs to amplify, thereby effectively optimizing the power supply rejection ratio (PSRR) of the bandgap reference voltage. Simultaneously, by using a diode connection for the MOSFET inside the reference voltage generation module, the second bias voltage of the reference voltage generation module is increased, further optimizing the PSRR of the bandgap reference voltage. Thus, without using operational amplifiers, and without significantly increasing circuit complexity and power consumption, the PSRR of the bandgap reference voltage VBG can be significantly improved.

[0101] In addition, the present invention also provides an analog chip comprising the above-described bandgap reference circuit.

[0102] It should be noted that, based on the advantages of the above-mentioned bandgap reference circuit, such as zero temperature coefficient and high power supply rejection ratio, when the above-mentioned bandgap reference circuit is applied to analog chips, it can effectively improve the stability and reliability of the bandgap reference voltage and the corresponding functional circuit, thereby improving the stability and reliability of the analog chip, and can be widely used in analog integrated circuit chips.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bandgap reference circuit, characterized in that, include: Positive temperature coefficient current generation module, which generates positive temperature coefficient current; A reference voltage generation module is connected to the positive temperature coefficient current generation module. It mirrors the positive temperature coefficient current, generates a positive temperature coefficient voltage based on the mirrored positive temperature coefficient current, and then superimposes the positive temperature coefficient voltage with the provided negative temperature coefficient voltage to obtain a bandgap reference voltage with zero temperature coefficient. An enable start control module is connected to the positive temperature coefficient current generation module and the reference voltage generation module respectively, receives a first enable signal and a second enable signal, and performs enable start control on the positive temperature coefficient current generation module and the reference voltage generation module respectively under the control of the first enable signal and the second enable signal. The positive temperature coefficient current generation module has a negative feedback loop and a positive feedback loop, and the absolute value of the loop gain of the negative feedback loop is greater than the absolute value of the loop gain of the positive feedback loop. The negative feedback loop is used to boost the first bias voltage provided to the reference voltage generation module to optimize the power supply rejection ratio of the bandgap reference voltage. The positive temperature coefficient current generation module includes a positive temperature coefficient current generation unit and a negative feedback unit. The positive temperature coefficient current generation unit generates the positive temperature coefficient current, and the negative feedback unit is connected to the positive temperature coefficient current generation unit to form the negative feedback loop. The positive temperature coefficient current generation unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode and a second diode, a first resistor, a first capacitor and a second capacitor. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is connected to the anode of the first diode, and the cathode of the first diode is grounded. The source of the second PMOS transistor is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor is also connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, the source of the second NMOS transistor is connected to the anode of the second diode through the first resistor connected in series, and the cathode of the second diode is grounded. The first terminal of the first capacitor is connected to the power supply voltage, the second terminal of the first capacitor is connected to the gate of the first PMOS transistor, the first terminal of the second capacitor is connected to the gate of the second NMOS transistor, and the second terminal of the second capacitor is connected to the drain of the second NMOS transistor. When the positive temperature coefficient current generation module is enabled, the positive temperature coefficient current is generated across the first resistor. The negative feedback unit includes a third PMOS transistor, a third NMOS transistor, and a third diode. The source of the third PMOS transistor is connected to the power supply voltage, the gate of the third PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the third PMOS transistor is connected to its gate, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the second NMOS transistor, the source of the third NMOS transistor is connected to the anode of the third diode, and the cathode of the third diode is grounded. When the positive temperature coefficient current generation module is enabled, the gate of the third PMOS transistor outputs the first bias voltage. The reference voltage generation module includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fourth NMOS transistor, a second resistor, a fourth diode, and a fifth diode. The source of the fourth PMOS transistor is connected to the power supply voltage, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, the source of the fourth NMOS transistor is connected to the anode of the fourth diode, and the cathode of the fourth diode is grounded. The source of the sixth PMOS transistor is connected to the power supply voltage, the gate of the sixth PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the seventh PMOS transistor is connected to the anode of the fifth diode via the second resistor connected in series, and the cathode of the fifth diode is grounded. The fourth PMOS transistor is configured with a diode connection. When the reference voltage generation module is enabled, the gate of the fifth PMOS transistor outputs a second bias voltage, and the drain of the seventh PMOS transistor outputs the bandgap reference voltage.

2. The bandgap reference circuit according to claim 1, characterized in that, By using the diode connection of the MOS transistor inside the reference voltage generation module, the second bias voltage of the reference voltage generation module is increased to optimize the power supply rejection ratio of the bandgap reference voltage.

3. The bandgap reference circuit according to claim 1, characterized in that, The first enable signal and the second enable signal are complementary. The enable start control module includes a first enable start control unit and a second enable start control unit. The first enable start control unit is connected to the positive temperature coefficient current generation module, and the second enable start control unit is connected to the reference voltage generation module. The first enable start control unit and the second enable start control unit respectively receive the first enable signal and the second enable signal. Under the control of the first enable signal and the second enable signal, the first enable start control unit performs enable start control on the positive temperature coefficient current generation module, and the second enable start control unit performs enable start control on the reference voltage generation module.

4. The bandgap reference circuit according to claim 3, characterized in that, The first enable / start control unit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor. The source of the eighth PMOS transistor is connected to the power supply voltage, the gate of the eighth PMOS transistor is connected to the gate of the third PMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second enable signal, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the seventh NMOS transistor is grounded, the drain of the ninth PMOS transistor is grounded, and the gate of the ninth PMOS transistor is connected to the drain of the eighth PMOS transistor. The source of the tenth PMOS transistor is connected to the power supply voltage, the gate of the tenth PMOS transistor is connected to the first enable signal, the drain of the tenth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain of the second PMOS transistor is also connected to the source of the ninth PMOS transistor. The source of the eleventh PMOS transistor is connected to the power supply voltage, the gate of the eleventh PMOS transistor is connected to the first enable signal, and the drain of the eleventh PMOS transistor is connected to the gate of the third PMOS transistor. The source of the twelfth PMOS transistor is connected to the power supply voltage, the gate of the twelfth PMOS transistor is connected to the first enable signal, and the drain of the twelfth PMOS transistor is connected to the gate of the third PMOS transistor. The source of the thirteenth PMOS transistor is connected to the power supply voltage, the gate of the thirteenth PMOS transistor is connected to the first enable signal, and the drain of the thirteenth PMOS transistor is connected to the gate of the third PMOS transistor. The drain of the eighth NMOS transistor is connected to the gate of the second NMOS transistor, the gate of the eighth NMOS transistor is connected to the second enable signal, and the source of the eighth NMOS transistor is grounded. The drain of the ninth NMOS transistor is connected to the anode of the first diode, the gate of the ninth NMOS transistor is connected to the second enable signal, and the source of the ninth NMOS transistor is grounded. The drain of the tenth NMOS transistor is connected to the anode of the second diode, the gate of the tenth NMOS transistor is connected to the second enable signal, and the source of the tenth NMOS transistor is grounded. The drain of the eleventh NMOS transistor is connected to the anode of the third diode, the gate of the eleventh NMOS transistor is connected to the second enable signal, and the source of the eleventh NMOS transistor is grounded.

5. The bandgap reference circuit according to claim 3, characterized in that, The second enable / start control unit includes a fourteenth PMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor. The source of the fourteenth PMOS transistor is connected to the power supply voltage, the gate of the fourteenth PMOS transistor is connected to the first enable signal, and the drain of the fourteenth PMOS transistor is connected to the gate of the seventh PMOS transistor. The source of the twelfth NMOS transistor is grounded, the drain of the twelfth NMOS transistor is connected to the anode of the fourth diode, the gate of the twelfth NMOS transistor is connected to the second enable signal, the drain of the thirteenth NMOS transistor is connected to the anode of the fifth diode, the gate of the thirteenth NMOS transistor is connected to the second enable signal, and the source of the thirteenth NMOS transistor is grounded.

6. An analog chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-5.

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