Method and device for detecting snapshot circuit burrs in a fully digital phase-locked loop

Abstract

The present invention discloses a method and device for detecting burrs in a snapshot circuit in a fully digital phase-locked loop. By adding an additional delay detection unit to a delay-to-digital converter circuit, the snapshot circuit is detected, thereby identifying whether the current phase difference is erroneous information, and then judging whether the snapshot circuit generates burrs. The present invention belongs to the technical field of fully digital phase-locked loops, and can detect burrs generated by a snapshot circuit in a fully digital phase-locked loop when a high-speed clock is used to sample a reference clock, thereby avoiding inputting an erroneous phase difference into the fully digital phase-locked loop.

Description

Technical Field

[0001] The invention belongs to the technical field of full digital phase locked loops, and in particular relates to a method and a device for detecting snapshot circuit burrs in a full digital phase locked loop. Background Art

[0002] In a fully digital phase-locked loop, a time-to-digital converter (TDC) including a snapshot circuit (SNAPSHOT) can effectively save power consumption and is therefore widely used. In the snapshot circuit, the frequency of the edge of the oscillator clock signal of the oscillator is equal to the operating frequency of the reference clock, so the clock frequency input to the delay-to-digital converter is equal to the operating frequency of the reference clock, which greatly reduces power consumption compared to a delay-to-digital converter that does not use a snapshot circuit. When the snapshot circuit uses a high-speed clock to sample the reference clock, it is easy to generate glitches due to process, voltage, temperature (PVT) fluctuations.

[0003] In the snapshot circuit, the principle of glitch generation is as follows: when the rising edge of the reference clock signal and the falling edge of the oscillator clock signal are too close, the sampling clock signal will generate a narrow pulse glitch, and the delayed reference clock signal logic cannot recognize the narrow sampling clock signal, and the rising edge of the delayed reference clock signal will slide to the next edge.

[0004] When using a delay-to-digital converter including a snapshot circuit, the phase detection range of the delay-to-digital converter is limited for the purpose of saving power and area. The burrs of the snapshot circuit may cause the input phase difference of the delay-to-digital converter to exceed the phase detection range of the delay-to-digital converter, thereby causing the delay-to-digital converter to output a full-scale phase difference. After the wrong phase difference is injected into the locked loop, the loop performance will be deteriorated, and the impact of the burrs cannot be avoided by initial correction. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide a method and device for detecting burrs in a snapshot circuit in a fully digital phase-locked loop. By adding an additional delay detection unit to a delay-to-digital converter circuit, the snapshot circuit can be detected, thereby identifying whether the current phase difference is erroneous information, and then judging whether the snapshot circuit generates burrs.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] A method for detecting a glitch in a snapshot circuit in a fully digital phase-locked loop, wherein the snapshot circuit receives a reference clock signal and an oscillator clock signal and outputs a snapshot clock signal to a delay-to-digital converter, the method comprising:

[0008] Obtaining an output signal of the delay-to-digital converter;

[0009] detecting a phase of the output signal;

[0010] Whether a glitch occurs is determined based on the detected phase value. If the detected phase value reaches a preset threshold, it is determined that a glitch occurs; if the detected phase value does not reach the preset threshold, it is determined that no glitch occurs.

[0011] Furthermore, the method comprises:

[0012] The output signal is phase detected by expanding the original detection interval of the delay-to-digital converter by adding an additional glitch detection interval, wherein the glitch detection interval at least covers the phase change between the reference clock signal and the oscillator clock signal.

[0013] Furthermore, a delay unit of a preset length is included between the additional burr detection interval and the original detection interval of the delay-to-digital converter.

[0014] On the other hand, the present invention also provides a device for detecting burrs in a snapshot circuit in a fully digital phase-locked loop, wherein the snapshot circuit receives a reference clock signal and an oscillator clock signal, and outputs a snapshot clock signal to a delay-to-digital converter, and the device comprises:

[0015] A signal acquisition module, the signal acquisition module acquires the output signal of the delay-to-digital converter;

[0016] A phase detection module, wherein the phase detection module detects the phase of the output signal;

[0017] The burr judgment module judges whether a burr occurs according to the detected phase value. If the detected phase value reaches a preset threshold, it is judged that a burr occurs; if the detected phase value does not reach the preset threshold, it is judged that no burr occurs.

[0018] Furthermore, the phase detection module expands the original detection interval of the delay-to-digital converter by adding an additional glitch detection interval, and performs phase detection on the output signal, and the glitch detection interval at least covers the phase change between the reference clock signal and the oscillator clock signal.

[0019] Furthermore, a delay unit of a preset length is included between the additional burr detection interval and the original detection interval of the delay-to-digital converter.

[0020] The beneficial effects of the present invention are:

[0021] (1) The present invention provides a method and device for detecting snapshot circuit glitches in a fully digital phase-locked loop, which can detect the snapshot circuit in the fully digital phase-locked loop and the glitches generated when a high-speed clock is used to sample a reference clock, thereby avoiding an incorrect phase difference input to the fully digital phase-locked loop.

[0022] (2) The present invention can detect the specific phase of the burr by means of an additional burr detection device without changing the structure of the delay-to-digital converter, thereby providing sufficient data support for the subsequent adjustment of the delay signal of the input snapshot circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the core sampling portion of the snapshot circuit of an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the phase detection range of a conventional delay-to-digital converter;

[0025] Figure 3 is a schematic diagram of a fully digital phase-locked loop with a snapshot circuit according to an embodiment of the present invention;

[0026] Figure 4 It is a schematic diagram of the burr detection principle of an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work shall fall within the scope of protection of the present invention.

[0029] When using a delay-to-digital converter including a snapshot circuit, the phase detection range of the delay-to-digital converter is limited for the purpose of saving power and area. The burrs of the snapshot circuit may cause the input phase difference of the TDC to exceed the phase detection range of the TDC, causing the delay-to-digital converter to output a full-scale phase difference. After the wrong phase difference is injected into the locked loop, the loop performance will be deteriorated, and the impact of the burrs cannot be avoided by initial correction.

[0030] In order to solve the above technical problems, the following embodiments of a method and device for detecting snapshot circuit glitches in a fully digital phase-locked loop of the present invention are proposed.

[0031] Example 1

[0032] Reference Figure 1 ,like Figure 1 Shown is a schematic diagram of the core sampling portion of the snapshot circuit of this embodiment. The snapshot circuit uses the oscillator clock signal of the oscillator to compare the position of the first high-frequency clock falling edge after the rising edge of the reference clock signal, and uses the falling edge to generate a snapshot clock signal. The snapshot clock signal is input into the delay-to-digital converter.

[0033] If the oscillator clock signal and the reference clock signal are too close, the pulse output after logic sampling will become narrower. If the pulse is too narrow, it will produce glitches, and the pulse time does not meet the setup time / hold time requirements of the subsequent DFF (D-type flip-flop), so it will not be recognized by the subsequent DFF. Therefore, the snapshot clock signal can only be recognized at the second falling edge of the oscillator clock signal, so the rising edge of the snapshot clock signal is delayed by one oscillator clock signal cycle than expected.

[0034] Reference Figure 2 ,like Figure 2 The figure shows a schematic diagram of the phase-detection range of a conventional delay-to-digital converter. The phase-detection range of a conventional delay-to-digital converter is limited. In order to save area and power consumption, the entire delay-to-digital converter phase-detection range T FS =N*△ is less than one oscillator clock signal period. So, if Figure 1 If the snapshot circuit has a glitch, the phase difference of the input signal exceeds a TDC range, which is an erroneous phase signal. This is because the actual signal input to the delay-to-digital converter should be a signal one oscillator clock signal cycle earlier.

[0035] Reference Figure 3 ,like Figure 3 The figure shows a schematic diagram of a fully digital phase-locked loop with a snapshot circuit in an embodiment. After the fully digital phase-locked loop is locked, when a phase edge of the reference clock signal of the snapshot circuit and the oscillator clock signal is too close, a glitch will be generated. This embodiment uses a glitch detection device to receive the signal output by the delay-to-digital converter, and by adding an additional glitch detection interval, the original detection interval of the delay-to-digital converter is expanded to perform phase detection on the output signal.

[0036] During normal operation, the phase difference between the reference clock signal and the oscillator clock signal is relatively small, and the interval corresponding to the output phase of the TDC is the normal detection interval of the TDC; when glitches occur, the phase relationship between the reference clock signal and the oscillator clock signal detected by the delay-to-digital converter will increase significantly, and the oscillator clock signal will increase a significant delay relative to the reference clock signal, which will cause the glitch detection interval to detect abnormal output values. Therefore, it is only necessary to add a delay detection unit that can completely cover the phase changes of the reference clock signal and the oscillator clock signal after the original normal detection interval of the delay-to-digital converter as the glitch detection interval, so that the glitches occurring in the loop can be detected.

[0037] Reference Figure 4 ,like Figure 4 The figure is a schematic diagram of the glitch detection principle of this embodiment. The delay-to-digital converter original detection interval in the figure is the original detection interval of the delay-to-digital converter, and the delay-to-digital converter outputs a normal Dout signal within the interval. When a glitch occurs, since the resolution of the glitch detection interval does not need to be divided as finely as the delay-to-digital converter working interval, it only needs to ensure that it can cover possible snapshot clock signal changes. Therefore, the glitch detection interval in this embodiment adopts a design of 10 delay resolution of the delay-to-digital converter.

[0038] As an implementation mode, this embodiment further expands the working range of the delay-to-digital converter through an interval delay unit, ensuring that after delaying an interval delay unit, plus the burr detection interval, the detection signal can be completely covered.

[0039] The present embodiment provides a method and device for detecting burrs in a snapshot circuit in a fully digital phase-locked loop, which can detect the burrs generated by the snapshot circuit in the fully digital phase-locked loop when the reference clock is sampled using a high-speed clock, thereby avoiding inputting an incorrect phase difference into the fully digital phase-locked loop. The present embodiment can detect the specific phase of the burr through an additionally provided burr detection device without changing the structure of the delay-to-digital converter, thereby providing sufficient data support for the subsequent adjustment of the delay signal of the input snapshot circuit.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting burrs in a snapshot circuit in a fully digital phase-locked loop, wherein the snapshot circuit receives a reference clock signal and an oscillator clock signal and outputs a snapshot clock signal to a delay-to-digital converter, characterized in that: The method comprises: Obtaining an output signal of the delay-to-digital converter; By adding an additional glitch detection interval, the original detection interval of the delay-to-digital converter is expanded to detect the phase of the output signal, and the glitch detection interval at least covers the phase change between the reference clock signal and the oscillator clock signal; Whether a glitch occurs is determined based on the detected phase value. If the detected phase value reaches a preset threshold, it is determined that a glitch occurs; if the detected phase value does not reach the preset threshold, it is determined that no glitch occurs.

2. The method for detecting snapshot circuit glitches in a fully digital phase-locked loop according to claim 1, characterized in that: A delay unit with a preset length is also included between the additional burr detection interval and the original detection interval of the delay-to-digital converter.

3. A device for detecting burrs in a snapshot circuit in a fully digital phase-locked loop, wherein the snapshot circuit receives a reference clock signal and an oscillator clock signal and outputs a snapshot clock signal to a delay-to-digital converter, characterized in that: The device comprises: A signal acquisition module, the signal acquisition module acquires the output signal of the delay-to-digital converter; a phase detection module, the phase detection module detecting the phase of the output signal by adding an additional glitch detection interval to expand the original detection interval of the delay-to-digital converter, the glitch detection interval at least covering the phase change between the reference clock signal and the oscillator clock signal; The burr judgment module judges whether a burr occurs according to the detected phase value. If the detected phase value reaches a preset threshold, it is judged that a burr occurs; if the detected phase value does not reach the preset threshold, it is judged that no burr occurs.

4. The device for detecting snapshot circuit burrs in a fully digital phase-locked loop according to claim 3, characterized in that: A delay unit with a preset length is also included between the additional burr detection interval and the original detection interval of the delay-to-digital converter.

Images