Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device (100) comprises a substrate (101), a buffer layer (102), an intermediate layer (103), an electron transport layer (104), an electron supply layer (105), a source electrode (201), a drain electrode (202), and a gate electrode (203), wherein the intermediate layer (103) comprises a stacked body in which a first intermediate layer (103A) and a second intermediate layer (103B) are stacked, and the second intermediate layer (103B) is provided on the first intermediate layer (103A). The first position 100 nm above the lower surface of the intermediate layer (103) is located in the first intermediate layer (103A), and the second position 100 nm below the upper surface of the intermediate layer (103) is located in the second intermediate layer (103B), and the value obtained by dividing the blade screw mixed dislocation density formed by the Burgers vector <11-23> / 3 at the second position by the blade screw mixed dislocation density formed by the Burgers vector <11-23> / 3 at the first position is less than 0.66.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular to a Group III nitride semiconductor device using a Group III nitride semiconductor. Background Art

[0002] A III-nitride semiconductor device using a III-nitride semiconductor, particularly gallium nitride (GaN) or aluminum gallium nitride (AlGaN), has a high dielectric breakdown voltage due to the band gap width of the material. In addition, a III-nitride semiconductor device can easily form a heterostructure such as AlGaN / GaN.

[0003] In the AlGaN / GaN heterostructure, a channel formed by high-density electrons (hereinafter referred to as "2DEG (2 Dimensional Electron Gas)") is formed on the GaN layer side of the AlGaN / GaN interface through piezoelectric polarization caused by the lattice constant difference between the materials and spontaneous polarization of AlGaN and GaN. III-nitride semiconductor devices using the channel of this two-dimensional electron gas layer are used in high-frequency power devices because of their relatively high electron saturation velocity, high insulation resistance, and high thermal conductivity.

[0004] In order to improve the characteristics of these Group III nitride semiconductor devices, it is desired to suppress as much as possible the phenomenon in which the electrical characteristics related to the output current vary with time, in other words, the phenomenon in which the reproducibility of the output current characteristics deteriorates, namely, "current collapse".

[0005] Patent document 1 discloses a nitride semiconductor device. The nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer. Furthermore, Patent document 1 discloses the following structure, namely: a channel in which carriers are accumulated is formed near the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer, the second nitride semiconductor layer has a larger band gap than the third nitride semiconductor layer, the first nitride semiconductor layer has a band gap equal to or larger than the band gap of the second nitride semiconductor layer, and a high concentration of carbon is introduced into the first nitride semiconductor layer compared to the second nitride semiconductor layer. Thus, the current collapse can be reduced by increasing the distance between the third nitride semiconductor layer in which the channel is formed and the first nitride semiconductor layer in which a high concentration of carbon is introduced. In addition, Patent document 1 discloses that the nitride semiconductor device is a transistor.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: International Publication No. 2012 / 066701 Summary of the invention

[0009] Problems to be solved by the invention

[0010] In the nitride semiconductor device described in Patent Document 1, in order to further suppress current collapse, if the second nitride semiconductor layer having a low carbon concentration and thus a small number of electron traps is simply thickened, stacking faults will occur in the second nitride semiconductor layer. Therefore, there is a problem that the gate leakage of the transistor increases due to the stacking faults in the second nitride semiconductor layer, thereby reducing the yield.

[0011] Therefore, the present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device that can suppress the occurrence of stacking faults.

[0012] Means used to solve problems

[0013] In order to achieve the above-mentioned object, a semiconductor device of one embodiment of the present disclosure comprises: a substrate; a buffer layer, which is arranged above the substrate and is composed of a group III nitride semiconductor; an intermediate layer, which is arranged above the buffer layer and is composed of a group III nitride semiconductor having a smaller band gap than the buffer layer; an electron transport layer, which is arranged above the intermediate layer and is composed of a group III nitride semiconductor having a smaller band gap than the intermediate layer; an electron supply layer, which is arranged above the electron transport layer and is composed of a group III nitride semiconductor having a larger band gap than the electron transport layer; a source electrode and a drain electrode, which are arranged above the electron supply layer with a gap between them; and a gate electrode, which is arranged relative to the gate electrode. The source electrode and the drain electrode are respectively spaced apart and arranged above the electron supply layer; the intermediate layer includes a stacked body in which a first intermediate layer and a second intermediate layer are stacked, the second intermediate layer is arranged above the first intermediate layer, a first position 100 nm above the lower surface of the intermediate layer is located in the first intermediate layer, a second position 100 nm below the upper surface of the intermediate layer is located in the second intermediate layer, and a value obtained by dividing a blade screw mixed dislocation density formed by a Burgers vector <11-23> / 3 at the second position by a blade screw mixed dislocation density formed by a Burgers vector <11-23> / 3 at the first position is less than 0.66.

[0014] In addition, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure comprises: a first step of forming a buffer layer composed of a group III nitride semiconductor on a substrate; a second step of forming an intermediate layer composed of a group III nitride semiconductor having a smaller band gap than the buffer layer on the buffer layer; a third step of forming an electron transport layer composed of a group III nitride semiconductor having a smaller band gap than the intermediate layer on the intermediate layer; a fourth step of forming an electron supply layer composed of a group III nitride semiconductor having a larger band gap than the electron transport layer on the electron transport layer; and a fifth step of forming an electron supply layer composed of a group III nitride semiconductor having a smaller band gap than the electron transport layer on the electron supply layer. A source electrode and a drain electrode are formed above the electron supply layer at a distance from each other; and a sixth step is to form a gate electrode above the electron supply layer at a distance from the source electrode and the drain electrode respectively; the second step comprises: a seventh step of forming a first intermediate layer above the buffer layer; and an eighth step of forming a second intermediate layer above the first intermediate layer; the value obtained by dividing the supply molar amount of the nitrogen raw material in the eighth step by the supply molar amount of the group III raw material is greater than 5000 and less than 20000, and the substrate temperature in the eighth step is greater than or equal to the substrate temperature in the seventh step.

[0015] Effects of the Invention

[0016] According to the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure, the occurrence of stacking faults can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a cross-sectional view showing the structure of a semiconductor device according to an embodiment.

[0018] Figure 2A It is a cross-sectional view showing the structure of a semiconductor device in the middle of manufacturing.

[0019] Figure 2B It is a cross-sectional view showing the structure of a semiconductor device in the middle of manufacturing.

[0020] Figure 2C It is a cross-sectional view showing the structure of a semiconductor device in the middle of manufacturing.

[0021] Figure 2D It is a cross-sectional view showing the structure of a semiconductor device in the middle of manufacturing.

[0022] Figure 2E It is a cross-sectional view showing the structure of a semiconductor device in the middle of manufacturing.

[0023] Figure 2F 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment.

[0024] Figure 2GIt is a cross-sectional view showing the structure of a nitride semiconductor substrate of Standard 1 of a comparative example.

[0025] Figure 2H It is a cross-sectional view showing the structure of a nitride semiconductor substrate of Standard 2 and Standard 4 of a comparative example.

[0026] Figure 3 It is a figure which shows the secondary ion mass spectrometry plot of the buffer layer, the first intermediate layer and the second intermediate layer of standard 3.

[0027] Figure 4 This is an image showing stacking faults in a standard 2 nitride semiconductor substrate.

[0028] Figure 5 This is a flowchart of a method for switching a process from a step of forming a first intermediate layer to a step of forming a second intermediate layer.

[0029] Figure 6 This is a diagram showing the results of the dependence of the number of defects detected by the defect inspection equipment on the film thickness of the first intermediate layer.

[0030] Figure 7 This is a diagram showing the results of the dependence of gate leakage on the film thickness of the second intermediate layer. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0032] In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, components, configuration positions of components, connection forms, steps, and the order of steps shown in the following embodiments are used as examples and are not intended to limit the present disclosure. In addition, the components of the following embodiments that are not described in the independent claims are described as arbitrary components.

[0033] In addition, each figure is a schematic diagram and does not necessarily illustrate strictly. Therefore, for example, the scales and the like in each figure are not necessarily the same. In addition, for example, in each figure, the thickness and size of the components are exaggerated in order to facilitate the understanding of the description. In addition, in each figure, the same reference numerals are given to substantially the same structures, and repeated descriptions are omitted or simplified.

[0034] In the present specification, terms such as parallel or orthogonal, which indicate a relationship between elements, and numerical ranges are not intended to be strictly defined, but include substantially equivalent ranges, for example, differences of several percent.

[0035] In addition, in this specification, the terms "above" and "below" do not refer to the upper side (vertically above) and the lower side (vertically below) in absolute spatial recognition, but are used as terms defined by relative positional relationships according to the stacking order in the stacking structure. In addition, the terms "above" and "below" are not only applicable to the case where two components are arranged at a distance from each other so that another component exists between the two components, but also to the case where two components are arranged in close contact with each other so that the two components are in contact.

[0036] In addition, in this specification and the accompanying drawings, the x-axis, y-axis and z-axis represent the three axes of the three-dimensional orthogonal coordinate system. In the embodiment, the z-axis direction is used as the film thickness direction of the substrate. In addition, in this specification, the "film thickness direction" refers to the film thickness direction of the substrate, which is a direction perpendicular to the upper surface of the substrate. The x-axis and y-axis are two axes parallel to the upper surface of the substrate. In addition, "planar view" refers to observation from a direction perpendicular to the upper surface of the substrate.

[0037] In addition, in this specification, unless otherwise stated, ordinal numbers such as “first” and “second” do not refer to the number or order of components, but are used to distinguish between components of the same kind to avoid confusion.

[0038] (Implementation Method)

[0039] [structure]

[0040] First, use Figure 1 A semiconductor device 100 according to an embodiment will be described. Figure 1 It is a cross-sectional view showing the structure of a semiconductor device 100 according to an embodiment.

[0041] In this embodiment, a case where the semiconductor device 100 is a high electron mobility transistor (HEMT) is described. In addition, the semiconductor device 100 is a nitride semiconductor device.

[0042] like Figure 1 As shown, the semiconductor device 100 includes a nitride semiconductor substrate 100A, a gate electrode 203, a source electrode 201, and a drain electrode 202. In addition, the nitride semiconductor substrate 100A includes a substrate 101, a buffer layer 102, an intermediate layer 103 composed of a first intermediate layer 103A and a second intermediate layer 103B, an electron traveling layer 104, an electron supply layer 105, and a 2DEG 106.

[0043] In this embodiment, the substrate 101 is, for example, a base substrate on which a buffer layer 102, an intermediate layer 103, an electron transport layer 104, and an electron supply layer 105 can be formed. In addition, the upper surface of the substrate 101 (the surface on the positive side of the z-axis) is the surface on which the above-mentioned buffer layer 102 and the like are formed. The substrate 101 is a substrate composed of Si. More specifically, the substrate 101 is a Si single crystal substrate with a (111) plane (i.e., a Si single crystal substrate with a (111) plane). The substrate 101 is not limited to a Si single crystal substrate with a (111) plane, but may also be a substrate composed of sapphire, SiC, GaN, AlN, or the like. In addition, the film thickness of the Si single crystal substrate with a (111) plane as the substrate 101 may be greater than 675 μm and less than 1200 μm.

[0044] The buffer layer 102 is provided above the substrate 101. In the present embodiment, the buffer layer 102 is, for example, a layer composed of a group III nitride semiconductor with a film thickness of 2 μm (i.e., a group III nitride semiconductor layer). In addition, the film thickness of the buffer layer 102 is not limited to the above. More specifically, the buffer layer 102 is a group III nitride semiconductor layer composed of a plurality of stacked structures composed of AlN and AlGaN. In addition, the buffer layer 102 may also be composed of a single layer or multiple layers of a group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN or AlInGaN. The buffer layer 102 may also include a layer obtained by stacking Al 1-α Ga α The buffer layer 102 may be a superlattice structure composed of a structure in which a plurality of N (0≤α<0.8) layers are stacked. Alternatively, the buffer layer 102 may be a structure in which 20 to 100 pairs of AlN and AlGaN are stacked as one pair.

[0045] In addition, the buffer layer 102 has a carbon concentration of, for example, 2.0E+19 atoms·cm -3 In addition, the carbon concentration of the buffer layer 102 is 1.0E+19 atoms·cm -3 Above 3.0E+20atoms·cm -3 The following will do.

[0046] In addition, the upper surface (the surface on the positive side of the z-axis) of the buffer layer 102 may be formed by SiH x More specifically, the dangling bonds on the upper surface of the buffer layer 102 are preferably terminated by SiH x For example, by supplying SiH to the upper surface of the buffer layer 102 4 Gas, the dangling bonds on the upper surface of the buffer layer 102 are terminated as described above. SiH 4The mixed dislocations can be reduced by adsorbing the dislocations on the upper surface of the buffer layer 102 and modifying the buffer layer 102. In addition, the so-called mixed dislocations refer to edge-shaped screw-type mixed dislocations of edge dislocations and screw dislocations. Stacking faults are known to occur starting from screw dislocations, and by reducing the mixed dislocations, the occurrence of stacking faults can be suppressed.

[0047] The intermediate layer 103 is a group III nitride semiconductor layer disposed above the buffer layer 102. More specifically, the intermediate layer 103 is a group III nitride semiconductor layer having a smaller band gap than the buffer layer 102 and a larger band gap than the electron traveling layer 104. The intermediate layer 103 includes a stacked body formed by stacking a first intermediate layer 103A and a second intermediate layer 103B. More specifically, the intermediate layer 103 includes a first intermediate layer 103A and a second intermediate layer 103B. The first intermediate layer 103A is disposed above the buffer layer 102, and the second intermediate layer 103B is disposed above the first intermediate layer 103A. The first intermediate layer 103A and the second intermediate layer 103B are group III nitride semiconductor layers having a smaller band gap than the buffer layer 102 and a larger band gap than the electron traveling layer 104, respectively.

[0048] In this embodiment, the thickness of the intermediate layer 103 is, for example, 1075 nm. In addition, the intermediate layer 103 (i.e., each of the first intermediate layer 103A and the second intermediate layer 103B) is composed of AlGaN with an average Al composition ratio of 5%. In addition, the definition of the average Al composition ratio is as follows. The average Al composition ratio of a layer is defined as follows: a In b Ga c When N(a+b+c=1, a≥0, b≥0, c≥0) is represented, it is represented by Formula 1.

[0049] (a / (a+b+c))×100% (Formula 1)

[0050] Next, the film thickness of the second intermediate layer 103B is 400 nm, and the film thickness of the first intermediate layer 103A is 675 nm.

[0051] The thickness of the intermediate layer 103 may be in the range of 1000 nm to 2000 nm, and more preferably in the range of 1000 nm to 1395 nm.

[0052] The thickness of the second intermediate layer 103B is preferably set to 100 nm or more and 400 nm or less, but is not limited thereto. The thickness of the first intermediate layer 103A is preferably set to 600 nm or more and 1000 nm or less, but is not limited thereto.

[0053] In addition, the average Al composition rate of the intermediate layer 103 can be greater than 1% and less than 10%. More preferably, the average Al composition rate satisfies the relationship of buffer layer 102>1st intermediate layer 103A≥2nd intermediate layer 103B. In this way, preferably, the higher the layer is, the lower the average Al composition rate is. In addition, the average Al composition rate of the first intermediate layer 103A can be greater than 5% and less than 10%. More preferably, the difference between the average Al composition rate of the second intermediate layer 103B and the average Al composition rate of the first intermediate layer 103A is less than 5%. In this way, the strain in the intermediate layer 103 can be reduced and the occurrence of stacking faults can be suppressed. In addition, in the intermediate layer 103, the average Al composition rate can be changed continuously instead of in stages. Furthermore, the intermediate layer 103 (the first intermediate layer 103A and the second intermediate layer 103B) can contain In.

[0054] In addition, the upper surface (the surface on the positive side of the z-axis) of the first intermediate layer 103A may be formed by SiH y More specifically, the dangling bonds on the upper surface of the first intermediate layer 103A may be terminated by SiH y For example, by supplying SiH to the upper surface of the first intermediate layer 103A, 4 Gas, the dangling bonds on the upper surface of the first intermediate layer 103A are terminated as described above. SiH 4 The dislocations adsorbed on the upper surface of the first intermediate layer 103A are modified to reduce mixed dislocations and suppress the occurrence of stacking faults.

[0055] The carbon concentration of the first intermediate layer 103A is, for example, 2.6E+16 atoms·cm -3 Alternatively, the carbon concentration of the first intermediate layer 103A may be 2E+16 atoms·cm -3 Above 7E+16atoms·cm -3 the following.

[0056] The carbon concentration of the second intermediate layer 103B is, for example, 6.5E+15 atoms·cm -3 In addition, the carbon concentration of the second intermediate layer 103B is 1.0E+15 atoms·cm -3 Above 2E+16atoms·cm -3 The following values ​​can generally be said to be values ​​below the detection limit.

[0057] Furthermore, the carbon concentration of the second intermediate layer 103B is preferably lower than the carbon concentration of the first intermediate layer 103A, and the carbon concentration of the first intermediate layer 103A is preferably lower than the carbon concentration of the buffer layer 102 .

[0058] In this embodiment, the intermediate layer 103 is described as a layer composed of two layers, namely the first intermediate layer 103A and the second intermediate layer 103B, but it can also be a plurality of layers more than two layers. A thin film AlN layer can also be inserted in the intermediate layer 103 to control the warping of the nitride semiconductor substrate 100A.

[0059] The electron transport layer 104 is provided above the intermediate layer 103. More specifically, the electron transport layer 104 is provided above the second intermediate layer 103B of the intermediate layer 103. In the present embodiment, the electron transport layer 104 is composed of GaN with a film thickness of 150 nm, for example, but the film thickness of the electron transport layer 104 is not limited thereto. In addition, the electron transport layer 104 is not limited to GaN, and may also be composed of a group III nitride semiconductor such as InGaN, AlGaN, AlInGaN, and the like, and n-type impurities may be contained in the electron transport layer 104. In addition, the electron transport layer 104 is a group III nitride semiconductor layer having a smaller band gap than the intermediate layer.

[0060] The electron supply layer 105 is a group III nitride semiconductor layer provided above the electron transport layer 104. In addition, the electron supply layer 105 is a group III nitride semiconductor layer having a larger band gap than the electron transport layer 104. In the present embodiment, the electron supply layer 105 has a film thickness of, for example, 20 nm, but the film thickness of the electron supply layer 105 is not limited thereto. The electron supply layer 105 is composed of AlGaN having an average Al composition ratio of 25%. A high concentration of 2DEG 106 is generated on the electron transport layer 104 side of the heterointerface between the electron supply layer 105 and the electron transport layer 104. The nitride semiconductor substrate 100A of the present embodiment has a channel serving as the 2DEG 106.

[0061] The electron supply layer 105 may have an average Al composition ratio of 20% to 100%. The electron supply layer 105 is not limited to AlGaN, but may be made of a group III nitride semiconductor containing In, such as AlInGaN or InAlN. The electron supply layer 105 may contain n-type impurities.

[0062] The gate electrode 203 is disposed above the electron supply layer 105. In addition, the gate electrode 203 is disposed at intervals relative to the source electrode 201 and the drain electrode 202. In the present embodiment, the gate electrode 203 is, for example, a multilayer electrode film consisting of a stacked structure in which a Ni film and an Al film are stacked in sequence, but is not limited thereto. In addition, the gate electrode 203 is in contact with the electron supply layer 105 and is Schottky-connected to the electron supply layer 105. In addition, the connection between the gate electrode 203 and the electron supply layer 105 is not limited to the Schottky connection, and an insulating film or a group III nitride semiconductor may also be provided between the gate electrode 203 and the electron supply layer 105.

[0063] The source electrode 201 and the drain electrode 202 are disposed above the electron supply layer 105 in a manner opposed to each other with the gate electrode 203 interposed therebetween. In other words, the source electrode 201 and the drain electrode 202 are disposed at intervals from each other. In the present embodiment, the source electrode 201 and the drain electrode 202 are, for example, multilayer electrode films each consisting of a stacked structure in which a Ti film and an Al film are stacked in sequence, but are not limited thereto. In addition, the source electrode 201 and the drain electrode 202 are electrically ohmically connected to the 2DEG 106, respectively.

[0064] [Method for manufacturing semiconductor device]

[0065] Below, refer to Figure 2A to Figure 2F A method for manufacturing the semiconductor device 100 according to the embodiment will be described.

[0066] Figure 2A to Figure 2E Each of them is a cross-sectional view showing the structure of the semiconductor device 100 during the manufacturing process. Figure 2F 1 is a flowchart showing a method for manufacturing the semiconductor device 100 according to the embodiment.

[0067] A buffer layer 102, an intermediate layer 103, an electron transport layer 104, and an electron supply layer 105 are formed on a substrate 101 made of Si by metal organic chemical vapor deposition (MOCVD) to form a group III nitride semiconductor layer, thereby forming a nitride semiconductor substrate 100A. Here, a semiconductor crystal growth device is used to form the nitride semiconductor substrate 100A.

[0068] First, a substrate 101 made of Si is placed in a semiconductor crystal growth apparatus ( S10 ).

[0069] Then, if Figure 2A As shown, a buffer layer 102 is formed on a substrate 101 composed of Si (S20). The buffer layer 102 is, for example, a III-nitride semiconductor layer composed of a plurality of stacked structures composed of AlN and AlGaN with a film thickness of 2 μm. The buffer layer 102 is a III-nitride semiconductor layer that is continuously epitaxially grown in a semiconductor crystal growth device in the +c-plane direction (<0001> direction). In addition, the buffer layer 102 contains a carbon concentration of 1.0E+19 atoms·cm -3 The above layer.

[0070] The following temperature and pressure conditions are applied as growth conditions for the buffer layer 102. As temperature conditions, for example, a substrate temperature of 600° C. to 1200° C. is applied. In addition, as pressure conditions, a growth pressure of reduced pressure (i.e., pressure below atmospheric pressure) is applied, and specifically, the growth pressure is preferably 50 KPa or less.

[0071] In addition, this step S20 corresponds to the first step.

[0072] Then, if Figure 2B As shown, the intermediate layer 103 is formed on the buffer layer 102 (S30). The intermediate layer 103 has a film thickness of 1075 nm, for example. The intermediate layer 103 is obtained by epitaxially growing AlGaN having an average Al composition ratio of 5%.

[0073] In addition, this step S30 is equivalent to the second process. In step S30 (the second process), the following steps S31 and S32 are performed. That is, in step S30, the first intermediate layer 103A is formed on the buffer layer 102 (S31), and further, the second intermediate layer 103B is formed on the first intermediate layer 103A (S32). This step S31 is equivalent to the seventh process, and step S32 is equivalent to the eighth process.

[0074] Due to the execution of step S31 and step S32, the intermediate layer 103 is composed of two layers (a first intermediate layer 103A and a second intermediate layer 103B) having different carbon concentrations. The first intermediate layer 103A has a thickness of 675 nm and a carbon concentration of 2.6E+16 atoms·cm -3 The second intermediate layer 103B has a thickness of 400 nm and a carbon concentration of 6.5E+15 atoms·cm -3 .

[0075] In step S30, the carrier gas is N 2 and H 2 In step S30, the growth pressure is, for example, 30 kPa. In step S30, a reduced pressure condition is preferably applied, and the growth pressure is preferably 80 kPa or less.

[0076] Regarding the substrate temperature, for example, the substrate temperature in step S31 of forming the first intermediate layer 103A is 1114° C., and the substrate temperature in step S32 of forming the second intermediate layer 103B is 1144° C. The substrate temperature in step S32 of forming the second intermediate layer 103B is greater than or equal to the substrate temperature in step S31 of forming the first intermediate layer 103A. In addition, it is preferred that the substrate temperature in step S32 of forming the second intermediate layer 103B is greater than 1100° C. and less than 1250° C. In this way, epitaxial growth in the lateral direction (i.e., in the direction parallel to the xy plane) can be promoted, so that mixed dislocations in the second intermediate layer 103B are reduced, and the occurrence of stacking faults can be suppressed.

[0077] Regarding the gas flow rate in step S31 and step S32, for example, NH 3 is 50slm. In addition, NH 3 Equivalent to the nitrogen raw material in each of step S31 and step S32. In step S31 for forming the first intermediate layer 103A, the flow rate of TMG (Trimethyl Gallium) is 81.6 sccm, and the flow rate of TMA (Trimethyl Aluminum) is 18.7 sccm. In step S32 for forming the second intermediate layer 103B, the flow rate of TMG is 40.8 sccm, and the flow rate of TMA is 9.6 sccm.

[0078] In addition, TMG and TMA correspond to the group III raw material in step S31 and step S32, respectively.

[0079] That is, ((supply molar amount of nitrogen raw material) / (supply molar amount of group III raw material)) (hereinafter referred to as V / III ratio) in step S31 of forming the first intermediate layer 103A is 4497, and the V / III ratio of the second intermediate layer 103B is 8984. In addition, the V / III ratio in step S32 of forming the second intermediate layer 103B is 5000 or more and 20000 or less.

[0080] In addition, in step S30 (second step), between step S31 and step S32, a step (ninth step) of stopping the supply of the group III raw material gas may be performed. In the present embodiment, as a method of switching from step S31 of forming the first intermediate layer 103A to step S32 of forming the second intermediate layer 103B, for example, a method of performing the ninth step of stopping the supply of the group III raw material for 1 minute is adopted. That is, between step S31 and step S32, the supply of the group III raw material is interrupted for 1 minute.

[0081] Then, if Figure 2CAs shown, an electron transit layer 104 is formed on the intermediate layer 103 (more specifically, the second intermediate layer 103B) (S40). The electron transit layer 104 has a film thickness of, for example, 150 nm. The electron transit layer 104 is obtained by epitaxially growing GaN.

[0082] As growth conditions for the electron transport layer 104, the following temperature conditions and pressure conditions are applied. As temperature conditions, for example, a substrate temperature of 900°C to 1200°C is applied, and more preferably a substrate temperature of 1000°C to 1150°C is applied. In addition, as pressure conditions, a growth pressure of normal pressure or reduced pressure can be applied. In addition, by using GaN to which impurities are not intentionally added as the electron transport layer 104, current collapse caused by the impurities can be suppressed. In addition, it is preferred that after the intermediate layer 103 is formed, the supply of the group III raw material gas is not stopped, and the electron transport layer 104 is continuously formed. In addition, it is preferred that the substrate temperature of step S40 of forming the electron transport layer 104 is equal to that of step S32 of forming the second intermediate layer 103B. In addition, this step S40 is equivalent to the third process.

[0083] Then, if Figure 2D As shown, the electron supply layer 105 is formed on the electron transit layer 104 (S50). The electron supply layer 105 is, for example, AlGaN with a film thickness of 20 nm and an average Al composition ratio of 25%.

[0084] By forming the electron supply layer 105 above the electron transit layer 104, 2DEG 106 is formed at the interface between the electron transit layer 104 and the electron supply layer 105 due to the influence of spontaneous polarization and piezoelectric polarization caused by the lattice constant difference. That is, 2DEG 106 is generated on the electron transit layer 104 side of the interface between the electron transit layer 104 and the electron supply layer 105.

[0085] As growth conditions for the electron supply layer 105, the following temperature conditions and pressure conditions are applied. As temperature conditions, for example, a substrate temperature of 900°C to 1200°C is applied, and more preferably a substrate temperature of 1000°C to 1150°C is applied. In addition, as pressure conditions, a reduced pressure condition is applied to the growth pressure, and the growth pressure is preferably 80KPa or less. Of course, the average Al composition rate of the electron supply layer 105, the film thickness, and the formation conditions can be changed as needed. In addition, step S50 is equivalent to the fourth process.

[0086] In this way, the nitride semiconductor substrate 100A is formed.

[0087] Then, if Figure 2EAs shown, a source electrode 201 and a drain electrode 202 are formed at intervals above the electron supply layer 105 (S60). More specifically, as follows. First, the nitride semiconductor substrate 100A is pre-cleaned with hydrochloric acid, and Ti and Al are deposited in sequence above the electron supply layer 105 by sputtering. Then, photolithography and dry etching are sequentially applied to pattern the stacked films of Ti and Al, thereby forming a source electrode 201 and a drain electrode 202 of a prescribed shape above the electron supply layer 105. In addition, photolithography and lift-off can also be applied sequentially to form a source electrode 201 and a drain electrode 202 of a prescribed shape. Next, the source electrode 201 and the drain electrode 202 are electrically connected to the 2DEG 106 by heat treatment in a nitrogen atmosphere. In addition, this step S60 is equivalent to the fifth process.

[0088] Next, a gate electrode 203 is formed above the electron supply layer 105 by spacing the source electrode 201 and the drain electrode 202 apart (S70). More specifically, as follows. TiN and Al are sequentially deposited above the electron supply layer 105 by sputtering. Then, photolithography and dry etching are sequentially applied to pattern the stacked film of TiN and Al, thereby forming the gate electrode 203 above the electron supply layer 105. In addition, a gate electrode 203 of a predetermined shape can also be formed by sequentially applying photolithography and lift-off. In addition, this step S70 is equivalent to the sixth step.

[0089] After going through the above series of processes, Figure 1 The semiconductor device 100 having the structure shown is completed.

[0090] [Reasons for the Present Disclosure and Experimental Results]

[0091] The reasons for conceiving the present disclosure will be described below based on experimental results.

[0092] Table 1 shows the experimental results of the growth conditions of the intermediate layer 103 and the average Al composition rate and carbon concentration of the intermediate layer 103 for each experimental standard of the embodiment. Table 1 also shows the experimental results of the growth conditions of the intermediate layer and the average Al composition rate and carbon concentration of the intermediate layer for each experimental standard of the comparative example.

[0093]

Table 1

[0094]

[0095] Here, nitride semiconductor substrates of standards 1 to 5 were prepared and used as experimental standards. Standards 1, 2, and 4 are experimental standards for comparative examples, and standards 3 and 5 are standards for this embodiment. Figure 2G and Figure 2H Provide explanation.

[0096] Figure 2G 1 is a cross-sectional view showing the structure of a nitride semiconductor substrate 100X according to Standard 1 of a comparative example. Figure 2H 1 is a cross-sectional view showing the structure of a nitride semiconductor substrate 100Y of Standard 2 and Standard 4 of a comparative example.

[0097] The nitride semiconductor substrate 100X of standard 1 is as follows Figure 2G As shown in FIG. 1 , the nitride semiconductor substrate 100A has the same structure as the nitride semiconductor substrate 100A of the present embodiment except that an intermediate layer 103X is provided instead of the intermediate layer 103. The intermediate layer 103X is composed of only the first intermediate layer 103A and does not include the second intermediate layer 103B.

[0098] The nitride semiconductor substrate 100Y of Standard 2 and Standard 4 is as follows Figure 2H As shown, the nitride semiconductor substrate 100A has the same structure as the nitride semiconductor substrate 100A of the present embodiment except that an intermediate layer 103Y is provided instead of the intermediate layer 103. The intermediate layer 103Y is composed only of the second intermediate layer 103B and does not include the first intermediate layer 103A.

[0099] In addition, regarding the experimental standards of the comparative example, namely, standard 1, standard 2, and standard 4, unless otherwise specified, the same manufacturing method as that of standard 3 of the present embodiment was used.

[0100] In addition, the structure of the nitride semiconductor substrate 100A according to the standards 3 and 5 of this embodiment is as follows: Figure 1 As shown.

[0101] The following describes nitride semiconductor substrates of standards 1 to 5.

[0102] As shown in Table 1, the total thickness of the first intermediate layer 103A and the second intermediate layer 103B is 1075 nm. Next, the carbon concentration of the first intermediate layer 103A is 2.6E+16 atoms·cm -3 The carbon concentration of the second intermediate layer 103B is 6.5E+15 atoms·cm -3 Thus, the carbon concentration of the second intermediate layer 103B is lower than the carbon concentration of the first intermediate layer 103A.

[0103] According to the above-mentioned criterion 1, the intermediate layer 103X is formed only of the first intermediate layer 103A, and according to the criterion 2, the intermediate layer 103Y is formed only of the second intermediate layer 103B. That is, in the criterion 1 and the criterion 2, the intermediate layer 103X and the intermediate layer 103Y are single-layer types.

[0104] According to Standard 3, the intermediate layer 103 is composed of a first intermediate layer 103A under the same conditions as Standard 1 and a second intermediate layer 103B under the same conditions as Standard 2, and the intermediate layer 103 is a heterogeneous layer stacking type. In addition, the film thickness of the first intermediate layer 103A of Standard 3 is 500nm, and the film thickness of the second intermediate layer 103B of Standard 3 is 575nm.

[0105] Figure 3 1 is a diagram showing a secondary ion mass spectrometry (SIMS) plot of the buffer layer 102, the first intermediate layer 103A, and the second intermediate layer 103B of standard 3. More specifically, Figure 3 The analysis results of the carbon concentration and the secondary ion concentration of Al in the buffer layer 102, the first intermediate layer 103A, and the second intermediate layer 103B of Standard 3 are shown. Figure 3 The horizontal axis of represents the depth of the intermediate layer 103 (more specifically, the second intermediate layer 103B) from the upper surface. Figure 3 It can be seen that the carbon concentration of the second intermediate layer 103B is lower than the carbon concentration of the first intermediate layer 103 A. In addition, the average Al composition rate satisfies the relationship of buffer layer 102 > first intermediate layer 103A ≥ second intermediate layer 103B.

[0106] In addition, the carbon concentrations of Standard 1, Standard 2, Standard 4, and Standard 5 shown in Table 1 are also used. Figure 3 The analyses shown were evaluated.

[0107] According to Standard 4, the intermediate layer 103Y, which is the same as Standard 2, is formed only of the second intermediate layer 103B. Standard 4 is the same as Standard 2 except that the average Al composition ratio of the intermediate layer 103Y is 10%.

[0108] The first intermediate layer 103A and the second intermediate layer 103B of Standard 5 have the same structure as the first intermediate layer 103A and the second intermediate layer 103B of Standard 3. However, according to Standard 5, the ninth step of stopping the supply of the Group III raw material gas is not performed between the step S31 of forming the first intermediate layer 103A and the step S32 of forming the second intermediate layer 103B.

[0109] The number of defects detected in the manufactured standards 1 to 3 (i.e., the nitride semiconductor substrate 100X of standard 1, the nitride semiconductor substrate 100Y of standard 2, and the nitride semiconductor substrate 100A of standard 3) was measured using a defect inspection device. As the defect inspection device, INSPECTRA 3000SR-III200 manufactured by Toray Engineering Co., Ltd. of Japan was used. Here, as defects, stacking faults and defects other than stacking faults were detected.

[0110] Furthermore, the mixed dislocation density of the prepared standards 1 to 3 was measured using a transmission electron microscope (TEM). The dislocation whose Burgers vector is <11-23> / 3 obtained by the transmission electron microscope (TEM) is an edge-shaped screw-type mixed dislocation in which edge dislocations and screw dislocations are mixed. Here, for standards 1 to 3, the density of edge-shaped screw-type mixed dislocations composed of Burgers vector <11-23> / 3 was measured. Furthermore, in order to quantify the effect of reducing the mixed dislocation density of the intermediate layer, the following index was used. First, the mixed dislocation density at the second position 100 nm below the upper surface of the intermediate layer (more specifically, the intermediate layers 103, 103X and 103Y) was measured, and the mixed dislocation density at the first position 100 nm above the lower surface of the intermediate layer (more specifically, the intermediate layers 103, 103X and 103Y) was measured. The mixed dislocation density at the first position was defined as B, and the mixed dislocation density at the second position was defined as A. In order to quantify the effect of reducing the mixed dislocation density, the mixed dislocation density ratio (A / B) was evaluated as an index.

[0111] When the mixed dislocation density ratio is small, more specifically, when it is sufficiently small compared to 1, it means that the mixed dislocation density at the upper position of the intermediate layer, i.e., the second position, is low relative to the mixed dislocation density at the lower position of the intermediate layer, i.e., the first position, and it can be said that the mixed dislocation density reduction effect of the intermediate layer is high. In addition, when the mixed dislocation density ratio is sufficiently small compared to 1, it means that the mixed dislocation density decreases as it moves upward in the intermediate layer.

[0112] In addition, regarding standard 3 which is the standard of this embodiment, the first position 100 nm above the lower surface of the intermediate layer 103 is located in the first intermediate layer 103A, and the second position 100 nm below the upper surface of the intermediate layer 103 is located in the second intermediate layer 103B.

[0113] Table 2 shows the experimental results of the number of defect detections, the occurrence of stacking faults, and the mixed dislocation density for standards 1 to 3.

[0114]

Table 2

[0115]

[0116] More specifically, Table 2 shows the number of defects (defect detection number) detected by the defect inspection equipment for each nitride semiconductor substrate of Standards 1 to Standards 3. In addition, Table 2 shows the presence or absence of stacking faults, the mixed dislocation density A at the second position and the mixed dislocation density B at the first position, and the mixed dislocation density ratio (A / B) for the center and the periphery of each nitride semiconductor substrate of Standards 1 to Standards 3. In addition, when the nitride semiconductor substrate is used for HEMT, the center becomes a more important area than the periphery of the nitride semiconductor substrate, so the experimental results on the center are more important.

[0117] First, two standards, namely, standards 1 and 2, in which the intermediate layer 103X and the intermediate layer 103Y are single-layer types, are compared. The number of defects detected in standard 2 (91160) is 512 times higher than the number of defects detected in standard 1 (178). Figure 4 is an image showing stacking faults detected by a defect inspection device according to Standard 2. More specifically, Figure 4 is an image showing stacking faults in the nitride semiconductor substrate 100Y of Standard 2. Figure 4 The stacking fault shown is a stacking fault that occurs in a certain layer of the nitride semiconductor substrate 100Y. In addition, the crescent-shaped defect detected by the defect inspection equipment using UV light is referred to as a stacking fault. The stacking fault in the nitride semiconductor substrate may become a leakage path when the HEMT is formed using the nitride semiconductor substrate, so it is desired to reduce it. As mentioned above, the defect inspection equipment detects stacking faults and defects other than stacking faults as defects. The defect detection number shown in Table 2 includes both the defect detection number of stacking faults and the defect detection number of defects other than stacking faults. Here, the background value (background level) of the defect detection number of defects other than stacking faults is about 300. Therefore, for the defect detection number that greatly exceeds the standard of about 300, it can be judged that a stacking fault has occurred. As shown in Table 2, it can be determined that stacking faults did not occur in Standard 1, in which the number of detected defects was 178, and stacking faults occurred in Standard 2, in which the number of detected defects was 91,160. In addition, it was confirmed that stacking faults did not occur in both the center and the periphery of the nitride semiconductor substrate 100X of Standard 1, and stacking faults occurred in both the center and the periphery of the nitride semiconductor substrate 100Y of Standard 2.

[0118] It is known that stacking faults occur starting from screw dislocations. Therefore, in order to suppress stacking faults, it is preferable to reduce the mixed dislocation density. Comparing the mixed dislocation density ratio (A / B) in the center of Standard 1 and Standard 2, it can be seen that the mixed dislocation density ratio of Standard 1 is smaller. More specifically, in Standard 1, the mixed dislocation density ratio is sufficiently smaller than 1 and becomes 0.66. As mentioned above, it can be said that the mixed dislocation density of the intermediate layer 103X is reduced. In this way, according to Standard 1, the mixed dislocation density at the upper position (second position) of the intermediate layer 103X can be sufficiently reduced, so it is considered that the central stacking fault is suppressed.

[0119] As described above, according to the experimental results in Table 2, in order to suppress stacking faults to a degree equal to or greater than that of Standard 1, that is, to eliminate stacking faults, the mixed dislocation density ratio is preferably 0.66 or less.

[0120] Furthermore, the standard 3, which is the standard of the present embodiment, was studied. According to the standard 3, the number of defects detected was reduced to 0.01 times compared with the standard 2, the number of defects detected was 552 and exceeded about 300 according to the standard 3, so it was judged that stacking faults occurred. However, as shown in Table 2, according to the standard 3, no stacking faults occurred in the more important area, that is, the center.

[0121] The mixed dislocation density ratio at the center is 0.66 in Standard 1 and 0.55 in Standard 3. Thus, in Standard 3, which is the standard of the present embodiment, since the intermediate layer 103 includes the first intermediate layer 103A and the second intermediate layer 103B, the mixed dislocation density ratio at the center is less than 0.66, more specifically 0.55. It can be said that Standard 3, which is the standard of the present embodiment, has a smaller mixed dislocation density ratio at the center than Standard 1, which is the standard of the comparative example, and the mixed dislocation density of the intermediate layer 103 is reduced more effectively. It can be seen from this that, with respect to the intermediate layer, the heterogeneous layer stacking type of Standard 3 is better than the single layer type of Standard 1. In addition, thus, according to Standard 3, since the mixed dislocation density at the upper position (the second position) of the intermediate layer 103 can be sufficiently reduced, it is considered that the stacking fault at the center is suppressed.

[0122] Furthermore, it is considered that the reason why the number of stacking faults is small in Criterion 3 where the intermediate layer 103 is a heterogeneous layer stacking type is because the number of mixed dislocations is reduced at the interface between the first intermediate layer 103A and the second intermediate layer 103B for the following two reasons.

[0123] The first reason is as follows. In step S32 of forming the second intermediate layer 103B, the V / III ratio is 5000 to 20000, specifically, 8984, which is high. As a result, as the first reason, the following situation can be cited, namely: the nitrogen face of the second intermediate layer 103B is stably formed, the migration of Ga is suppressed, and the growth of the second intermediate layer 103B in the lateral direction is promoted.

[0124] The second reason is as follows. The substrate temperature in step S32 of forming the second intermediate layer 103B is higher than or equal to the substrate temperature in step S31 of forming the first intermediate layer 103A, specifically, 1144°C. As a result, the following can be cited as the second reason, namely, in step S32, the carrier gas H 2 The resulting etching is promoted, and the growth of the second intermediate layer 103B in the lateral direction is promoted.

[0125] Based on the above, the V / III ratio of step S32 for forming the second intermediate layer 103B is preferably 5000 or more and 20000 or less. In addition, the substrate temperature of step S32 for forming the second intermediate layer 103B may be greater than or equal to the substrate temperature of step S31 for forming the first intermediate layer 103A. In addition, in step S32, the substrate temperature for promoting the growth in the lateral direction is preferably 1100° C. or more and 1250° C. or less. That is, if the substrate temperature of step S32 for forming the second intermediate layer 103B is 1100° C. or more and 1250° C. or less, the growth of the second intermediate layer 103B is further promoted, and the occurrence of stacking faults is suppressed.

[0126] Next, we will compare Standard 1 and Standard 3. Here we will focus on the carbon concentration.

[0127] As described in the above background technology, it is desirable to suppress current collapse as much as possible. As a cause of the current collapse, the capture of electrons can be cited. The carbon in the intermediate layer 103 becomes an electron capture source, and the higher the carbon concentration in the intermediate layer 103, the easier it is for electrons to be captured. Therefore, in order to suppress the current collapse, it is required to sufficiently reduce the carbon concentration in the intermediate layer 103.

[0128] The carbon concentration of the intermediate layer 103X (first intermediate layer 103A) of standard 1 is 2.6E+16 atoms·cm -3 The carbon concentrations of the first intermediate layer 103A and the second intermediate layer 103B of Standard 3 are 2.6E+16 atoms·cm -3 and 6.5E+15atoms·cm -3According to Standard 3, the TMG flow rate and TMA flow rate when forming the second intermediate layer 103B are about half of the TMG flow rate and TMA flow rate when forming the first intermediate layer 103A. Therefore, the carbon concentration of the second intermediate layer 103B can be sufficiently reduced compared to the first intermediate layer 103A. In this way, the carbon concentration in the second intermediate layer 103B included in the intermediate layer 103 of Standard 3 is sufficiently reduced compared to the intermediate layer 103X of Standard 1, so Standard 3 can fully suppress current collapse compared to Standard 1.

[0129] Next, the number of defects detected in the produced standard 2 and standard 4 was measured using a defect inspection device. Table 3 shows the experimental results of the number of defects detected in the standard 2 and standard 4.

[0130]

Table 3

[0131]

[0132] From the experimental results in Table 3, it can be seen that the number of defect detections in Standard 4 is reduced compared to Standard 2. It can be seen that in order to eliminate the stacking fault, it is preferred that the Al average composition ratio of the second intermediate layer 103B is high. This is considered to be because when the difference in the Al average composition ratio between the buffer layer 102 (Al average composition ratio: 20% or more and 100% or less) and the intermediate layer 103Y (second intermediate layer 103B) is small, the strain generated in the intermediate layer 103Y becomes small, so the occurrence of stacking faults is suppressed. Since it is expected that the same phenomenon will occur in Standard 3 as the standard of this embodiment, it is also preferred in Standard 3 that the Al average composition ratio is buffer layer 102>first intermediate layer 103A≥second intermediate layer 103B.

[0133] That is, in this embodiment, it is preferred that the average Al composition ratio of the first intermediate layer 103A is greater than or equal to the average Al composition ratio of the second intermediate layer 103B, and the average Al composition ratio of the buffer layer 102 is greater than the average Al composition ratio of the first intermediate layer 103A.

[0134] This reduces the strain generated in the first intermediate layer 103A and the second intermediate layer 103B. This achieves the semiconductor device 100 that can further suppress the occurrence of stacking faults.

[0135] Furthermore, in the present embodiment, the average Al composition ratio of the first intermediate layer 103A is preferably 5% or more and 10% or less.

[0136] Thus, when the average Al composition ratio of the buffer layer 102 is 20% or more and 100% or less, the strain generated in the first intermediate layer 103A is reduced. Therefore, the semiconductor device 100 capable of further suppressing the occurrence of stacking faults is realized.

[0137] In addition, in the present embodiment, the difference between the average Al composition ratio of the second intermediate layer 103B and the average Al composition ratio of the first intermediate layer 103A is preferably 5% or less.

[0138] This further reduces the strain generated in the second intermediate layer 103B. Therefore, the semiconductor device 100 is realized which can further suppress the occurrence of stacking faults.

[0139] Next, the number of defects detected in the produced Standard 3 and Standard 5 was measured using a defect inspection device. Table 4 shows the experimental results of the number of defects detected in Standard 3 and Standard 5.

[0140]

Table 4

[0141]

[0142] In addition, both Standard 3 and Standard 5 are standards of the present embodiment. The nitride semiconductor substrate 100A of Standard 3 is manufactured by performing the ninth step, while the nitride semiconductor substrate 100A of Standard 5 is manufactured without performing the ninth step.

[0143] According to the experimental results in Table 4, in Standard 3, the number of detected defects is smaller than that in Standard 5, that is, the occurrence of stacking faults is suppressed. Therefore, in order to reduce stacking faults, it is better to perform the ninth step of stopping the supply of the Group III raw material gas between Step S31 of forming the first intermediate layer 103A and Step S32 of forming the second intermediate layer 103B.

[0144] This is explained as follows. If the supply of the group III raw material is interrupted, the growth at a high temperature of 1100° C. or higher is interrupted, and the surface of the first intermediate layer 103A is heated by the carrier gas H 2 The surface of the first intermediate layer 103A is roughened by etching. It is considered that the orientation of dislocations changes during the growth of the second intermediate layer 103B, and the number of mixed dislocations decreases due to mutual interference between dislocations, thereby reducing the number of defects detected in Criterion 3.

[0145] That is, it is preferable that the second step includes a ninth step of stopping the supply of the group III source gas between the seventh step and the eighth step.

[0146] Thus, a method for manufacturing the semiconductor device 100 capable of suppressing the occurrence of stacking faults is realized.

[0147] Furthermore, using Figure 5 The ninth step will be described.

[0148] Figure 5 103A is a flowchart of a method for switching the process from step S31 of forming the first intermediate layer 103A to step S32 of forming the second intermediate layer 103B. More specifically, Figure 5(a) shows a flow chart of Standard 3 for performing the ninth step, Figure 5 (b) shows a flow chart of Standard 5 without performing the 9th step.

[0149] like Figure 5 As shown in (a), in the manufacturing method of the nitride semiconductor substrate 100A of standard 3, steps S10, S20 and S31 are performed. A 9th step (S33) of stopping the supply of the group III raw material gas is also performed. That is, in this case, the supply of the group III raw material gas is interrupted. Then, the supply of the group III raw material gas is restarted (S34) to form the second intermediate layer 103B (S32). In addition, the case of changing the substrate temperature in steps S31 and S32 is preferably set to the period during which the supply of the group III raw material gas is stopped (that is, during the 9th step (S33)). In addition, the time of the 9th step (S33), that is, the time for interrupting the supply of the group III raw material gas, is preferably more than 1 minute and less than 5 minutes. By making the time more than 1 minute, the surface of the first intermediate layer 103A can be sufficiently roughened. In addition, by making the time less than 5 minutes, the productivity can be improved. In addition, in the 9th step (S33), it is preferred to supply SiH 4 By supplying SiH when the supply of the group III raw material is interrupted (9th step (S33)), 4 The upper surface of the first intermediate layer 103A is SiH y Therefore, SiH 4 It can be expected that the dislocations adsorbed on the upper surface of the first intermediate layer 103A will modify the first intermediate layer 103A and reduce mixed dislocations, thereby suppressing the occurrence of stacking faults.

[0150] Thus, in this embodiment, the time for the ninth step is preferably not less than 1 minute and not more than 5 minutes.

[0151] The surface of the first intermediate layer 103A can be made sufficiently rough, and productivity can be improved.

[0152] In addition, in the present embodiment, in the ninth step, SiH 4 gas.

[0153] Therefore, SiH 4 The dislocations adsorbed on the upper surface of the first intermediate layer 103A are modified to reduce mixed dislocations and suppress the occurrence of stacking faults.

[0154] In addition, if Figure 5 As shown in (b), in Standard 5, the nitride semiconductor substrate 100A is manufactured without performing the ninth step.

[0155] The semiconductor device 100 and the method for manufacturing the semiconductor device 100 according to the present embodiment are summarized as follows.

[0156] The semiconductor device 100 of this embodiment comprises: a substrate 101; a buffer layer 102, which is arranged above the substrate 101 and is composed of a group III nitride semiconductor; an intermediate layer 103, which is arranged above the buffer layer 102 and is composed of a group III nitride semiconductor having a smaller band gap than the buffer layer 102; an electron transport layer 104, which is arranged above the intermediate layer 103 and is composed of a group III nitride semiconductor having a smaller band gap than the intermediate layer 103; an electron supply layer 105, which is arranged above the electron transport layer 104 and is composed of a group III nitride semiconductor having a larger band gap than the electron transport layer 104; a source electrode 201 and a drain electrode 202, which are arranged above the electron supply layer 105 and are spaced apart from each other; and a gate electrode 203, which is arranged above the electron supply layer 105 and is spaced apart from each other relative to the source electrode 201 and the drain electrode 202. The intermediate layer 103 includes a laminated body formed by laminating a first intermediate layer 103A and a second intermediate layer 103B. The second intermediate layer 103B is provided above the first intermediate layer 103A. The first position 100 nm above the lower surface of the intermediate layer 103 is located in the first intermediate layer 103A, and the second position 100 nm below the upper surface of the intermediate layer 103 is located in the second intermediate layer 103B. The value obtained by dividing the blade screw mixed dislocation density (A) formed by the Burgers vector <11-23> / 3 at the second position by the blade screw mixed dislocation density (B) formed by the Burgers vector <11-23> / 3 at the first position (i.e., the mixed dislocation density ratio A / B) is 0.66 or less.

[0157] Thus, as shown in the above-mentioned criterion 3, since the intermediate layer 103 includes the first intermediate layer 103A and the second intermediate layer 103B, the mixed dislocation density ratio (A / B) is less than 0.66, more specifically 0.55. In the present embodiment (e.g., criterion 3), the mixed dislocation density ratio (A / B) in the center is smaller than that in the criterion 1 as a comparative example, and it can be said that the mixed dislocation density of the intermediate layer 103 is reduced more effectively. In this way, in the present embodiment, the mixed dislocation density at the upper position (second position) of the intermediate layer 103 can be sufficiently reduced. Therefore, the number of stacking faults caused by the mixed dislocation density at the second position can be suppressed, that is, a semiconductor device 100 capable of suppressing the occurrence of stacking faults is realized.

[0158] The manufacturing method of the semiconductor device 100 of the present embodiment comprises: a first step of forming a buffer layer 102 composed of a group III nitride semiconductor above a substrate 101; a second step of forming an intermediate layer 103 composed of a group III nitride semiconductor having a smaller band gap than the buffer layer 102 above the buffer layer 102; a third step of forming an electron transporting layer 104 composed of a group III nitride semiconductor having a smaller band gap than the intermediate layer 103 above the intermediate layer 103; a fourth step of forming an electron supply layer 105 composed of a group III nitride semiconductor having a larger band gap than the electron transporting layer 104 above the electron transporting layer 104; a fifth step of forming a source electrode 201 and a drain electrode 202 spaced apart from each other above the electron supply layer 105; and a sixth step of forming a gate electrode 203 spaced apart from the source electrode 201 and the drain electrode 202 above the electron supply layer 105. The second step includes a seventh step of forming a first intermediate layer 103A on the buffer layer 102 and an eighth step of forming a second intermediate layer 103B on the first intermediate layer 103A. The value obtained by dividing the molar amount of the nitrogen source supplied by the molar amount of the group III source supplied in the eighth step (V / III ratio) is 5000 to 20000, and the substrate temperature in the eighth step is higher than or equal to the substrate temperature in the seventh step.

[0159] Thus, as shown in the above-mentioned criterion 3, since the intermediate layer 103 includes the first intermediate layer 103A and the second intermediate layer 103B, the mixed dislocation density ratio (A / B) is less than 0.66, more specifically 0.55. In the present embodiment (e.g., criterion 3), the mixed dislocation density ratio (A / B) in the center is smaller than that in the criterion 1 which is a comparative example, and it can be said that the mixed dislocation density of the intermediate layer 103 is reduced more effectively. Thus, in the present embodiment, the mixed dislocation density at the upper position (second position) of the intermediate layer 103 can be sufficiently reduced. Therefore, the number of stacking faults caused by the mixed dislocation density at the second position can be suppressed, that is, a method for manufacturing the semiconductor device 100 capable of suppressing the occurrence of stacking faults is realized.

[0160] Furthermore, the V / III ratio in step S32 (eighth step) of forming the second intermediate layer 103B is 5000 or more and 20000 or less, so that the nitrogen face of the second intermediate layer 103B is stably formed, Ga migration is suppressed, and the growth of the second intermediate layer 103B in the lateral direction is promoted. Therefore, the method for manufacturing the semiconductor device 100 of the present embodiment can further suppress the occurrence of stacking faults.

[0161] Furthermore, the substrate temperature in step S32 of forming the second intermediate layer 103B is higher than or equal to the substrate temperature in step S31 (seventh step) of forming the first intermediate layer 103A, so that the carrier gas H 2 The resulting etching is promoted, and the growth of the second intermediate layer 103B in the lateral direction is promoted. Therefore, the method for manufacturing the semiconductor device 100 of the present embodiment can further suppress the occurrence of stacking faults.

[0162] In addition, the film thickness of the intermediate layer 103 in this embodiment was further studied below.

[0163] like Figure 3 As shown in FIG. 1 , the carbon concentration of the buffer layer 102 is much higher than the carbon concentration of the first intermediate layer 103A and the second intermediate layer 103B. From the viewpoint that electrons are captured by carbon in the buffer layer 102, the interval between the electron traveling layer 104 and the buffer layer 102 is preferably 1000 nm or more. Therefore, the film thickness of the intermediate layer 103 was set to 1075 nm and 1395 nm, and the film thickness dependence of the first intermediate layer 103A and the second intermediate layer 103B of each characteristic was confirmed.

[0164] Figure 6 Graph showing the dependence of the number of defects detected by the defect inspection equipment on the film thickness of the first intermediate layer 103A. Figure 6 It is known that the number of detected defects decreases as the first intermediate layer 103A is thicker regardless of the thickness of the intermediate layer 103. The reduction in the number of detected defects is saturated when the thickness of the first intermediate layer 103A is 600 nm or more, so the thickness of the first intermediate layer 103A is preferably set to 600 nm or more.

[0165] Figure 7 1 is a graph showing the result of the dependence of gate leakage on the film thickness of the second intermediate layer 103B. More specifically, Figure 7 1 shows the results of measuring the gate leakage of the semiconductor device 100 when the film thickness of the second intermediate layer 103B is changed. Figure 7 As shown, the measurement conditions of gate leakage are as follows. The length of the gate electrode 203 (length in the x-axis direction), i.e., Lg, is 150nm, the width of the gate electrode 203 (width in the y-axis direction), i.e., Wg, is 200μm, the distance between the gate electrode 203 and the drain electrode 202 (distance in the x-axis direction), i.e., Lgd, is 5μm, and the distance between the gate electrode 203 and the source electrode 201 (distance in the x-axis direction), i.e., Lgs, is 2μm. The voltage between the gate electrode 203 and the source electrode 201, i.e., Vgs, is 0V, and the voltage between the drain electrode 202 and the source electrode 201, i.e., Vds, is 150V. From Figure 7It is known that the gate leakage is reduced as the thickness of the second intermediate layer 103B is thicker. The reduction of gate leakage is saturated when the thickness of the second intermediate layer 103B is 400 nm or less, so the thickness of the second intermediate layer 103B is preferably set to 400 nm or less.

[0166] That is, in the present embodiment, the thickness of the intermediate layer 103 is preferably not less than 1000 nm and not more than 1395 nm.

[0167] This can sufficiently increase the distance between the electron transit layer 104 and the buffer layer 102 having a high carbon concentration, thereby suppressing electrons from being trapped by carbon in the buffer layer 102 , that is, suppressing current collapse.

[0168] Furthermore, in the present embodiment, the thickness of the first intermediate layer 103A is preferably 600 nm or more.

[0169] As a result, the number of defects detected is reduced, that is, a semiconductor device 100 is achieved in which the occurrence of stacking faults can be further suppressed.

[0170] Furthermore, in the present embodiment, the thickness of the second intermediate layer 103B is preferably 400 nm or less.

[0171] Thus, gate leakage in the semiconductor device 100 can be reduced.

[0172] (Other embodiments)

[0173] The above describes one or more forms of semiconductor devices based on the embodiments, but the present disclosure is not limited to these embodiments, etc. For example, forms obtained by implementing various modifications that a person skilled in the art would think of to the embodiments, and forms realized by arbitrarily combining the constituent elements and functions in the embodiments within the scope of the present disclosure are also included in the present disclosure.

[0174] In addition, various changes, substitutions, additions, omissions, etc. can be made to the above-mentioned embodiments within the scope of the claims or the scope of their equivalents.

[0175] Industrial Applicability

[0176] The semiconductor device of the present disclosure is useful as a power switching element or the like used in communication equipment, inverters, power supply circuits, and the like that require high-speed operation.

[0177] Description of symbols

[0178] 100 Semiconductor devices

[0179] 100A, 100X, 100Y Nitride semiconductor substrate

[0180] 101 Substrate

[0181] 102 Buffer layer

[0182] 103, 103X, 103Y middle layer

[0183] 103A 1st Intermediate Floor

[0184] 103B 2nd Intermediate Layer

[0185] 104 Electron Travel Layer

[0186] 105 Electron supply layer

[0187] 106 2DEG

[0188] 201 Source electrode

[0189] 202 drain electrode

[0190] 203 Gate electrode

Claims

1. A semiconductor device, characterized in that: have: substrate; A buffer layer, disposed above the substrate, and composed of a Group III nitride semiconductor; an intermediate layer, disposed above the buffer layer, and composed of a Group III nitride semiconductor having a smaller band gap than the buffer layer; An electron traveling layer, provided above the intermediate layer, and composed of a Group III nitride semiconductor having a smaller band gap than that of the intermediate layer; an electron supply layer, provided above the electron transport layer, and composed of a group III nitride semiconductor having a larger band gap than that of the electron transport layer; A source electrode and a drain electrode are provided above the electron supply layer with a gap therebetween; and a gate electrode provided above the electron supply layer at intervals from the source electrode and the drain electrode, The intermediate layer includes a laminated body in which a first intermediate layer and a second intermediate layer are laminated. The second intermediate layer is arranged above the first intermediate layer. A first position 100 nm above the lower surface of the intermediate layer is located in the first intermediate layer, The second position below the upper surface of the intermediate layer by 100 nm is located in the second intermediate layer. The value obtained by dividing the density of the blade-shaped screw mixed dislocation formed by the Burgers vector <11-23> / 3 at the second position by the density of the blade-shaped screw mixed dislocation formed by the Burgers vector <11-23> / 3 at the first position is 0.66 or less, The thickness of the intermediate layer is not less than 1000 nm and not more than 1395 nm.

2. The semiconductor device according to claim 1, wherein The first intermediate layer has a thickness of 600 nm or more.

3. The semiconductor device according to claim 2, wherein: The second intermediate layer has a thickness of 400 nm or less.

4. The semiconductor device according to any one of claims 1 to 3, wherein The average Al composition ratio of the first intermediate layer is greater than or equal to the average Al composition ratio of the second intermediate layer. The buffer layer has an average Al composition ratio greater than an average Al composition ratio of the first intermediate layer.

5. The semiconductor device according to claim 4, wherein: The first intermediate layer has an average Al composition ratio of not less than 5% and not more than 10%.

6. The semiconductor device according to claim 5, wherein: The difference between the average Al composition rate of the second intermediate layer and the average Al composition rate of the first intermediate layer is 5% or less.

7. The semiconductor device according to claim 1, wherein The dangling bonds on the upper surface of the buffer layer are due to SiH x And terminate, x=0,1,2,3.

8. The semiconductor device according to claim 1, wherein The dangling bonds on the upper surface of the first intermediate layer are due to SiH y And terminate, y=0,1,2,3.

9. A method for manufacturing a semiconductor device, characterized in that: have: In a first step, a buffer layer composed of a group III nitride semiconductor is formed on the substrate; In a second step, an intermediate layer having a film thickness of not less than 1000 nm and not more than 1395 nm and composed of a Group III nitride semiconductor having a smaller band gap than the buffer layer is formed on the buffer layer; A third step of forming an electron transport layer composed of a Group III nitride semiconductor having a smaller band gap than that of the intermediate layer on the intermediate layer; A fourth step of forming an electron supply layer composed of a Group III nitride semiconductor having a larger band gap than that of the electron transporting layer on the electron transporting layer; In a fifth step, a source electrode and a drain electrode are formed on the electron supply layer at a distance from each other; and In a sixth step, a gate electrode is formed above the electron supply layer at a distance from the source electrode and the drain electrode. The second step includes: A seventh step of forming a first intermediate layer on the buffer layer; and In the eighth step, a second intermediate layer is formed on the first intermediate layer. The value obtained by dividing the molar amount of the nitrogen raw material supplied in the eighth step by the molar amount of the Group III raw material supplied is 5000 or more and 20000 or less, and The substrate temperature in the eighth step is higher than or equal to the substrate temperature in the seventh step.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The substrate temperature in the eighth step is not less than 1100°C and not more than 1250°C.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein: The second step includes a ninth step of stopping the supply of the group III source gas between the seventh step and the eighth step.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The time for the ninth step is not less than 1 minute and not more than 5 minutes.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: In the above-mentioned ninth step, SiH4 gas is supplied.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: In the above-mentioned ninth step, SiH4 gas is supplied.

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