Display panel, method of manufacturing the same, and method of correcting defects of the display panel

Abstract

A display panel whose manufacturing yield is inhibited from decreasing, a defect correction method for such a display panel, and a manufacturing method for a display panel using the defect correction method are provided. A display panel (1000a) has a display region (AA) defined by a plurality of pixels (P) and a peripheral region (NA) other than the display region. The display panel has, in the peripheral region, a gate driver circuit including a shift register (110) and a dummy capacitor portion (CA). The dummy capacitor portion includes a plurality of capacitor elements (40) connected in parallel with a dummy stage. The plurality of capacitor elements each include a first capacitor electrode (CE1s), a second capacitor electrode (CE2g), and a dielectric layer between the first capacitor electrode and the second capacitor electrode. The dummy capacitor portion further has at least one first connection portion whose respective both ends are connected to an arbitrary one of the first capacitor electrodes of the plurality of capacitor elements and another one of the first capacitor electrodes of the plurality of capacitor elements.

Description

TECHNICAL FIELD

[0001] The present application relates to a display panel, a defect correction method for a display panel, and a manufacturing method for a display panel. BACKGROUND

[0002] An active matrix type display panel provided with a thin film transistor (TFT) is used for display devices for various uses such as mobile terminals, televisions, and the like.

[0003] From the viewpoint of reducing manufacturing costs, design, and functionality, it is required to narrow the frame of the active matrix type display panel. By using a gate driver monolithic (GDM) technology that integrates a gate drive circuit (sometimes also referred to as a "gate driver") on a TFT substrate, compared to a case where a gate drive circuit is mounted on a TFT substrate using COF (Chip On Film) or COG (Chip On Glass), or the like, it is possible to reduce costs involved in driver mounting, and to achieve a narrow frame. The GDM technology is sometimes also referred to as GOA (Gate on Array). For example, a display device to which the GDM technology is applied is disclosed in Patent Literature 1.

[0004] The gate drive circuit includes a shift register having a plurality of stages corresponding to a plurality of pixel rows possessed by the display device. The output of each stage of the shift register is connected to a gate bus line (scanning wiring) associated with the pixel row, respectively, and a scanning signal is supplied to the gate bus line. In order to improve the operation stability of the shift register, a dummy stage that does not contribute to display is sometimes also provided, and a dummy scanning line having the same wiring resistance as the gate bus line is connected to the dummy stage (for example, Patent Literatures 2 and 3).

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: International Publication No. 2011 / 104945

[0008] Patent Literature 2: Japanese Patent Application Publication No. 2002-214643

[0009] Patent Literature 3: U.S. Patent Application Publication No. 2007 / 001987 Specification SUMMARY

[0010] Technical Problem to be Solved by the Invention

[0011] It is required to improve the manufacturing yield of a display device to which the GDM technology is applied. An object of the present application is to provide a display panel capable of suppressing a decrease in manufacturing yield, a defect correction method for such a display panel, and a manufacturing method for a display panel using the defect correction method.

[0012] Technical solution for solving technical problems

[0013] According to the embodiment of the present application, the following solution means described in the items are provided.

[0014] [Item 1]

[0015] A display panel has a plurality of pixels arranged in a matrix shape of a plurality of pixel rows and a plurality of pixel columns, has a display region and a peripheral region outside the display region, and further has a gate drive circuit provided in the peripheral region, the gate drive circuit including a shift register having a plurality of stages corresponding to the plurality of pixel rows respectively and a dummy stage, and a dummy capacitor portion provided in the peripheral region, the dummy capacitor portion including a plurality of capacitor elements connected to the dummy stage in parallel, each of the plurality of capacitor elements including a first capacitor electrode, a second capacitor electrode, and a dielectric layer between the first capacitor electrode and the second capacitor electrode, the dummy capacitor portion further including at least one first connection portion, each of the at least one first connection portion having both ends connected to the first capacitor electrode of any one of the plurality of capacitor elements and the first capacitor electrode of another one of the plurality of capacitor elements.

[0016] [Item 2]

[0017] The display panel according to item 1, for each of the first capacitor electrodes of the plurality of capacitor elements, the dummy capacitor portion has two or more paths from an input terminal to the first capacitor electrode of each of the plurality of capacitor elements, the input terminal inputting a signal that provides a potential to the first capacitor electrode.

[0018] [Item 3]

[0019] The display panel according to item 1 or 2, the at least one first connection portion includes a plurality of first connection portions, the first capacitor electrode of each of the plurality of capacitor elements is connected to one end of each of any two or more of the plurality of first connection portions, the other end of the any two or more of the plurality of first connection portions is connected to the first capacitor electrode of a different capacitor element from the plurality of capacitor elements respectively, the plurality of capacitor elements includes two or more capacitor elements each having the first capacitor electrode connected to an input terminal without passing through the first capacitor electrode of any one of the plurality of capacitor elements, the input terminal inputting a signal that provides a potential to the first capacitor electrode.

[0020] [Item 4]

[0021] The display panel according to any one of items 1 to 3, wherein the second capacitance electrode is commonly provided in the plurality of capacitance elements, and has at least one first opening portion overlapping the at least one first connection portion.

[0022] [Item 5]

[0023] The display panel according to any one of items 1 to 3, wherein the virtual capacitance portion further has at least one second connection portion, both ends of each of the at least one second connection portion being connected to any one of the second capacitance electrodes of the plurality of capacitance elements and another one of the second capacitance electrodes of the plurality of capacitance elements.

[0024] [Item 6]

[0025] The display panel according to item 5, wherein the at least one second connection portion is provided in a manner not overlapping the at least one first connection portion.

[0026] [Item 7]

[0027] The display panel according to item 5 or 6, wherein, for each of the second capacitance electrodes of the plurality of capacitance elements, the virtual capacitance portion has two or more paths from an input terminal to each of the second capacitance electrodes of the plurality of capacitance elements, the input terminal inputting a signal for providing a potential to the second capacitance electrode.

[0028] [Item 8]

[0029] The display panel according to any one of items 5 to 7, wherein the at least one second connection portion includes a plurality of second connection portions, the second capacitance electrode of each of the plurality of capacitance elements being connected to one end of any two or more of the plurality of second connection portions, the other ends of the any two or more of the plurality of second connection portions being respectively connected to the second capacitance electrodes of different capacitance elements of the plurality of capacitance elements, the plurality of capacitance elements including two or more capacitance elements each having the second capacitance electrode connected to an input terminal without passing through any one of the second capacitance electrodes of the plurality of capacitance elements, the input terminal inputting a signal for providing a potential to the second capacitance electrode.

[0030] [Item 9]

[0031] The display panel according to any one of items 5 to 8, wherein the dummy capacitor portion further includes a conductive layer formed opposite to the first capacitor electrode of the plurality of capacitor elements with the insulating layer interposed therebetween, on a side opposite to the second capacitor electrode of the first capacitor electrode, and electrically connected to the first capacitor electrode, the conductive layer having at least one second opening portion overlapping with the at least one first connection portion and the at least one second connection portion.

[0032] [Item 10]

[0033] The display panel according to item 9, wherein the conductive layer is formed of a transparent conductive material.

[0034] [Item 11]

[0035] The display panel according to item 9 or 10, wherein the conductive layer is formed of the same conductive film as a pixel electrode provided in each of the plurality of pixels.

[0036] [Item 12]

[0037] The display panel according to any one of items 1 to 11, wherein one of a signal providing a low potential and a scan signal selecting any one of the plurality of pixel rows is supplied to the first capacitor electrode, and the other of the signal providing the low potential and the scan signal selecting any one of the plurality of pixel rows is supplied to the second capacitor electrode.

[0038] [Item 13]

[0039] The display panel according to any one of items 1 to 12, having: a substrate; a gate metal layer supported by the substrate; the dielectric layer covering the gate metal layer; and a source metal layer formed on the dielectric layer, the first capacitor electrode being included in one of the gate metal layer and the source metal layer, and the second capacitor electrode being included in the other of the gate metal layer and the source metal layer.

[0040] [Item 14]

[0041] A defect correction method of the display panel according to any one of items 1 to 13, wherein, when insulating breakdown occurs in any one of the plurality of capacitor elements, the first connection portion connected at one end to the first capacitor electrode of the capacitor element in which insulating breakdown has occurred is cut off.

[0042] [Item 15]

[0043] A defect correction method is a defect correction method of the display panel according to any one of items 4 to 8, and when insulation breakdown has occurred in any one of the plurality of capacitive elements, a portion of the first connection portion that overlaps with the first opening portion is cut off at one end connected to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred.

[0044] [Item 16]

[0045] A defect correction method is a defect correction method of the display panel according to any one of items 5 to 8, and when insulation breakdown has occurred in any one of the plurality of capacitive elements, the first connection portion is cut off at one end connected to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred, or the second connection portion is cut off at one end connected to the second capacitive electrode of the capacitive element in which insulation breakdown has occurred.

[0046] [Item 17]

[0047] A defect correction method is a defect correction method of the display panel according to any one of items 5 to 8, and when insulation breakdown has occurred in any two of the plurality of capacitive elements, the first connection portion is cut off at one end connected to the first capacitive electrode of one of the two capacitive elements in which insulation breakdown has occurred, and the second connection portion is cut off at one end connected to the second capacitive electrode of the other of the two capacitive elements in which insulation breakdown has occurred.

[0048] [Item 18]

[0049] A defect correction method is a defect correction method of the display panel according to any one of items 9 to 11, and when insulation breakdown has occurred in any one of the plurality of capacitive elements, the first connection portion is cut off at one end connected to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred.

[0050] [Item 19]

[0051] A manufacturing method of a display panel includes a process of correcting a defect of the display panel using the defect correction method according to any one of items 14 to 18.

[0052] Advantageous Effects

[0053] According to the embodiment of the present application, a display panel in which reduction in manufacturing yield is suppressed, a defect correction method of such a display panel, and a manufacturing method of a display panel using the defect correction method are provided. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1is a schematic diagram showing the configuration of the display device 1100a having the display panel 1000a according to the first embodiment of the present application.

[0055] Figure 2 is a schematic plan view of the display device 1100a.

[0056] Figure 3 is a schematic plan view of the display panel 1000a, and is a plan view schematically showing the peripheral area NA of the display panel 1000a.

[0057] Figure 4A is a schematic plan view of the display panel 1000a, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000a.

[0058] Figure 4B is a schematic plan view for explaining one example of the defect correction method of the display panel 1000a, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000a.

[0059] Figure 5A is a schematic plan view of the display panel 1000b according to the second embodiment of the present application, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000b.

[0060] Figure 5B is a schematic plan view for explaining one example of the defect correction method of the display panel 1000b, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000b.

[0061] Figure 5C is a schematic plan view for explaining another example of the defect correction method of the display panel 1000b, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000b.

[0062] Figure 5D is a schematic plan view for explaining still another example of the defect correction method of the display panel 1000b, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000b.

[0063] Figure 6A is a schematic plan view of the display panel 1000b1 according to the modification of the second embodiment of the present application, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000b1.

[0064] Figure 6Bis a schematic plan view for explaining one example of a defect correction method of the display panel 1000b1, and is a plan view that schematically indicates a portion of the peripheral area NA of the display panel 1000b1.

[0065] Figure 7A is a schematic plan view of the display panel 1000c of the third embodiment of the present application, and is a plan view that schematically indicates a portion of the peripheral area NA of the display panel 1000c.

[0066] Figure 7B is a schematic cross-sectional view of the virtual capacitor portion CA of the display panel 1000c for explaining one example of a defect correction method of the display panel 1000c.

[0067] Figure 7C is a schematic plan view for explaining one example of a defect correction method of the display panel 1000c, and is a plan view that schematically indicates a portion of the peripheral area NA of the display panel 1000c.

[0068] Figure 7D is a schematic cross-sectional view of the virtual capacitor portion CA of the display panel 1000c for explaining one example of a defect correction method of the display panel 1000c. DETAILED DESCRIPTION

[0069] Embodiments of the present application will be described below with reference to the accompanying drawings. Note that a liquid crystal display panel is described below as an example of a display panel in the embodiments of the present application, but the present application is not limited to the embodiments below and can be applied to an active matrix display panel such as an organic EL display device. In the drawings used in the following embodiments, components having substantially the same function are denoted with common reference numerals, and the description thereof is omitted in some cases.

[0070] (First Embodiment)

[0071] Reference Figure 1 , Figure 2 and Figure 4A , a liquid crystal display panel 1000a and a liquid crystal display device 1100a including the liquid crystal display panel 1000a (hereinafter, referred to as "display panel 1000a" and "display device 1100a" in some cases) of the present embodiment are described. Figure 1 is a schematic view showing the configuration of the display device 1100a. Figure 2 is a schematic plan view of the display device 1100a. Figure 3 is a schematic plan view showing a portion of the display panel 1000a. Figure 4A is a schematic plan view showing a portion of the peripheral area NA of the display panel 1000a.

[0072] As Figure 1 and Figure 2As shown, the display panel 1000a has multiple pixels P arranged in a matrix with multiple pixel rows and multiple pixel columns. Each pixel P has a TFT (thin-film transistor) 1 and a pixel electrode 5 electrically connected to the TFT 1. The pixel rows are along the row direction (…). Figure 2 Multiple pixels P arranged in the X direction, the pixel column is along the column direction ( Figure 2 The display panel 1000a has a plurality of pixels P arranged in the Y direction. The display panel 1000a has a TFT substrate 101 and a counter substrate 201 facing each other, and a liquid crystal layer disposed between these substrates. The display panel 1000a has a display area AA defined by the plurality of pixels P and a peripheral area NA outside the display area AA. The peripheral area NA includes a first peripheral area NA1 located further outward in the row direction than the display area AA and a second peripheral area NA2 located further outward in the column direction than the display area AA. The display device 1100a has the display panel 1000a and a circuit board 510 connected to the display panel 1000a.

[0073] In this example, the gate bus GL is associated with multiple pixel rows, and the source bus SL is associated with multiple pixel columns. The TFT1 of each pixel P receives its gate signal from the corresponding gate bus GL and its source signal from the corresponding source bus SL. The pixel rows are sequentially designated as row 1, row 2, ..., row rx from top to bottom. The gate bus associated with the pixel row r (1 ≤ r ≤ rx) is denoted as gate bus GL(r) (see reference). Figure 1 Here, rx is the number of pixel rows in the display panel 1000a. Pixels in the r-th pixel row are selected by a scan signal voltage supplied to the gate bus GL(r). The gate bus GL(r) associated with the r-th pixel row is connected to the gate of the TFT connected to the pixels contained in the r-th pixel row. Pixel columns are sequentially designated from left to right as the first column, second column, ..., qy-th column. Sometimes, the source bus SL associated with the q-th pixel column is referred to as the source bus SL(q). Here, qy is the number of pixel columns in the display panel 1000a. Display signal voltages are supplied from the source bus SL(q) to the pixels in the q-th pixel column (1≤q≤qy). The source bus SL(q) associated with the q-th pixel column is connected to the source of the TFT connected to the pixels contained in the q-th pixel column.

[0074] The display panel 1000a has a gate driver circuit GD. Here, the gate driver circuit GD is integrally formed on the TFT substrate 101 (gate driver monolithic). The gate driver circuit GD is provided in the first peripheral region NA1 of the display panel 1000a, and includes a shift register 110 having a plurality of stages (sometimes referred to as "drive stages") corresponding to a plurality of pixel rows. The output of each drive stage of the shift register 110 is connected to a gate bus line GL associated with a plurality of pixel rows. Typically, the shift register 110 has rx drive stages, and if the stages are sequentially set as a first stage, a second stage,..., and an rxth stage from the top, the output of an rth stage (1≤r≤rx) is connected to a gate bus line GL(r). The shift register 110 has, in addition to the rx drive stages, one or more dummy stages adjacent to the rx drive stages in the column direction, which do not contribute to display. In this example, a plurality of dummy stages are provided on both the upper and lower sides of the rx drive stages. The dummy stages provided on the upper side of the drive stages (i.e., the preceding stages of the initial stages of the drive stages) are sequentially set as a u1th stage, a u2th stage from the top, and the dummy stages provided on the lower side of the drive stages (i.e., the succeeding stages of the final stages of the drive stages) are sequentially set as a d1th stage, a d2th stage from the top. The shift register 110 is configured by cascade connection of a plurality of unit circuits QC. Each stage (each of the drive stages and the dummy stages) of the shift register 110 is configured by each unit circuit QC. The unit circuit QC configuring each stage of the shift register 110 has at least one TFT. The drive stage of the rth stage (1≤r≤rx) is configured by a unit circuit QC(r), and the dummy stages of the u1th stage, the u2th stage, the d1th stage, and the d2th stage are configured by unit circuits QC(u1), QC(u2), QC(d1), and QC(d2), respectively. The number of dummy stages of the shift register 110 is not limited to the example shown in the drawing, and can be appropriately changed to a manner in which at least one dummy stage is provided on the upper side (the preceding stages of the initial stages of the drive stages) and / or the lower side (the succeeding stages of the final stages of the drive stages) of the drive stages.

[0075] Among the dummy stages of the shift register 110, the dummy stages provided on the upper side of the drive stages are each connected to a plurality of capacitor elements 40 connected in parallel provided in the virtual capacitor section CA provided in the peripheral region NA. Further, in this example, the dummy stages provided on the lower side of the drive stages among the dummy stages of the shift register 110 are each connected to a dummy bus line dL. The dummy bus line dL has, for example, a wiring resistance equivalent to that of the gate bus line GL. By connecting the virtual capacitor section CA or the dummy bus line dL to each of the dummy stages, a capacitance equivalent to a parasitic capacitance formed with the gate bus line GL is connected to each of the dummy stages. The load of the unit circuit QC of the dummy stage is designed to be equivalent to the load of the unit circuit QC of the drive stage. The load of each unit circuit QC of each stage of the shift register 110 is determined by the capacitance and resistance of the wiring connected to the unit circuit QC.

[0076] As Figure 4A shown, sometimes the virtual capacitor section CA has four capacitor elements 40a, 40b, 40c, and 40d connected in parallel (sometimes collectively referred to as "capacitor elements 40"). Here, the four capacitor elements 40a to 40d each include a first capacitor electrode CE1s, a second capacitor electrode CE2g, and a dielectric layer between the first capacitor electrode CE1s and the second capacitor electrode CE2g. The first capacitor electrodes CE1s of the four capacitor elements 40 are supplied with mutually identical potentials, and the second capacitor electrodes CE2g of the four capacitor elements 40 are supplied with mutually identical potentials. The first capacitor electrodes CE1s and the second capacitor electrodes CE2g are supplied with mutually different potentials. The first capacitor electrodes CE1s are supplied with, for example, a signal that provides a low-level potential VSS. The second capacitor electrodes CE2g are supplied with, for example, a scan signal Gout provided to the gate bus line GL.

[0077] The virtual capacitor section CA also has a plurality of first connection sections 46 (four first connection sections 46 in this case). Both ends of each first connection section 46 are connected to a first capacitor electrode CE1s of any one of the four capacitor elements 40 and a first capacitor electrode CE1s of any other one of the four capacitor elements 40. Here, both ends of each first connection section 46 are connected to the first capacitor electrodes CE1s of two adjacent capacitor elements 40. The first capacitor electrodes CE1s and the first connection sections 46 are formed of, for example, the same conductive film as the source bus line SL (i.e., included in the source metal layer). The second capacitor electrodes CE2g are provided in common among the plurality of capacitor elements 40. For example, the second capacitor electrodes CE2g are provided so as to at least partially overlap the first capacitor electrodes CE1s of the plurality of capacitor elements 40, respectively. The second capacitor electrodes CE2g are provided so as to be visible from the normal direction of the display panel 1000a when viewed from the normal direction of the display panel 1000a (i.e., the direction perpendicular to the display panel 1000a). Figure 4A), respectively, have a plurality of opening portions CHa (here, 3 opening portions CHa) overlapping any one of the four first connection portions 46. Of the four first connection portions 46, the first connection portion 46 having both ends connected to the first capacitance electrode CE1s of the capacitance element 40a and the first capacitance electrode CE1s of the capacitance element 40d has a portion not overlapping the second capacitance electrode CE2g, and thus does not need to be provided with an opening portion in the portion overlapping the second capacitance electrode CE2g. The second capacitance electrode CE2g is formed of, for example, the same conductive film as the gate bus line GL (i.e., included in the gate metal layer). The first connection portion 46 is, for example, preferably provided with a shape that is easily cut by irradiation of laser light. The first capacitance electrode CE1s and the second capacitance electrode CE2g of each capacitance element 40 preferably at least partially overlap. The first connection portion 46 has, for example, a smaller area than the first capacitance electrode CE1s provided, for example, in order to form a capacitance between the second capacitance electrode CE2g, when the display panel 1000a (or the TFT substrate 101) is viewed from the normal direction. The first connection portion 46 is, for example, a portion provided extending from the substantially rectangular first capacitance electrode CE1s, and can also be referred to as a portion provided protruding from the outer edge of the substantially rectangular first capacitance electrode CE1s. The first connection portion 46 is, for example, provided in a wiring shape, in other words, is a thin line connecting between two first capacitance electrodes CE1s, and is a shape having a small width with respect to the length of the line. Both ends of the first connection portion 46 are, for example, located on the outer edge of the two first capacitance electrodes CE1s.

[0078] A defect correction method of the display panel 1000a will be described with reference to Figure 4B When an insulation breakdown Lx occurs in one of the plurality of (here, four) capacitance elements 40 connected in parallel, the first connection portion 46 having one end connected to the first capacitance electrode CE1s of the capacitance element 40 in which the insulation breakdown Lx has occurred is cut. Typically, the first connection portion 46 having one end connected to the first capacitance electrode CE1s of the capacitance element 40 in which the insulation breakdown Lx has occurred is entirely cut. Specifically, for example, as shown in FIG. 14, the first connection portion 46 having one end connected to the first capacitance electrode CE1s of the capacitance element 40 in which the insulation breakdown Lx has occurred is cut by irradiation of laser light. Figure 4BAs shown, the first connecting portion 46 connected to the first capacitance electrode CE1s of the capacitance element 40b in which insulation breakdown has occurred and the first capacitance electrode CE1s of the other capacitance element 40a is cut (cutting site CPA), and the first connecting portion 46 connected to the first capacitance electrode CE1s of the capacitance element 40b in which insulation breakdown has occurred and the first capacitance electrode CE1s of the other capacitance element 40c is cut (cutting site CPB). The first connecting portion 46 is cut, for example, by irradiation of laser, thereby cutting at the cutting sites CPA and CPB. At this time, the portion of the first connecting portion 46 overlapping with the opening portion CHa of the second capacitance electrode CE2g is cut, and thus the influence on the second capacitance electrode CE2g is suppressed. In this way, in the manufacturing process of the display panel 1000a, when insulation breakdown has occurred in any one of the capacitance elements 40, by electrically separating the first capacitance electrode CE1s of the capacitance element 40b in which insulation breakdown has occurred from the first capacitance electrodes CE1s of the other capacitance elements 40a, 40c, and 40d, the defect of the display panel 1000a can be corrected. If the display panel 1000a and the defect correction method of the display panel 1000a are used, the reduction in the manufacturing yield of the display panel 1000a can be suppressed. The insulation breakdown of the capacitance element 40 includes, for example, a case where a short circuit (leakage) between the first capacitance electrode CE1s and the second capacitance electrode CE2g is generated due to the mixing of foreign matter, the formation failure of the insulating film (dielectric layer), an electro-static discharge (ESD) based on static electricity from the outside, or the like.

[0079] The display panel 1000a does not need to provide a dummy bus for connection with at least a part of the dummy stage of the shift register 110 in the peripheral region, and thus can contribute to narrow bezel.

[0080] Here, the source metal layer is disposed on the gate metal layer. That is, the TFT substrate 101 of the display panel 1000a has a substrate, a gate metal layer supported by the substrate, a dielectric layer (gate insulating layer) covering the gate metal layer, and a source metal layer formed on the dielectric layer. Here, an example is described in which the source metal layer includes a first capacitor electrode CE1s and a first connection portion 46, and the gate metal layer includes a second capacitor electrode CE2g, but the embodiments of the present invention are not limited to this example. The first capacitor electrode CE1s and the first connection portion 46 may be included in the gate metal layer, and the second capacitor electrode CE2g may be included in the source metal layer. In this case, a scan signal Gout, for example, supplied to the gate bus GL, is supplied to the first capacitor electrode CE1s, and a signal, for example, providing a low-level potential VSS, is supplied to the second capacitor electrode CE2g. Furthermore, in such a defect correction method for the display panel, the portion of the first connection portion 46 (gate metal layer) that overlaps with the opening CHa of the second capacitor electrode CE2g (source metal layer) can be cut off from the gate insulating layer. From the perspective of reducing manufacturing costs, it is preferable that the first capacitor electrode CE1s is contained in one of the gate metal layer and the source metal layer, and the second capacitor electrode CE2g is contained in the other of the gate metal layer and the source metal layer.

[0081] The structure of the display panel 1000a and the display device 1100a will be described in further detail.

[0082] like Figure 2 As shown, the circuit board 510 includes a control circuit CNTL that supplies control signals to the gate drive circuit GD. For example, the control circuit CNTL is mounted on the circuit board 510. The circuit board 510 is connected to a terminal portion TP formed in the second peripheral region NA2 of the display panel 1000a via a source substrate 520. The circuit board 510 is connected to the source substrate 520 via a flexible printed circuit (FPC) 512. Terminals electrically connected to the trunk lines for supplying signals to the gate drive circuit GD are provided on the terminal portion TP. The circuit board 510 provides signals from the terminal portion TP of the display panel 1000a to the trunk lines for supplying signals to the gate drive circuit GD via the source substrate 520. In this example, the circuit board 510 is connected to the display panel 1000a via multiple source substrates 520. The source substrate 520 (printed wiring substrate) is connected to the display panel 1000a via multiple flexible circuit boards 522, and the source drive circuit SD, which provides display signal voltage to the source bus SL, is mounted on the flexible circuit board 522. Additionally, in Figure 2In the drawing, the illustration of the source bus line SL is omitted for easy observation. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. The control signal supplied by the control circuit CNTL to the gate driver circuit GD includes a gate start pulse signal GSP, a gate clock signal GCK, and a gate end pulse signal GEP, for example. The control signal supplied by the control circuit CNTL to the source driver circuit SD includes a source start pulse signal SSP and a source clock signal SCK, for example. Note that the configuration and connection method of the source driver circuit SD and the control circuit CNTL are not limited to the illustrated manner. Note that in Figure 2 In the drawing, the illustration of the source bus line SL is omitted for easy observation. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. The control circuit CNTL supplies a control signal to the gate driver circuit GD, for example. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. Note that the configuration and connection method of the source driver circuit SD and the control circuit CNTL are not limited to the illustrated manner. Note that in

[0083] In the drawing, the illustration of the source bus line SL is omitted for easy observation. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. The control circuit CNTL supplies a control signal to the gate driver circuit GD, for example. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. Note that the configuration and connection method of the source driver circuit SD and the control circuit CNTL are not limited to the illustrated manner. Note that in Figure 3 In the drawing, the illustration of the source bus line SL is omitted for easy observation. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. The control circuit CNTL supplies a control signal to the gate driver circuit GD, for example. The control circuit CNTL supplies a control signal to the source driver circuit SD, for example. Note that the configuration and connection method of the source driver circuit SD and the control circuit CNTL are not limited to the illustrated manner. Note that in

[0084] As the n clock trunks CKL1 to CKLn, in Figure 3In the example of FIG. 10A, eight clock trunks CKL1 to CKL8 (n = 8) are provided. When gate clock signals GCK supplied from the clock trunks CKL1 to CKL8 are set as GCK1 to GCK8, the gate clock signals GCK1 to GCK8 are, for example, oscillating voltages having a period of 8H (1H is 1 horizontal scanning period), a duty ratio of 1 : 1 (4H of 8H of 1 period is high, and 4H is low), and a phase difference of 1H. For example, the low potential Vgl = -7V, and the high potential Vgh = 35V. Terminals (8 clock trunk terminals) electrically connected to the clock trunks CKL1 to CKL8 are provided in the terminal portion TP of the second peripheral area NA2 of the display panel 1000a, and the gate clock signals GCK1 to GCK8 are supplied to the clock trunks CKL1 to CKL8 connected from the control circuit CNTL via the clock trunk terminals. The clock trunks CKL1 to CKL8 and the inputs (input terminals) of the stages of the shift register 110 are electrically connected via the wiring 154 extending in the row direction, and thus the gate clock signals GCK1 to GCK8 are supplied to the inputs of the stages of the shift register 110. An example of the connection relationship between the inputs of the stages of the shift register 110 and the n clock trunks CKL1 to CKLn is described below. For example, the gate clock signals GCK1 to GCK8 are supplied to the inputs of the first to eighth stages from the clock trunks CKL1 to CKL8, the gate clock signals GCK1 to GCK8 are supplied to the inputs of the ninth to sixteenth stages from the clock trunks CKL1 to CKL8, the gate clock signals GCK1 to GCK8 are supplied to the inputs of the seventeenth to twenty-fourth stages from the clock trunks CKL1 to CKL8, and so on. That is, the gate clock signal GCKk is supplied to the input of the {(a x n) + k} stage of the shift register 110 from the clock trunk CKLk (here, a is an integer of 0 or more, and k is an integer of 0 or more and n - 1 or less).

[0085] The outer trunk 122 and the inner trunk 124 are, for example, used to supply a signal providing a low potential (for example, VSS = -7V) to the plurality of stages of the shift register 110. The outer trunk 122 connected from the control circuit CNTL via the outer trunk terminal is supplied with a signal providing a fixed potential (for example, a signal providing a low potential VSS). The outer trunk 122 and the inner trunk 124 are electrically connected via the branch 140, and the inner trunk 124 and the inputs (input terminals) of the stages of the shift register 110 are electrically connected via the wiring 152, and thus a signal providing a low potential VSS is supplied to the inputs of the stages of the shift register 110.

[0086] The display panel 1000a can further have other trunks 121 provided in the first peripheral area NA1, extending in the column direction, and supplying a common other signal to a plurality of stages of the shift register 110. In this case, a signal supplying two kinds of low potential (e.g., VSS1 = -12 V, VSS2 = -7 V) is supplied from the control circuit CNTL. The outer trunk 122 and the inner trunk 124 supply a signal supplying the low potential VSS2 to the plurality of stages of the shift register 110, and the trunk 121 supplies a signal supplying the low potential VSS1 to the plurality of stages of the shift register 110.

[0087] In addition, the outer trunk 122 and the inner trunk 124 can also supply, for example, a signal VD supplying a high potential (which can be different from Vgh) to the plurality of stages of the shift register 110. The outer trunk 122 connected to the control circuit CNTL via the outer trunk terminal can also be supplied with the signal VD supplying the high potential.

[0088] In this example, the inner trunk 124 is disposed farther from the display area AA than the shift register 110, and the outer trunk 122 is disposed farther from the display area AA than the inner trunk 124. Eight clock trunks CKL1 to CKL8 are provided between the outer trunk 122 and the inner trunk 124. The width of the row direction of the outer trunk 122 is typically larger than the width of the row direction of the inner trunk 124.

[0089] The display panel 1000a further has a first trunk 132 and a second trunk 134 for supplying signals to the plurality of stages of the shift register 110, respectively. The first trunk 132 and the second trunk 134 supply, for example, a reset signal to each stage of the shift register 110. As the reset signal, a gate start pulse signal GSP and / or a gate end pulse signal GEP can also be used. The first trunk 132 is provided in the first peripheral area NA1 and supplies a common signal to one or a plurality of stages of a first type included in the plurality of stages. The second trunk 134 is provided between the first trunk 132 and the display area AA and supplies a common other signal to one or a plurality of stages of a second type included in the plurality of stages. The first trunk 132 and the second trunk 134 extend in the column direction. Since the first trunk 132 and the second trunk 134 are electrically independent, it is possible to supply mutually different signals to the stages of the first type and the stages of the second type.

[0090] (Second Embodiment)

[0091] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D A display panel 1000b of the present embodiment and a defect correction method thereof will be described. Figure 5Ais a schematic plan view of the display panel 1000b, and is a plan view schematically showing a part of the peripheral area NA. Figure 5B , Figure 5C and Figure 5D are schematic plan views for explaining a defect correction method of the display panel 1000b. Hereinafter, points different from the previous embodiment will be mainly explained.

[0092] In the display panel 1000a, the second capacitance electrode CE2g is commonly provided over the plurality of capacitance elements 40, but in the display panel 1000b, four second capacitance electrodes CE2g are provided in a manner corresponding to the four capacitance elements 40 respectively. In the display panel 1000b, the virtual capacitance portion CA also has a plurality of second connection portions 42 (four second connection portions 42 in this case). Both ends of each second connection portion 42 are connected to any one of the second capacitance electrodes CE2g of the four capacitance elements 40 and to any other of the second capacitance electrodes CE2g of the four capacitance elements 40. Here, both ends of each second connection portion 42 are connected to the second capacitance electrodes CE2g of two adjacent capacitance elements 40. Each second connection portion 42 is provided so as not to overlap any of the first connection portions 46 when viewed in the normal direction of the display panel 1000b (). Figure 5A ), the same as the first connection portions 46 and the first capacitance electrodes CE1s.

[0093] Referring to Figure 5B and Figure 5C , one example of a defect correction method of the display panel 1000b will be explained. When insulation breakdown Lx occurs in one of the plurality of capacitance elements 40d connected in parallel, the defect can be corrected by cutting off the first connection portion 46 having one end connected to the first capacitance electrode CE1s of the capacitance element 40d in which insulation breakdown has occurred, or by cutting off the second connection portion 42 having one end connected to the second capacitance electrode CE2g of the capacitance element 40d in which insulation breakdown has occurred. Typically, all of the first connection portions 46 having one end connected to the first capacitance electrode CE1s of the capacitance element 40d in which insulation breakdown has occurred are cut off, or all of the second connection portions 42 having one end connected to the second capacitance electrode CE2g of the capacitance element 40d in which insulation breakdown has occurred are cut off. Specifically, for example, as shown in Figure 5B , the first connection portion 46 having both ends connected to the first capacitance electrode CE1s of the capacitance element 40d in which insulation breakdown has occurred and the first capacitance electrode CE1s of the other capacitance element 40c is cut off (cut-off portion CPa), and the first connection portion 46 having both ends connected to the first capacitance electrode CE1s of the capacitance element 40d in which insulation breakdown has occurred and the first capacitance electrode CE1s of the other capacitance element 40a is cut off (cut-off portion CPb). Or, as shown inFigure 5C The second connection portion 42 connecting both ends of the second capacitor electrode CE2g of the capacitor element 40d in which insulation breakdown has occurred and the second capacitor electrode CE2g of the other capacitor element 40c (cut portion CPa) and the second connection portion 42 connecting both ends of the second capacitor electrode CE2g of the capacitor element 40d in which insulation breakdown has occurred and the second capacitor electrode CE2g of the other capacitor element 40a (cut portion CPb) are cut. The insulation breakdown of the two capacitor elements 40 can be detected by Figure 5B Alternatively Figure 5C the defective display panel 1000b can be corrected by any one of the defect correction methods of Figure 5B the defective display panel 1000b can be corrected by any one of the defect correction methods of Figure 5C the defective display panel 1000b can be corrected by any one of the defect correction methods of

[0094] Another example of the defect correction method of the display panel 1000b will be described with reference to Figure 5D The defective display panel 1000b can be corrected even when insulation breakdown has occurred in two of the plurality of capacitor elements 40, and thus the reduction in manufacturing yield can be effectively suppressed compared with the display panel 1000a. When insulation breakdown has occurred in any two (here, the capacitor elements 40d and 40b) of the plurality of capacitor elements 40 connected in parallel, the first connection portion 46 (typically, all) connecting one end of the first capacitor electrode CE1s of one of the two capacitor elements in which insulation breakdown has occurred is cut, and the second connection portion 42 (typically, all) connecting one end of the second capacitor electrode CE2g of the other of the two capacitor elements in which insulation breakdown has occurred is cut. Specifically, for example, the following four portions are cut.

[0095] • The first connection portion 46 connecting both ends of the first capacitor electrode CE1s of one of the two capacitor elements 40d in which insulation breakdown has occurred and the first capacitor electrode CE1s of any one of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred (cut portion CPa) is cut.

[0096] • The first connection portion 46 connecting both ends of the first capacitor electrode CE1s of one of the two capacitor elements 40d in which insulation breakdown has occurred and the first capacitor electrode CE1s of any one of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred (cut portion CPb) is cut.

[0097] • The second connecting portion 42 (cut portion CPc) that connects the second capacitance electrode CE2g of the other one of the two capacitance elements 40b in which insulation breakdown has occurred and the second capacitance electrode CE2g of any one of the four capacitance elements 40 other than the two capacitance elements in which insulation breakdown has occurred.

[0098] • The second connecting portion 42 (cut portion CPd) that connects the second capacitance electrode CE2g of the other one of the two capacitance elements 40b in which insulation breakdown has occurred and the second capacitance electrode CE2g of the other one of the four capacitance elements 40 other than the two capacitance elements in which insulation breakdown has occurred.

[0099] Since the display panel 1000b satisfies (1) and (2) below, in the case where insulation breakdown has occurred in any two of the plurality of (here, four) capacitance elements 40, defects can be corrected.

[0100] (1) With respect to each of the four first capacitance electrodes CE1s, there are two or more paths of electrical conduction from an input end (the front end of the arrow of "VSS" of the figure) of a signal that inputs a potential to the first capacitance electrode CE1s to each of the four first capacitance electrodes CE1s. Here, the "path" can include other first capacitance electrodes CE1s in addition to the one or more first connecting portions 46.

[0101] (2) With respect to each of the four second capacitance electrodes CE2g, there are two or more paths of electrical conduction from an input end (the front end of the arrow of "Gout" of the figure) of a signal that inputs a potential to the second capacitance electrode CE2g to each of the four second capacitance electrodes CE2g. Here, the "path" can include other second capacitance electrodes CE2g in addition to the one or more second connecting portions 42.

[0102] It is preferable to satisfy both of the above (1) and (2), but it is also possible to satisfy only either one. In order to satisfy the above (1), it is preferable to satisfy (3a) and (3b) below, and in order to satisfy the above (2), it is preferable to satisfy (4a) and (4b) below.

[0103] (3a) The first capacitance electrodes CE1s of the four capacitance elements 40 are each connected to one end of any two or more of the four first connection portions 46, and the other ends of the any two or more of the four first connection portions 46 are respectively connected to the first capacitance electrodes CE1s of different ones of the four capacitance elements 40. In other words, the first capacitance electrodes CE1s of the four capacitance elements 40 are each connected to one end of two or more of the first connection portions 46, and the other ends of the two or more of the first connection portions 46 are connected to the first capacitance electrodes CE1s of mutually different capacitance elements 40.

[0104] (3b) The four capacitance elements 40 include two or more capacitance elements each having a first capacitance electrode CE1s connected to an input terminal (the leading end of the arrow of "VSS" in the figure) that inputs a signal that supplies a potential to the first capacitance electrode CE1s, without passing through the first capacitance electrode CE1s of another capacitance element. In Figures 5A to 5D In the example of FIG. 6, the capacitance elements 40a and 40d are connected to the input terminal that inputs the signal that supplies the potential to the first capacitance electrode CE1s, without passing through the first capacitance electrode CE1s of another capacitance element.

[0105] (4a) The second capacitance electrodes CE2g of the four capacitance elements 40 are each connected to one end of any two or more of the four second connection portions 42, and the other ends of the any two or more of the four second connection portions 42 are respectively connected to the second capacitance electrodes CE2g of different ones of the four capacitance elements 40. In other words, the second capacitance electrodes CE2g of the four capacitance elements 40 are each connected to one end of two or more of the second connection portions 42, and the other ends of the two or more of the second connection portions 42 are connected to the second capacitance electrodes CE2g of mutually different capacitance elements 40.

[0106] (4b) The four capacitance elements 40 include two or more capacitance elements each having a second capacitance electrode CE2g connected to an input terminal (the leading end of the arrow of "Gout" in the figure) that inputs a signal that supplies a potential to the second capacitance electrode CE2g, without passing through the second capacitance electrode CE2g of another capacitance element. In Figures 5A to 5D In the example of FIG. 6, the capacitance elements 40c and 40d are connected to the input terminal that inputs the signal that supplies the potential to the second capacitance electrode CE2g, without passing through the second capacitance electrode CE2g of another capacitance element.

[0107] (Modified Example)

[0108] Referring to Figure 6A and Figure 6B , a display panel 1000b1 of a modified example of the present embodiment and a defect correction method thereof are described. Figure 6Ais a schematic plan view of the display panel 1000b1, and is a plan view schematically showing a part of the peripheral area NA. Figure 6B is a schematic plan view for explaining a defect correction method of the display panel 1000b1.

[0109] The display panel 1000b1 is different from the display panel 1000b in that the virtual capacitor section CA has six capacitor elements 40 connected in parallel. Since the display panel 1000b1 satisfies both of the above (1) and (2), in the case where insulation breakdown occurs in any two of the six capacitor elements 40, the defect can be corrected by the same method as the defect correction method explained with reference to Figure 5A and Figure 5B the same method as the defect correction method explained above. It can be said that the same applies to the number of capacitor elements 40 connected in parallel that the virtual capacitor section CA has, which is five or more than seven. Specifically, for example, as shown in Figure 6B , the following four sections are cut. • The first connecting section 46 (cut section CPc) that connects one capacitor element 40c of the two ends of the first capacitor electrode CE1s of the one capacitor element 40c and the first capacitor electrode CE1s of any one capacitor element 40b of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred is cut.

[0110] • The first connecting section 46 (cut section CPd) that connects one capacitor element 40c of the two ends of the first capacitor electrode CE1s of the one capacitor element 40c and the first capacitor electrode CE1s of another capacitor element 40d of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred is cut.

[0111] • The second connecting section 42 (cut section CPA) that connects the second capacitor electrode CE2g of the other capacitor element 40f of the two ends of the second capacitor electrode CE2g of the other capacitor element 40f and the second capacitor electrode CE2g of any one capacitor element 40e of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred is cut.

[0112] • The second connecting section 42 (cut section CPB) that connects the second capacitor electrode CE2g of the other capacitor element 40f of the two ends of the second capacitor electrode CE2g of the other capacitor element 40f and the second capacitor electrode CE2g of another capacitor element 40a of the four capacitor elements 40 other than the two capacitor elements in which insulation breakdown has occurred is cut.

[0113] (Third Embodiment)

[0114] With reference to Figure 7A , Figure 7B ,Figure 7C and Figure 7D A display panel 1000c and a defect correction method thereof according to the present embodiment will be described. FIG. 7 is a schematic plan view of the display panel 1000c, and is a plan view schematically showing a part of the peripheral area NA. Figure 7B is a schematic cross-sectional view for illustrating a virtual capacitor portion CA of the display panel 1000c. Figure 7C is a schematic plan view for illustrating one example of a defect correction method of the display panel 1000c, and is a plan view schematically showing a part of the peripheral area NA of the display panel 1000c. Figure 7D is a schematic cross-sectional view of the virtual capacitor portion CA of the display panel 1000c for illustrating one example of a defect correction method of the display panel 1000c. Hereinafter, points different from the previous embodiment will be mainly described.

[0115] The display panel 1000c is different from the display panel 1000b in that the display panel 1000c further has an interlayer insulating layer 15 covering the plurality of capacitor elements 40, and a transparent conductive layer 16 formed on the interlayer insulating layer 15. The transparent conductive layer 16 is electrically connected to the first capacitor electrode CE1s in the contact portion CHc. The transparent conductive layer 16 has an opening portion CHb overlapping the first connection portion 46 and the second connection portion 42, as viewed from the normal direction of the display panel 1000c (FIG. 7). Figure 7A The transparent conductive layer 16 is, for example, an ITO layer, and is formed of, for example, the same transparent conductive film as the pixel electrode 5 provided on each pixel P. The transparent conductive layer 16 is not limited to a conductive layer formed of a transparent conductive material, but can be another conductive layer. As shown in FIG. 6, the transparent conductive layer 16 is provided on the gate metal layer 12 including the second capacitor electrode CE2g, the source metal layer 14 including the first capacitor electrode CE1s, and the dielectric layer 13 (e.g., a gate insulating layer) therebetween, with the interlayer insulating layer 15 interposed therebetween. Figure 7B

[0116] Referring to Figure 7C and Figure 7D , one example of a defect correction method of the display panel 1000c will be described. When insulation breakdown Lx occurs in one of the plurality of capacitor elements 40b connected in parallel, the first connection portion 46 connected at one end to the first capacitor electrode CE1s of the capacitor element 40b in which the insulation breakdown has occurred is cut. Typically, the first connection portion 46 connected at one end to the first capacitor electrode CE1s of the capacitor element 40b in which the insulation breakdown has occurred is entirely cut. Specifically, for example, as shown in FIG. 8, the first connection portion 46 connected at one end to the first capacitor electrode CE1s of the capacitor element 40b in which the insulation breakdown has occurred is cut. Figure 7C ​As shown, the first connecting portion 46 at both ends of the first capacitance electrode CEl s of the capacitance element 40b in which insulation breakdown has occurred and the first capacitance electrode CEl s of the other capacitance element 40a is cut (cutting site CPA), and the first connecting portion 46 at both ends of the first capacitance electrode CEl s of the capacitance element 40b in which insulation breakdown has occurred and the first capacitance electrode CEl s of the other capacitance element 40c is cut (cutting site CPB). The display panel 1000c can suppress reduction in manufacturing yield. At this time, in the capacitance element 40b in which insulation breakdown has occurred, since the first capacitance electrode CEl s and the second capacitance electrode CE2g are in conduction, after the first connecting portion 46 is cut, the potential of the first capacitance electrode CEl s of the capacitance element 40b is equal to the potential of the second capacitance electrode CE2g (for example, Gout). On the other hand, the transparent conductive layer 16 is electrically connected to the first capacitance electrode CEl s, and thus the potential of the transparent conductive layer 16 is equal to the potential of the first capacitance electrode CEl s (for example, VSS). Thus, the capacitance 50 is formed by the first capacitance electrode CEl s of the capacitance element 40b in which insulation breakdown has occurred, the transparent conductive layer 16, and the interlayer insulating layer 15 therebetween. By forming the capacitance 50, it is possible to reduce the influence of separation of the capacitance element 40b in which insulation breakdown has occurred.

[0117] Here, the case where the first capacitance electrode CEl s and the first connecting portion 46 are included in the source metal layer, and the second capacitance electrode CE2g is included in the gate metal layer, that is, the case where the first capacitance electrode CEl s is disposed on the second capacitance electrode CE2g, is described, but the second capacitance electrode CE2g can be disposed on the first capacitance electrode CEl s. In this case, the conductive layer electrically connected to the first capacitance electrode CEl s is located on the opposite side of the first capacitance electrode CEl s from the second capacitance electrode CE2g, with the insulating layer interposed therebetween. That is, the conductive layer is located below the first capacitance electrode CEl s with the insulating layer interposed therebetween. Even in this case, the same effects as the display panel 1000c can be obtained.

[0118] Industrial Applicability

[0119] The display panel of the embodiment of the present application is widely used for active matrix type display panels such as liquid crystal display panels and organic EL display panels. If the display panel of the embodiment of the present application is used, it is possible to improve the manufacturing yield of the active matrix type display panel. The defect correction method of the display panel of the embodiment of the present application can be used for the manufacturing method of the display panel.

[0120] Explanation of Reference Numerals

[0121] 40, 40a, 40b, 40c, 40d: capacitive element; 42: second connection portion; 46: first connection portion; CE1s: first capacitive electrode; CE2g: second capacitive electrode; 101: TFT substrate; 110: shift register; 201: counter substrate; 510: circuit substrate; 1000a, 1000b, 1000b1, 1000c: display panel; 1100a: display device.

Claims

1. A display panel having a plurality of pixels arranged in a matrix of a plurality of pixel rows and a plurality of pixel columns, having a display region defined by the plurality of pixels and a peripheral region outside the display region, further having: a gate driver circuit provided in the peripheral region, the gate driver circuit including a shift register having a plurality of stages corresponding to the plurality of pixel rows, respectively, and a dummy stage; and a dummy capacitor section provided in the peripheral region, the dummy capacitor section including a plurality of capacitor elements connected to the dummy stage and connected in parallel to each other, each of the plurality of capacitor elements including a first capacitor electrode, a second capacitor electrode, and a dielectric layer between the first capacitor electrode and the second capacitor electrode, the dummy capacitor section further including at least one first connection section each of which has both ends connected to the first capacitor electrode of any one of the plurality of capacitor elements and the first capacitor electrode of another one of the plurality of capacitor elements.

2. The display panel according to claim 1, wherein for each of the first capacitor electrodes of the plurality of capacitor elements, the dummy capacitor section has two or more paths from an input terminal to the first capacitor electrode of each of the plurality of capacitor elements, the input terminal inputting a signal that provides a potential to the first capacitor electrode.

3. The display panel according to claim 1, wherein the at least one first connection section includes a plurality of first connection sections, the first capacitor electrode of each of the plurality of capacitor elements is connected to one end of any two or more of the plurality of first connection sections, respectively, the other ends of the any two or more of the plurality of first connection sections being connected to the first capacitor electrodes of different capacitor elements of the plurality of capacitor elements, respectively, the plurality of capacitor elements includes two or more capacitor elements each having the first capacitor electrode connected to an input terminal without passing through the first capacitor electrode of any one of the plurality of capacitor elements, the input terminal inputting a signal that provides a potential to the first capacitor electrode.

4. The display panel of any one of claims 1-3, wherein, the second capacitor electrodes are commonly provided in the plurality of capacitor elements and have at least one first opening section overlapping the at least one first connection section.

5. The display panel according to any one of claims 1 to 3, wherein the dummy capacitor section further has at least one second connection section each of which has both ends connected to the second capacitor electrode of any one of the plurality of capacitor elements and the second capacitor electrode of another one of the plurality of capacitor elements.

6. The display panel according to claim 5, wherein the at least one second connection section is provided in a manner not overlapping the at least one first connection section.

7. The display panel according to claim 5, wherein For each of the second capacitor electrodes of the plurality of capacitor elements, the dummy capacitor portion has two or more paths from an input terminal to each of the second capacitor electrodes of the plurality of capacitor elements, the input terminal inputting a signal for providing a potential to the second capacitor electrodes.

8. The display panel according to claim 5, wherein the at least one second connection portion includes a plurality of second connection portions, the second capacitor electrode of each of the plurality of capacitor elements is connected to one end of each of any two or more of the plurality of second connection portions, and the other end of each of the any two or more of the plurality of second connection portions is connected to the second capacitor electrode of a different capacitor element among the plurality of capacitor elements, the plurality of capacitor elements includes two or more capacitor elements each having the second capacitor electrode connected to an input terminal without passing through the second capacitor electrode of any of the plurality of capacitor elements, the input terminal inputting a signal for providing a potential to the second capacitor electrodes.

9. The display panel according to claim 5, wherein the dummy capacitor portion further includes a conductive layer formed opposite to the first capacitor electrodes of the plurality of capacitor elements with an insulating layer interposed therebetween, on a side opposite to the second capacitor electrodes of the first capacitor electrodes, and electrically connected to the first capacitor electrodes, the conductive layer has at least one second opening portion overlapping the at least one first connection portion and the at least one second connection portion.

10. The display panel according to claim 9, wherein the conductive layer is formed of a transparent conductive material.

11. The display panel according to claim 9, wherein the conductive layer is formed of the same conductive film as a pixel electrode provided in each of the plurality of pixels.

12. The display panel according to any one of claims 1 to 3, wherein one of a signal for providing a low potential and a scan signal for selecting any one of the plurality of pixel rows is supplied to the first capacitor electrodes, the other of the signal for providing a low potential and the scan signal for selecting any one of the plurality of pixel rows is supplied to the second capacitor electrodes.

13. The display panel of any one of claims 1-3, wherein, having: a substrate; a gate metal layer supported by the substrate; the dielectric layer covering the gate metal layer; and a source metal layer formed on the dielectric layer, the first capacitor electrodes are included in one of the gate metal layer and the source metal layer, the second capacitor electrodes are included in the other of the gate metal layer and the source metal layer.

14. A defect correction method for the display panel according to any one of claims 1 to 3, wherein when insulation breakdown occurs in any of the plurality of capacitor elements, the first connection portion connected at one end to the first capacitor electrode of the capacitor element in which the insulation breakdown has occurred is cut off.

15. A defect correction method for the display panel according to claim 4, wherein When insulation breakdown occurs in any of the plurality of capacitive elements, a portion of the first connecting portion that overlaps with the first opening portion is cut off, the portion being connected at one end to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred.

16. A defect correction method according to claim 5, wherein, when insulation breakdown occurs in any of the plurality of capacitive elements, when insulation breakdown occurs in any of the plurality of capacitive elements, the first connecting portion connected at one end to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred is cut off, or the second connecting portion connected at one end to the second capacitive electrode of the capacitive element in which insulation breakdown has occurred is cut off.

17. A defect correction method according to claim 5, wherein, when insulation breakdown occurs in any two of the plurality of capacitive elements, when insulation breakdown occurs in any two of the plurality of capacitive elements, the first connecting portion connected at one end to the first capacitive electrode of one of the two capacitive elements in which insulation breakdown has occurred is cut off, the second connecting portion connected at one end to the second capacitive electrode of the other of the two capacitive elements in which insulation breakdown has occurred is cut off.

18. A defect correction method according to claim 9, wherein, when insulation breakdown occurs in any of the plurality of capacitive elements, when insulation breakdown occurs in any of the plurality of capacitive elements, the first connecting portion connected at one end to the first capacitive electrode of the capacitive element in which insulation breakdown has occurred is cut off.

19. A method for manufacturing a display panel, characterized by, including a step of correcting a defect of the display panel by the defect correction method according to claim 14.

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