A control circuit based on an FPGA SOC architecture, a liquid crystal screen and a picture control method

Abstract

The application provides a control circuit based on an FPGA SOC architecture, a liquid crystal screen and a picture control method, and relates to the field of electronic circuits.The control circuit comprises an SOC, an FPGA, an SD NAND, an SDRAM and a video encoder.The SOC, the FPGA, the video encoder and the liquid crystal screen are sequentially connected.The FPGA is connected with the SD NAND and the SDRAM respectively, and the SOC is connected with a bus driver.The application adopts the FPGA+SOC architecture, and when the SOC is down due to various reasons, the picture file indication information before the SOC is down can be displayed on the liquid crystal screen, so that the maintainability of the whole machine and the system is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuit, in particular to a control circuit based on FPGA SOC architecture, a liquid crystal screen and a picture control method. BACKGROUND

[0002] Generally, airborne (special) display adopts FPGA+SOC architecture to realize, and the SOC generates a graphic picture and sends it to the FPGA for processing, and then outputs it to the liquid crystal screen for display. Because the SOC has complicated processing tasks, it cannot completely avoid the occurrence of the dead machine phenomenon. When the SOC is dead, a simple and fixed character picture is generally displayed by the FPGA, and no information about the cause of the dead machine can be obtained from the picture, and the maintainability is low. SUMMARY

[0003] The present application provides a control circuit based on FPGA SOC architecture, a liquid crystal screen and a picture control method, when the SOC is down due to various reasons, the custom picture with key information before the SOC is down can be displayed on the liquid crystal screen, and the maintainability of the whole machine and system is increased.

[0004] In one aspect, the embodiment of the present application provides a control circuit based on FPGA SOC architecture, which further comprises a SOC, an FPGA, an SD NAND, an SDRAM, a video encoder, the SOC, the FPGA, the video encoder and the liquid crystal screen are connected in sequence, the FPGA is connected with the SD NAND and the SDRAM respectively, and the SOC is connected with a bus driver.

[0005] Preferably, the FPGA further comprises an SD NAND / SDRAM parameter calculation module, an SD NAND picture reading control module and an SDRAM controller, the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, a video output module and the video encoder are connected in sequence; the SDRAM controller is connected with the SDRAM; and the SD NAND controller is connected between the SD NAND picture reading control module and the SD NAND.

[0006] Preferably, the FPGA further comprises a clock module, and the clock module is connected with the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, the video output module respectively.

[0007] In another aspect, the embodiment of the present application further provides a picture control method using the control circuit based on FPGA SOC architecture, which comprises the following steps:

[0008] When the SOC is in standby or down, the FPGA does not detect the video signal output by the SOC, the control signal OE of the bus driver is closed, and the SD NAND is hung by the FPGA;

[0009] The picture file is read from the SD NAND through the SDIO bus and output to the liquid crystal screen through the video encoder.

[0010] Before the above-mentioned when the SOC is in standby or down, the FPGA does not detect the video signal output by the SOC, the control signal OE of the bus driver is closed, and the SD NAND is hung by the FPGA, it further comprises:

[0011] When the SOC is in a running state, the video signal is normally output to the FPGA, and after the FPGA completes the processing, the video signal is output to the liquid crystal screen through the video encoder.

[0012] Meanwhile, the FPGA opens the control signal OE of the bus driver, sets the SDIO bus to a high-impedance state, at this time, the SD NAND is hung by the SOC, and the SOC saves the picture file into the SD NAND in a timing manner.

[0013] In another aspect, the embodiment of the present application also provides a liquid crystal screen, which is provided with the control circuit based on the FPGA SOC architecture.

[0014] When the SOC works abnormally and is stuck, the picture file indication information saved before the SOC is stuck is output by the FPGA and displayed on the liquid crystal screen, the maintainability of the system is increased, and the flexibility is large and can meet various demands of customers on standby and down pictures. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0016] Figure 1 The hardware circuit schematic diagram of the embodiment of the present application.

[0017] Figure 2 The FPGA hanging SD NAND logic block diagram of the embodiment of the present application.

[0018] Figure 3 The flow chart of the picture control method based on the FPGA SOC architecture control circuit of the embodiment of the present application.

[0019] Figure 4This is another flowchart of the screen control method based on the FPGA SOC architecture described in the embodiment of the present invention. Detailed Implementation

[0020] The following describes in detail, with reference to the accompanying drawings, a method, apparatus, and server for processing user operation data according to an embodiment of the present invention.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] like Figure 1 As shown, a control circuit based on an FPGA SOC architecture further includes: SOC1, FPGA2, SD NAND3, SDRAM4, and video encoder5. SOC1, FPGA2, video encoder5, and an LCD screen are connected sequentially. FPGA2 is connected to both SD NAND3 and SDRAM4. A bus driver connects SOC1 to SD NAND3. SOC1 can use any mainstream platform such as NXP, Hisilicon, or Rockchip. FPGA2 can use any mainstream model from Altera or Xinlinx. SDRAM4 and video encoder5 can also use any mainstream model available on the market. The SD NAND3 uses the CSNP4GCR01-AMW from Shenzhen Leilong Development Co., Ltd. The CSNP4GCR01-AMW is a domestically produced NAND Flash (surface-mount TF card) with built-in bad block management, requiring no driver writing. It is compact, easy to use, highly compatible, stable, and reliable. Firmware is customizable. It features an LGA-8 package, a standard SDIO interface, and is compatible with SPI / SD interfaces and major MCU platforms. It can replace ordinary TF / SD cards, measures 6x8mm, has a built-in SLC wafer erase / write cycle life of 100,000 cycles, and has passed 10,000 random power-down cycles. The bus driver uses the TI SN74AVC16T245DGGR, which features 16 bidirectional signal control channels, operates on a 3.3V power supply, is compatible with TTL and CMOS levels, and has an enable control pin.

[0023] When SOC1 malfunctions and freezes, FPGA2 outputs the critical information saved by SOC1 before the freeze and displays it on the LCD screen. This increases system maintainability and flexibility, meeting various customer needs for standby crash displays. This method has wider adaptability and higher maintainability, and can meet various customer needs for standby crash displays. It can be widely used in the automotive display field, achieving good economic benefits.

[0024] likeFigure 2 As shown in the figure, the FPGA 2 further comprises: an SD NAND / SDRAM parameter calculation module 21, an SD NAND picture reading control module 22 and an SDRAM controller 23, which are sequentially connected; the SDRAM controller 23 is connected with the SDRAM 4; and the SD NAND controller 24 is connected between the SD NAND picture reading control module 22 and the SD NAND 3.

[0025] The FPGA 2 further comprises a clock module 25, which is connected with the SD NAND / SDRAM parameter calculation module 21, the SD NAND picture reading control module 22 and the SDRAM controller 23, and the video output module 24. The clock module 25 provides driving clock for other modules; the SD NAND / SDRAM parameter calculation module 21 provides parameters for the SD NAND picture reading control module 22 and the SDRAM controller 23 according to picture resolution and other information; the SD NAND picture reading control module 22 controls the read interface of the SD NAND controller 24, and converts the RGB888 format data read from the SD NAND 3 into RGB565 format data and writes into the SDRAM controller 23; finally, the video output module 24 reads picture data from the SDRAM controller 23 and displays on the liquid crystal screen.

[0026] As shown in the figure, Figure 3 The embodiment of the application further provides a picture control method using the control circuit based on the FPGA SOC architecture, which comprises the following steps:

[0027] S310, when the SOC is in standby or down, the FPGA does not detect the video signal output by the SOC, the control signal OE of the bus driver is closed, and the SD NAND is hung by the FPGA;

[0028] S320, start reading picture file indication information from the SD NAND through the SDIO bus and output to the liquid crystal screen through the video encoder; the picture file indication information comprises picture generated by the SOC, which can contain product logo information, time information, data information (voltage, oil pressure, oil quantity, speed, etc.) received by the SoC before down, and other self-defined key information; the picture file comprises BMP picture information, and the BMP picture comprises standby (down) picture.

[0029] As shown in the figure, Figure 4As shown, when the SOC is in standby or shutdown, the FPGA does not detect the video signal output by the SOC, and the control signal OE of the bus driver is closed, and before the SD NAND is hung by the FPGA, the following is further included:

[0030] S410, when the SOC is in a running state, a normal video signal is output to the FPGA, and after the FPGA completes processing, the video signal is output to the liquid crystal screen through a video encoder;

[0031] S420, meanwhile, the FPGA opens the control signal OE of the bus driver, sets the SDIO bus to a high-impedance state, at this time, the SD NAND is hung by the SOC, and the SOC saves picture file indication information to the SD NAND in a timing manner.

[0032] The embodiment of the present application further provides a liquid crystal screen, which is provided with the control circuit based on the FPGA SOC architecture.

[0033] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control circuit based on an FPGA SOC architecture, characterized in that, The application relates to a control circuit based on an FPGA SOC architecture. The SOC, FPGA, SD NAND, SDRAM and video encoder are sequentially connected, the FPGA is connected with the SD NAND and the SDRAM respectively, the SOC is connected with a bus driver, the FPGA further comprises an SD NAND / SDRAM parameter calculation module, an SD NAND picture reading control module and an SDRAM controller, the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, a video output module and the video encoder are sequentially connected, the SDRAM controller is connected with the SDRAM, an SD NAND controller is connected between the SD NAND picture reading control module and the SD NAND, the FPGA further comprises a clock module, the clock module is connected with the SD NAND / SDRAM parameter calculation module, the SD NAND picture reading control module and the SDRAM controller, the video output module respectively, wherein, When the SOC is in standby or down, the FPGA does not detect the video signal output by the SOC, the control signal OE of the bus driver is closed, and the SD NAND is hung by the FPGA; The picture file is read from the SD NAND through the SDIO bus and is output to the liquid crystal screen through the video encoder, and the picture file indication information comprises product information, time information and data information received by the SoC before down.

2. A picture control method using the control circuit based on the FPGA SOC architecture according to claim 1, characterized by, Before the SOC is in standby or down, the FPGA does not detect the video signal output by the SOC, the control signal OE of the bus driver is closed, and the SD NAND is hung by the FPGA, the application further comprises the following steps: When the SOC is in a running state, the FPGA is normally output with a video signal, and the FPGA is output to the liquid crystal screen through the video encoder after processing; The FPGA opens the control signal OE of the bus driver, sets the SDIO bus to a high impedance state, and the SOC hangs the SD NAND at this time, and the SOC saves the picture file into the SD NAND.

3. A liquid crystal panel, characterized by comprising: The liquid crystal screen is provided with the control circuit based on the FPGA SOC architecture.

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