System and method for signed conversion

Abstract

The present disclosure relates to systems and methods for signed conversion. Described herein relate to systems and methods for a converter including a first input, a second input, and a plurality of digital-to-analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a zeroing operation. The DAC cell is configured to provide a data magnitude in a polarity on at least one of the first leg or the second leg during at least a portion of a clock cycle. The data magnitude and the polarity are provided according to a first signal at the first input and a second signal at the second input.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to signal converters, including but not limited to digital-to-analog converters (DACs) for use in radio frequency (RF) systems. BACKGROUND

[0002] DACs, such as unipolar current steering DACs operating at high signal frequencies, can suffer degraded performance (e.g., duty cycle error) due to rising and falling edges at the data output having different and uncorrelated errors. SUMMARY

[0003] In one aspect, the present disclosure relates to a converter comprising: a first port; a second port; and a plurality of digital-to-analog converter (DAC) cells, wherein a DAC cell of the DAC cells comprises a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell, wherein the first circuit is configured to provide a zeroing operation during a first time period within a clock cycle, wherein the DAC cell is configured to provide a signal having a data magnitude at a certain polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle, a first signal at the first input indicating the polarity and a second signal at the second input indicating the data magnitude.

[0004] In another aspect, the present disclosure relates to a converter comprising: a plurality of digital-to-analog converter (DAC) cells, wherein the DAC cells each comprise a first transistor configured to provide a first signal at a first node at least partially in response to a data signal, a second transistor configured to provide the first signal to a first output in response to a sign signal, a third transistor configured to provide the first signal to a second output in response to an inverse of the sign signal, wherein a fourth transistor is configured to couple a second node coupled to the second transistor to a third node coupled to the third transistor during a first time period within a clock cycle.

[0005] In other respects, this disclosure relates to a method for converting a digital sign signal and a digital amplitude signal into an analog signal, the method comprising: providing a first signal to a branch coupled to a first port of a digital-to-analog converter (DAC) unit in at least part of response to a data signal being at a first logic level of the data signal and the sign signal being at a first logic level of the sign signal; coupling the first branch to a second branch of the DAC unit during a first time period within a first clock cycle, the first time period following the provision of a first current signal to the first branch; providing a second signal to a second branch coupled to a second port in at least part of response to the data signal being at the first logic level of the data signal and the sign signal being at a second logic level of the sign signal; and coupling the first branch to the second branch during a second time period within a second clock cycle, the second time period following the provision of a second current signal to the second branch. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will be more clearly and better understood through a detailed description taken with reference to the accompanying drawings, wherein the same reference numerals identify corresponding elements throughout. In the drawings, the same reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0007] Figure 1 This is a schematic block diagram of a communication system including a base station and a client device according to some embodiments.

[0008] Figure 2 This is a schematic block diagram of an apparatus for communicating via a wireless communication link according to some embodiments.

[0009] Figure 3 This is a schematic block diagram of a transmitter including a DAC according to some embodiments.

[0010] Figure 4 According to some embodiments, it is used for Figure 3 The electrical schematic diagram of the DAC unit described in the document.

[0011] Figure 5 According to some embodiments, it is used for Figure 5 The timing diagram of the DAC unit signals described in the document. Detailed Implementation

[0012] Referring generally to the schematic, an exemplary DAC uses multiple DAC units to provide an analog signal in response to a digital signal representing a positive or negative number. In some embodiments, the DAC is configured to reduce duty cycle errors that produce even-order distortion (e.g., second-order harmonic distortion (HD2) / second-order intermodulation distortion (IMD2) distortion). In some embodiments, the DAC is configured to receive a sign bit and an amplitude bit and provide a sign-return-to-zero DAC for an analog signal. In some embodiments, the same DAC units are selected for up / down transitions to create even-order symmetry in the transition error and thereby reduce even-order distortion.

[0013] According to some embodiments, the DAC system and method advantageously reduce or effectively remove second harmonic distortion (HD2) by applying a dynamic element-matching (DEM) algorithm when selecting DAC units. In some embodiments, the DAC comprises four units. The system and method use the same units for both up and down transitions, such that the rising and falling edges are symmetrically related to even-order frequencies. The rising and falling edges may respectively refer to a portion of the signal in which the amplitude increases and a portion of the signal in which the amplitude decreases. In some embodiments, the falling edge occurs when the signal transitions from logic level 1 to logic level 0. In some embodiments, the rising edge occurs when the signal transitions from logic level 0 to logic level 1.

[0014] In some embodiments, the positive and negative bits are applied in the output stage of the DAC unit (e.g., near or as close as possible to the output of a cascaded transistor). A cascaded transistor can refer to a means for shielding components of the DAC (e.g., current sources or switching transistors in the DAC unit). In some embodiments, a cascaded transistor is a means for attenuating the output swing such that the signal swing at the drain of the cascaded transistor coupled to the output is greater than the signal swing at the source of the cascaded transistor. Therefore, in some embodiments, a cascaded transistor can reduce the output swing (e.g., the range of the output signal) experienced by the switching transistor.

[0015] In some embodiments, the system and method are used for a high-speed DAC and provide high spurious-free dynamic range (SFDR) (e.g., 40 to 80 dB relative to the carrier frequency (dBc)) for 5G applications. In some embodiments, the system and method are used for a transmitter that does not use a local oscillator to up-convert analog signals for radio transmission. In some embodiments, the DAC is configured as a 25% return-to-zero DAC to reduce timing errors for positive and negative signals. A 25% return-to-zero DAC is a DAC that uses a clock signal with a 75% duty cycle and provides a 25% silence period for return-to-zero operation.

[0016] In one aspect, the DAC is implemented for wireless communication. For example, the DAC can be implemented in a transmitter for radio frequency (RF) communication, such as cellular communication (3G, 4G, 5G, 6G, etc.), Wi-Fi communication, Bluetooth communication, etc. In some embodiments, the transmitter is a base station (e.g., eNodeB (eNB), gNodeB (gNB), etc.) or a client device providing wireless communication. In one aspect, the DAC can operate at high speed (e.g., exceeding 5Gbps) and can convert digitally represented RF modulated signals into analog signals represented analog signals. The DAC can provide the analog signals to a preamplifier or power amplifier for transmission via an antenna, making the analog upconverter or analog mixer unnecessary. By omitting the analog upconverter or analog mixer, the transmitter can reduce power consumption and can be implemented with a small form factor. Furthermore, the modulation or upconversion of signals from baseband frequencies (e.g., 100MHz to 1GHz) to RF frequencies (1 to 10GHz) can be performed by digital logic circuitry, which is less susceptible to noise than analog circuitry, allowing the transmitter to improve signal quality. Although the DAC disclosed herein is provided for a transmitter to perform wireless communication, the DAC can be implemented for various applications. For example, the DAC disclosed herein can be implemented for wired communication, optical communication, or any computing device that performs high-speed digital-to-analog conversion.

[0017] In some embodiments, one or more components may be embodied wholly or partially as one or more transistors. The implemented transistor may be an N-type transistor or a P-type transistor. An N-type transistor is a transistor that utilizes electrons as the majority carriers. A P-type transistor is a transistor that utilizes holes as the majority carriers. The transistor may be any suitable type of transistor, including, but not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. Furthermore, one or more transistors shown or described herein may be embodied as two or more transistors connected in parallel. In one aspect, a transistor includes a source electrode, a drain electrode, and a gate electrode. The source and drain electrodes are interchangeable depending on the voltage applied to them. Therefore, the source and drain electrodes may be referred to herein as source / drain electrodes. Current may flow between the source and drain electrodes depending on the voltage applied to the gate electrode of the transistor. In some applications, the transistor may be implemented as a switch. For example, if the voltage difference between the gate and source electrodes of a transistor is greater than the transistor's threshold voltage, then the transistor can be electrically coupled between its source and drain electrodes. Conversely, if the voltage difference between the gate and source electrodes is less than the transistor's threshold voltage, then the transistor can be disabled to electrically decouple it from its source and drain electrodes.

[0018] In the following description, numerous details are set forth for illustrative purposes to provide a thorough understanding of the described embodiments. However, those skilled in the art will understand that other embodiments may be practiced without some of these details. In other instances, structures and apparatuses are shown in block diagram form. Several embodiments are described herein, and while various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, no single or multiple features of any described embodiment should be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0019] Similarly, when an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element may be directly connected to the other element, or that there may be an intermediary element between the elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there is no intermediary element in the "direct" connection between the elements. However, the existence of a direct connection does not preclude other connections in which intermediary elements may be present.

[0020] Furthermore, for ease of description, the methods and processes discussed herein may be described in a specific order. However, it should be understood that, unless the context otherwise requires, intermediate processes may occur before and / or after any part of the described process, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0021] Unless otherwise indicated, all figures used herein to express quantities, dimensions, etc., shall be understood in all instances to be modified by the term “about.” In this application, unless expressly stated otherwise, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or.” Furthermore, the use of the term “including” and other forms such as “includes” and “included” shall be considered non-exclusive. Additionally, unless expressly stated otherwise, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit.

[0022] Some embodiments relate to a converter. The converter includes a first input, a second input, and a plurality of digital-to-analog converter (DAC) units. A DAC unit includes a first circuit, a first branch associated with a first output of the DAC unit, and a second branch associated with a second output of the DAC unit. The first circuit is configured to couple the first branch to the second branch during a first time period within a clock cycle. The DAC units are configured to provide a signal with a data amplitude of a certain polarity on at least one of the first or second branches during at least a portion of the clock cycle. The data amplitude and polarity are provided based on a first signal at the first input and a second signal at the second input. In some embodiments, the data amplitude may refer to a characteristic of the signal related to the quantity or amplitude of the signal. The data amplitude may be represented by one or more bits of the digital input signal. In some embodiments, polarity may refer to the state of the signal being in a positive or negative state (e.g., above or below logic level 0 or ground). In some embodiments, polarity may be represented by one or more bits of the digital input signal.

[0023] In some embodiments, the first signal is a sign signal indicating polarity and the second signal is a data signal indicating data amplitude. In some embodiments, the first circuit includes a first pair of transistors and a second pair of transistors coupled between a first branch and a second branch. Each of the first pair of transistors is an N-channel transistor and each of the second pair of transistors is a P-channel transistor. In some embodiments, the first circuit performs a zero-reset operation. The data signal may refer to a signal indicating the data amplitude of the output signal of the DAC unit. In some embodiments, the data signal is a digital signal (e.g., one or more bits). The sign signal may refer to a signal indicating the polarity of the output signal of the DAC unit. In some embodiments, the sign signal is a digital signal (e.g., one or more bits). A digital sign signal may refer to a sign signal represented by one or more bits. A digital amplitude signal may refer to a sign signal represented by one or more bits.

[0024] In some embodiments, the converter further includes a second circuit configured to select the same DAC unit for up- and down-conversion, such that the rising and falling edges at the first and second outputs are correlated.

[0025] In some embodiments, the first time period is 25% of the clock cycle. In some embodiments, the first signal is a positive or negative sign signal indicating polarity and the second signal is a data signal indicating data amplitude. The transition of the positive or negative sign signal is provided during the first time period. In some embodiments, the first time period is the last time period of the clock cycle. The transition of the positive or negative sign signal may refer to a change from a first level (e.g., a logic level) of the positive or negative sign signal to a second level.

[0026] In some embodiments, a first signal is provided to a first transistor disposed on a first branch, and a data signal is combined with a clock signal associated with a clock cycle and provided to a second transistor. In some embodiments, the first transistor is disposed between the second transistor and a first output. In some embodiments, the first transistor is disposed between the second transistor and a cascaded transistor coupled to the first output.

[0027] Some embodiments relate to a converter. The converter includes a plurality of digital-to-analog converter (DAC) units. Each DAC unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is configured to provide a first signal at a first node in response at least partially to a data signal, and the second transistor is configured to provide the first signal to a first output in response to a sign signal. The third transistor is configured to provide the first signal to a second output in response to the inverse of the sign signal. The fourth transistor is configured to couple a second node coupled to the second transistor to a third node coupled to the third transistor during a first time period within a clock cycle.

[0028] In some embodiments, the sign transition is provided during a first time period. In some embodiments, the DAC unit is a current-mode digital-to-analog converter unit. In some embodiments, the gate of the first transistor receives a data signal combined with a clock signal associated with a clock cycle in a logical AND operation.

[0029] In some embodiments, the converter further includes a cascaded transistor coupled to a first output. The cascaded transistor is positioned between the first output and a second transistor.

[0030] Some embodiments relate to a method for converting a digital positive / negative signal and a digital amplitude signal into an analog signal. The method includes providing a first current signal to a branch coupled to a first output of a digital-to-analog converter (DAC) unit, at least partially in response to a data signal being at a first logic level of the data signal and a positive / negative signal being at a first logic level of the positive / negative signal. The method further includes coupling the first branch to a second branch of the DAC unit during a first time period within a first clock cycle. The first time period follows the provision of the first current signal to the first branch. The method further includes providing a second current signal to a second branch coupled to a second output, at least partially in response to a data signal being at a first logic level of the data signal and a positive / negative signal being at a second logic level of the positive / negative signal. The method further includes coupling the first branch to the second branch during a second time period within a second clock cycle, the second time period following the provision of the second current signal to the second branch.

[0031] In some embodiments, the method further includes providing a first current signal to a first branch or a second current signal to a second branch in response to the data signal being at a second level of the data signal. In some embodiments, the method further includes using a first circuit to provide the data signal to a DAC unit. The first circuit is configured to select a DAC unit to receive the data signal such that the rising and falling edges of the signals at the first and second outputs are correlated.

[0032] In some embodiments, the method further includes supplying current from a power node via a third branch, at least in part, in response to a data signal being at a second level. In some embodiments, the first time period is the last quarter of a first clock cycle.

[0033] Figure 1This describes a communication system 100 comprising a base station 120 and client devices 110A, 110B, and 110C according to some embodiments. The base station 120 and client devices 110A, 110B, and 110C can communicate via a wireless communication link. The wireless communication link can be a cellular communication link conforming to 3G, 4G, 5G, 6G, or other cellular communication protocols. In one aspect, client devices 110A…110C are located within a geographical boundary 150 relative to the base station 120 and can communicate with or through the base station 120. In some embodiments, the communication system 100 includes more, fewer, or different numbers of... Figure 1 The base station 120 and / or client device 110 shown in the figure.

[0034] In some embodiments, the client device 110 may be a user device, such as a mobile phone, smartphone, personal digital assistant (PDA), tablet computer, laptop computer, wearable computing device (e.g., head-mounted display, smartwatch), etc. The client device 110 may also be referred to as a user equipment (UE). Each client device 110 can communicate with the base station 120 via a corresponding communication link. For example, the client device 110 can transmit or provide RF wireless signals to the base station 120 via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links), and / or receive RF wireless signals from the base station 120 via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links). The wireless signals may be signals exchanged or provided through a wireless medium (e.g., air). The wireless signals may contain or carry data, such as video data, audio data, image data, text, etc.

[0035] In some embodiments, base station 120 may be a device configured to provide wireless communication to client device 110 within a geographical boundary 150. Examples of base stations include eNB, gNB, etc. Base station 120 may be communicatively coupled to another base station 120 or other communication devices via a wireless communication link and / or a wired communication link. Base station 120 may receive RF wireless signals from client device 110 or another base station 120 via a wireless communication link. Alternatively or additionally, base station 120 may transmit or provide RF wireless signals to another client device 110, another base station 120, or another communication device via a wireless communication link. Thus, base station 120 enables communication among client devices 110 associated with base station 120 or other client devices 110 associated with different base stations 120.

[0036] Figure 2This diagram illustrates a block diagram of an apparatus 210 for communication via a wireless communication link, according to some embodiments. In some embodiments, apparatus 210 may be a base station 120, a client device 110, or any device capable of communication via a wireless communication link. In some embodiments, apparatus 210 includes an antenna 215, a wireless interface 220, a processor 230, and a memory device 240. These components may be embodied as hardware, software, firmware, or a combination thereof. In some embodiments, apparatus 210 includes more, fewer, or different... Figure 2 The components shown in the diagram. For example, device 210 may include an electronic display and / or an input device. For example, device 210 may include... Figure 2 In addition to the antenna 215 and additional wireless interface 220 shown in the figure.

[0037] In some embodiments, antenna 215 is used to receive and / or transmit RF wireless signals over a wireless medium (e.g., air). Antenna 215 may be a dipole antenna, patch antenna, loop antenna, or any suitable antenna for wireless communication. In one aspect, a single antenna 215 is used for both transmitting and receiving wireless signals. For receiving wireless signals, antenna 215 may detect wireless signals having electromagnetic wave variations in a wireless medium (e.g., air) and provide an electrical signal of RF having voltage and / or current corresponding to the detected variations in the electromagnetic waves to wireless interface 220. The electrical signal of RF may be referred to herein as an RF signal. For transmitting wireless signals, antenna 215 may receive the electrical signal of RF having voltage and / or current from wireless interface 220 and transmit a wireless signal having electromagnetic wave variations corresponding to the electrical signal over a wireless medium (e.g., air). In some embodiments, different antennas 215 may be used for transmitting and receiving wireless signals. In some embodiments, multiple antennas 215 may be used to support multiple-input multiple-output (MIMO) communication.

[0038] In some embodiments, wireless interface 220 is circuitry or a component that provides or receives RF signals to or from antenna 215. In some embodiments, wireless interface 220 includes transmitter 224 and receiver 228. In some embodiments, transmitter 224 and receiver 228 may be implemented in the same integrated circuit. In some embodiments, transmitter 224 and receiver 228 may be implemented in different integrated circuits. Transmitter 224 may be circuitry or a component that generates or provides RF signals for transmitting data. In one aspect, transmitter 224 may receive from processor 230 a baseband signal containing or representing data (e.g., audio data, image data, text, or any data) for transmission at a baseband frequency (e.g., 0 to 1 GHz), and upconvert the baseband signal to generate an RF signal. Transmitter 224 may provide the RF signal to antenna 215 for transmission. Receiver 228 may be circuitry or a component that receives RF signals to receive data. In one aspect, receiver 228 may receive an RF signal from antenna 215 and down-convert the RF signal to a baseband frequency (e.g., 0 to 1 GHz) to obtain a down-converted signal at the baseband frequency. The down-converted signal at the baseband frequency may contain or represent data (e.g., audio data, image data, text, or any data) generated by another device (e.g., another base station 120, another client device 110, etc.). Receiver 228 may provide the down-converted signal to processor 230. In one configuration, transmitter 224 and receiver 228 may be coupled to the same antenna 215. In another configuration, transmitter 224 and receiver 228 may be coupled to different antennas 215.

[0039] Processor 230 is a data processing component. Processor 230 may be embodied in an FPGA, ASIC, logic circuit, etc. Processor 230 may obtain instructions from memory device 240 and execute those instructions. In one aspect, processor 230 may receive a down-converted signal at a baseband frequency from wireless interface 220 and decode or process data contained in or represented by the down-converted signal. For example, processor 230 may obtain audio data or image data from the down-converted signal. In another aspect, processor 230 may generate or obtain data for transmission at a baseband frequency and encode or process the data. For example, processor 230 may encode or process image data or audio data at a baseband frequency and provide a baseband signal containing or representing the encoded or processed data to wireless interface 220 for transmission.

[0040] Memory device 240 is a component for storing data. Memory device 240 may be embodied as RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any device capable of storing data. Memory device 240 may be embodied as a non-transitory computer-readable medium storing instructions executable by processor 230 to perform the various functions of device 210 disclosed herein. In some embodiments, memory device 240 and processor 230 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 230, and wireless interface 220 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 230, and wireless interface 220 are implemented as discrete components (or separate integrated circuits).

[0041] Figure 3 The diagram illustrates a transmitter 224 according to some embodiments. In some embodiments, the transmitter 224 includes a DAC (also referred to as "DAC circuit 310"), a modulator 320, an interface circuit 370, and a power amplifier (PA) 380. These components can operate together to generate an RF signal 385 for transmission. In one aspect, the modulator 320 operates in the digital domain, while the interface circuit 370 and PA 380 operate in the analog domain. The DAC circuit 310 can operate in both the analog and digital domains and can serve as an interface between the modulator 320 operating in the digital domain and the interface circuit 370 and PA 380 operating in the analog domain. In some embodiments, the transmitter 224 may include more, fewer, or different components. Figure 3 The components shown are illustrated. For example, modulator 320 may be implemented as part of processor 230. Although DAC circuitry 310 is shown as part of transmitter 224, DAC circuitry 310 may be used in other devices, including but not limited to optical devices (e.g., optical transceivers or sensors) and computing devices. As described below, in some embodiments, DAC circuitry 310 is configured to reduce or effectively eliminate second harmonic distortion (HD2) by applying a DEM algorithm or configured as a sign-return-to-zero DAC.

[0042] In some embodiments, modulator 320 is a circuit or component capable of receiving a baseband signal comprising K-bit data In_A…In_K represented digitally, and performing modulation or up-conversion on the K-bit data In_A…In_K. Modulation or up-conversion may be multiplying the value represented by the K-bit data In_A…In_K by a sine or cosine function of the carrier frequency of the RF. The carrier frequency may be a frequency at which the wireless signal can be transmitted (e.g., 2 GHz or 60 GHz). In one method, modulator 320 may perform a digital logic circuitry multiplying the value represented by the K-bit data In_A…In_K by a sine or cosine function of the carrier frequency to obtain N-bit data D_A…D_N representing an up-converted signal of the RF. Modulator 320 may provide the N-bit data D_A…D_N, represented digitally, to DAC circuit 310.

[0043] In some embodiments, the DAC circuit 310 is a circuit or component capable of performing digital-to-analog conversion. In some embodiments, the DAC circuit 310 includes a plurality of DAC units 325A…325N and an adder circuit 330. The DAC units 325A to N can be any number of units (e.g., 2, 3, 4, 8, etc.). In some embodiments, the number of units is four. The DAC units 325A…325N can operate together to receive N-bit data D_A…D_N in digital representation and provide signals at outputs 335A, 335B in an analog representation corresponding to the N-bit data D_A…D_N. The data representation may include a sign signal or a sign bit. For example, the voltage amplitude of the signal at outputs 335A, 335B may represent or correspond to the values ​​of the N-bit data D_A…D_N and the sign bit. In some embodiments, the DAC circuit 310 includes more, less, or different... Figure 3 The components shown in the document.

[0044] In some embodiments, a DAC unit, such as one of DAC units 325A to N, may refer to any circuitry or component that receives digital data (e.g., a 1-bit signal DA) and a digital sign signal S (e.g., a 1-bit signal SA) and provides an analog signal output. The output may be a current or voltage representing the digital data and the sign data. In some embodiments, the DAC unit may be a current-mode or voltage-mode DAC unit. DAC unit 325A is described below and in some embodiments is similar to or identical to any or all of DAC units 325B to N. DAC units 325A to N include outputs 328A to N and 329A to N, which provide a signal (e.g., current) corresponding to a single bit of data D and a sign signal for receive by adder circuitry 330. In some embodiments, DAC unit 325A includes an input port coupled to modulator 320 to receive the data signal D_A and an input port coupled to receive the sign signal S_A. The sign signals S_A and S_B to S_N may be the same or related signals. In some embodiments, DAC unit 325A includes an output port or outputs 328A and 329B coupled to adder circuit 330. In some embodiments, outputs 328A and 329B provide differential current signals. Ports may be pads, contacts, metal rails, or any conductive component capable of receiving or providing electrical signals (e.g., voltage or current). Input ports may be ports for receiving signals, while output ports may be ports for providing or outputting signals. In this configuration, DAC unit 325A may receive one bit of data D_A and one bit of sign signal S_A, and provide output signals at outputs 328A and 329B, the output signals having an amplitude corresponding to one bit of data D_A and a positive or negative characteristic (e.g., polarity) corresponding to the sign signal S_A. For example, in response to a bit of data D_A having a value of "0", DAC unit 325A may bypass and not provide current. For example, in response to a single data bit D_A with a value of '1' and a single sign bit S_A, DAC unit 325A can provide signals with specific amplitude and polarity to adder circuit 330 at outputs 328A and 328B. In some embodiments, the current supplied (e.g., absorbed or supplied) to adder circuit 330 at output 328A can be considered a positive signal, and the current supplied to output 329A can be considered a negative signal. References below Figure 4 A detailed description of exemplary embodiments and operation of DAC unit 325A is provided. In some embodiments, DAC circuit 310 is a current-mode DAC. A current-mode DAC is a DAC that accumulates current from DAC units 325A…325N to provide an analog output and may be a unary current DAC.

[0045] In some embodiments, adder circuit 330 is a circuit or component that can accumulate or otherwise provide a current signal at outputs 335A to B corresponding to current signals provided at outputs 328A to N and 329A to N from a group of DAC units 325A…325N. In some embodiments, outputs 335A to N provide differential current signals. In some embodiments, adder circuit 330 includes various components for adding the differential current signals provided at outputs 328A to N and 329A to N. In some embodiments, the adder includes an operational amplifier, a current mirror, a current source, a resistor, or other circuit elements that can combine currents from the DAC unit group 325A to N or outputs 328A to N and 329A to N and generate or provide signals corresponding to the combined currents at outputs 335A, 335B. In some embodiments, adder circuit 330 may be or include a resistor ladder. In some embodiments, the magnitude of the combined current corresponds to the magnitude of the voltage at outputs 335A, 335B. For example, for the 4-bit input data '+0001' corresponding to the value '1', the amplitude difference of the voltage signals at outputs 335A and 335B can be 100mV corresponding to the current from a single DAC unit from DAC units 325A to N. For example, for the 4-bit input data '-0001' corresponding to the value '1', the amplitude difference of the voltage signals at outputs 335A and 335B can be -100mV corresponding to the current from a single DAC unit from DAC units 325A to N. For example, for the 4-bit input data '+0111' corresponding to the value '3', the amplitude difference of the voltage signals at outputs 335A and 335B can be 300mV corresponding to the current from all three DAC units from DAC units 325A to N.

[0046] According to various embodiments, DAC circuit 310 may include circuitry and components for converting digital signals into analog signals, such as wireless signals (e.g., radio frequency (RF)) and / or wired signals (e.g., fiber optic, copper wire, twisted pair, etc.). DAC circuit 310 may include DACs of various architectures and / or designs, including, but not limited to, pulse-width modulation (PWM) DACs, delta-sigma DACs, thermometer-encoded DACs, oversampling DACs, noise-shaping DACs, digitally controlled oscillators, resistor DACs (e.g., resistor ladder (R-2R) DACs), current DACs, voltage DACs, switched-capacitor DACs, unary DACs, binary weighted DACs, or other suitable DAC designs. In other embodiments, the DAC may be implemented using combinations of components (e.g., resistors, capacitors, current sources, voltage sources, etc.). In yet another instance, DAC circuit 310 may be part of an ADC. For example, DAC circuit 310 may form at least a portion of the clock data recovery (CDR) circuitry of an ADC. For example, DAC circuit 310 may be a phase interpolator DAC configured to output analog signals based on phase interpolation codes.

[0047] In some embodiments, interface circuitry 370 is a circuit or component that can interface between DAC circuitry 310 and PA 380. Examples of interface circuitry 370 include baluns, impedance matching circuitry, etc. In one configuration, interface circuitry 370 includes a first input port coupled to a first output port of adder circuitry 330, a second input port coupled to a second output port of adder circuitry 330, and an output port coupled to an input port of PA 380. In this configuration, interface circuitry 370 can convert the differential signals at outputs 335A and 335B into signal 375. For example, interface circuitry 370 can obtain the amplitude difference of the signals at outputs 335A and 335B and provide the difference as signal 375. In one aspect, interface circuitry 370 can provide impedance matching between DAC circuitry 310 and PA 380, such that the output port of PA 380 can have a specific impedance within a certain range (e.g., 40 to 60 ohms) to ensure proper operation of PA 380.

[0048] In some embodiments, PA 380 is a circuit or component that amplifies signal 375 to obtain RF signal 385 to drive antenna 215. In some embodiments, PA 380 includes a single amplifier circuit or two or more amplifier circuits cascaded together. In one configuration, PA 380 includes an input port coupled to the output port of interface circuitry 370 and an output port coupled to antenna 215. In this configuration, PA 380 amplifies the amplitude of signal 375 to obtain RF signal 385 with amplified amplitude and provides RF signal 385 to antenna 215 for transmission.

[0049] In some embodiments, encoder 390 (e.g., a constant transition rate (CTR)-DEM encoder) may be configured to receive input data In_A…In_K and sign signals and provide data signals DA_A to D_N and sign signals S_A to S_N. In some embodiments, the CTR-DEM logic may be implemented as hardware, software, or a combination of hardware and software. In some instances, the CTR-DEM logic may be implemented as (but not limited to) a circuit (including logic circuitry), a custom integrated circuit (IC), an application-specific circuit (ASIC), or a field-programmable gate array (FPGA) implementation. In other instances, encoder 390 may be implemented as part of a DAC controller. For example, encoder 390 may be implemented as part of the firmware of a DAC controller.

[0050] In some embodiments, encoder 390 is configured to select the same DAC units 325A to 325N for up-conversion and DAC units 325A to 325N for down-conversion. In some embodiments, up and down conversion may refer to changes in the current supplied to adder circuit 330 and may be due to changes in the digital data signals DA_A to D_N or changes in the state of the sign signals S_A to S_N. In some embodiments, units are selected by providing a logic 1 for the data signals (data signals DA to DN) of a particular unit. Using the same DAC units 325A to 325N for up and down conversion provides even-number symmetry of the error, which reduces distortion (e.g., second-order harmonic distortion (HD2) / second-order intermodulation distortion (IMD2)). For example, if DAC units 325A and DAC units 325B each provide current based on a positive digit 0010 input (by providing data signals D_A and D_B and signals S_A and S_B as logic 1), then DAC units 325A and 325B should be selected to provide current corresponding to a negative digit 0010 input (by providing data signals D_A and D_B as logic 1 and signals S_A and S_B as logic 0). In this way, the rising and falling edges of the signals at outputs 328X and 329X are correlated (e.g., including rising and falling timing errors associated with the positive-to-negative transition) and have even-order symmetry. In some embodiments, correlation may refer to the signal changes at outputs 328A_N and 329A to N caused by input changes corresponding to opposite changes in the signals at outputs 328A_N and 329A to N (e.g., reverse matching of rising and falling edges of the signals at outputs 328X and 329X due to input changes). In another example, if DAC unit 325B provides current based on a positive digital input (by providing data signals D_B and S_B as logic 1), then DAC unit 325B should be selected to provide current corresponding to a negative digital input 0001 (by providing data signals D_B and S_B as logic 0). In another example, if DAC units 325A and DAC unit 325B each provide current based on a negative digital input 0010 (by providing data signals D_A and D_B and signals S_A and S_B as logic 0), then DAC units 325A and 325B should be selected to provide current corresponding to a positive digital input 0010 (by providing data signals D_A and D_B as logic 1 and signals S_A and S_B as logic 1). In some embodiments, by using encoder 390 to select the same unit for positive and negative transitions, an SFDR of 85.8 dBc can be achieved when combined with a zero-reset operation. In some embodiments, the return-to-zero DAC, which does not select the same unit for both positive and negative transitions, has an SFDR of 68.2 SFDR. The lower performance is due to third and second harmonic distortion.

[0051] It should be noted that various logic and sub-components can be used to implement encoder 390. Encoder 390 can be implemented as hardware, such as digital logic and / or logic circuits utilizing various hardware and logic components. According to various embodiments, encoder 390 tracks DAC units 325A to N for transitions, such that units for up-transitions are used for the next transition of the same amplitude on the opposite side. Up / down transitions can refer to signal transitions representing a transition from one number to another. For example, up and down transitions can include transitions from +1 to 0, +1 to -1, +2 to -2, etc., and from -1 to 0, -1 to +1, -2 to +2, etc.

[0052] Clock circuit 392 can provide a clock signal for various sampling and timing operations associated with DAC circuit 310. Clock circuit 392 can be part of a modulator or DAC circuit 310 and can be any circuit used to generate a clock signal (comprising time periods of a first level and a second level, e.g., periodic pulse signals of logic 1 and logic 0 values). In some embodiments, clock circuit 392 provides clock signal 502 ( Figure 5 In some embodiments, clock circuit 392 is a logic circuit configured to provide a square wave clock signal or other logic signal having a 75% duty cycle. In some embodiments, clock circuit 392 may respond to a local oscillator or other frequency source and use flip-flops or other logic to create a clock signal.

[0053] Figure 4 This illustration shows a schematic diagram of a DAC unit 325X according to some embodiments. The DAC unit 325X may be a DAC unit 325A…325N (…). Figure 3 One of the components of DAC unit 325X. The components of DAC unit 325X can operate together to provide signals at outputs 328X and 329X, corresponding to the data signal DX and the sign signal SX. In some embodiments, unit 325X includes transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, and a current source 408. The current source 408 is coupled to a ground node 409.

[0054] Transistors M1 and M2 are switching or driving transistors that receive signals SW+ and SW- at their gates, respectively. Transistor M2 is coupled in series with transistor M3, which is coupled to power node 406 (e.g., a low-voltage power supply). Transistor M3 is biased at its gate to provide sink current to current source 408 when transistor M2 is turned on by signal SW- at its gate. Transistors M4 and M5 have their sources coupled to the drain of transistor M1, whose source is coupled to current source 408. Transistor M1 is controlled by signal SW+ at its gate and sinks current to current source 408 when turned on by signal Sw+. Current source 408 is any circuit that conducts or sinks current relatively independently of the voltage across the circuit. Current source 408 can be active or passive and may include diodes, transistors (e.g., enhancement-mode MOST FETs), operational amplifiers, or other circuit components.

[0055] Transistors M8, M6, and M4 are disposed on the first branch associated with output 328X. Transistors M9, M7, and M5 are disposed on the second branch associated with output 329X. Transistors M2 and M3 are disposed on the third branch associated with power node 406. In some embodiments, a branch may refer to any part of the circuit. In some embodiments, a branch may include two or more components coupled in series or components coupled to a node. In some embodiments, a node may refer to any location in the circuit where an electrical connection can be made. In some embodiments, the connection may be a contact, a conductor, or other structure capable of making an electrical connection. In some embodiments, the connection may be inherent in the structure of the component or integrated with the structure of the component. In some embodiments, a power node may refer to a location where a connection to a power source can be made.

[0056] Transistors M4 and M5 control the polarity of the signals at outputs 328X and 329X. When the SX+ signal is at logic level 1 indicating positive polarity, transistor M5 is turned off by the signal SX- at its gate, and transistor M4 is turned on by the signal SX+ at its gate. In some embodiments, the signal SX- is the inverted signal of SX+. In this configuration, when transistor M1 is on, indicating a positive current amplitude at output 328x, current is absorbed from output 328x through transistors M8 and M6. When the SX- signal is at logic level 1 indicating negative polarity, transistor M5 is turned on by the signal SX- at its gate, and transistor M4 is turned off by the signal SX- at its gate. In this configuration, when transistor M4 is on, indicating a negative current amplitude at output 329x, current is absorbed from output 329x through transistors M9 and M7. When the data signal DX is at logic 0, transistor M2 is turned on by the signal SW-, and transistor M1 is turned off by the signal SW+, causing current to flow through transistor M2 to current source 408 but not through transistor M1. Transistors M5 and M2 provide a dummy path for current source 408, allowing current source 408 to draw current when transistor M1 is turned off.

[0057] In one aspect, transistors M6 through M9 can operate as cascaded transistors to protect transistors M1, M2 (e.g., switching transistors) or transistors M4 and M5. Transistors M6 through M9 can be MOSFETs, FinFETs, GaaFETs, or any type of transistor. Transistors M6 through M9 can be N-type transistors. In some embodiments, some of transistors M6 through M9 can be implemented as P-type or N-type transistors. Transistors M6 and M7, as well as transistors M8 and M9, can be omitted. In some embodiments, transistors M8 and M9 have a thicker gate oxide than transistors M6 and M7 to provide more power. Transistors M6 through M9 can be biased at their gates to provide appropriate current levels at outputs 328X and 329X.

[0058] Cascaded transistors can help mitigate voltage stress. In one instance, a voltage exceeding the transistor's tolerable stress voltage across its source and drain electrodes can damage the transistor. By implementing one or more cascaded transistors, large voltages can be distributed among the series-connected transistors. For example, the voltage between the drain electrodes of transistor M1 and M8 can be shared or distributed among transistors M1, M4, M6, and M8, thus protecting transistor M1 or M4. Similarly, the voltage between the drain electrodes of transistor M1 and M9 can be shared or distributed among transistors M1, M5, M7, and M9, thus protecting transistor M1 or M5.

[0059] In some embodiments, transistors M10 to M13 provide circuitry for resetting signals at outputs 328x and 329x in response to signals SW+ and SW-. In some embodiments, transistors M10 and M11 are P-channel transistors controlled by signal SW+ such that the sources of transistors M8 and M9 are connected when signal SW+ is negative or logic 0. Transistor M10 couples its drain to the source of transistor M11, and transistor M11 couples its drain to the source of transistor M12, such that current flows in either direction between the sources of transistors M8 and M9 when transistors M10 and M11 are turned on. In some embodiments, transistors M11 and M12 are N-channel transistors controlled by signal SW- such that the sources of transistors M6 and M7 are connected when signal SW- is negative or logic 1. Transistor M12 couples its drain to the source of transistor M13, and transistor M13 couples its drain to the source of transistor M12, such that when transistors M10 and M11 are turned on, current flows in either direction between the sources of transistors M6 and M7.

[0060] Other circuitry can be used to reset or equalize the nodes associated with transistors M6 through M9. For example, a single switch or a pair of switches can be used to reset the outputs for zero-level operation. In some embodiments, the positive and negative signals Sx+ and / or Sx- are applied to transistors M4 and M5 as close as possible to outputs 328X and 329X. In some embodiments, transistors M4 and M5 are positioned closer to outputs 328X and 329X than transistor M1 and further away from outputs 328X and 329X than transistors M6 and M7. In some embodiments, the DAC unit 325X contains more, less, or different... Figure 4 The components shown in the document.

[0061] refer to Figures 4 to 5 The logical AND function is applied to data signals and clock signals 502 ( Figure 5 A signal 508 (SW+) is provided, and a logic NAND function is applied to the data signal and clock signal 502 to provide signal 510 (SW-). In some embodiments, the data signal DX may be or correspond to one of the bit or data signals D_A to D_N, and the sign signal SX may be or correspond to the sign signals S_A to S_N. (See reference...) Figure 5 Signal 504 is the positive / negative signal SX, and signal 506 is the inverted signal (SX-) of positive / negative signal 506. (Reference) Figures 4 to 5The data signal DX can be provided by the modulator 320. For example, based on the value of a single bit, the data signal DX can have one of a first voltage (e.g., VDD or 1V) or a second voltage (e.g., GND or 0V) lower than the first voltage. For example, the data signal DX with the first voltage can represent the value '1' of a single bit. For example, the data signal DX with the second voltage can represent the value '0' of a single bit. The positive / negative signal SX can be provided by the modulator 320. For example, based on the value of a single bit, the positive / negative signal SX can have one of a first voltage (e.g., VDD or 1V) or a second voltage (e.g., GND or 0V) lower than the first voltage. For example, the positive / negative signal SX with the first voltage can represent the value '1' of a single bit or a positive polarity. For example, the positive / negative signal SX with the second voltage can represent the value '0' of a single bit or a negative number.

[0062] refer to Figure 5 Timing diagram 500 includes clock signal 502, positive / negative signal 504 (e.g., signal SX+), positive / negative signal 506 (e.g., signal SX-), signal 508 (e.g., signal SW+), and signal 510 (e.g., signal SW-). Clock signal 502 is a signal that periodically switches between two voltages (e.g., logic levels). In some embodiments, a clock signal is provided in which 90% to 60% of the clock cycle is a logic level 1 period and 10% to 40% of the clock cycle is at logic level 0. In some embodiments, a clock signal is provided in which 75% of the clock cycle is a logic level 1 period and 25% of the clock cycle is at logic level 0 (provided with a 75% duty cycle). In some embodiments, a clock cycle may refer to the amount of time it takes for a period of clock signal 502 to complete (e.g., from...). Figure 5 (Time t1 to time t2 in the clock cycle). The logic level 0 portion of the clock cycle corresponds to the silent period 512 of transistors M10 to M13 (e.g., from time t1 to time t2 in the clock cycle). Figure 5 The signals at reset transistors M4 to M9 are used for zeroing operations during the time intervals t3 to t2. In some embodiments, positive and negative signals 504 and 506 are provided such that a transition 514 of positive and negative signals 504 and 506 is provided during a quiet period 512.

[0063] In some embodiments, a zero-reset operation may refer to any operation in which a signal at or near the output of the DAC unit changes from logic level 1 to logic level 0 or near logic level 0 within a clock cycle (e.g., at or near the end of the clock cycle). In some embodiments, the signal may have a DC offset when it becomes zero again. In some embodiments, a zero-reset operation typically occurs even if multiple consecutive logic 1s appear in the signal. In some embodiments, a zero-reset operation provides a zero output or quiescent condition between consecutive digital inputs. In some embodiments, a zero-reset operation causes a signal associated with the amplitude (data signal DX) of a switching transistor (e.g., transistor M4) applied to the DAC unit to become zero or near zero for a period of time. The period of time is associated with a silent time or a silent period 512 associated with clock signal 502. In some embodiments, a logic AND is used to combine the data signal DX and clock signal 502 to apply to the gate of transistor M1 to turn off transistor M1 during the zero-reset operation. The zero-reset operation reduces or eliminates timing errors to the positive / negative signal 504 because, in some embodiments, the transition 514 of the positive / negative signal 504 occurs during the silent period 512.

[0064] The transistors M1 to M13 described above can be any type of transistor, including field-effect transistors (FETs), insulated-gate FETs (IGFETs), bipolar junction transistors (BJTs), etc. In some embodiments, the transistors are P-channel or N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). A P-channel transistor contains a P-channel between its source and drain, which is a channel composed of the majority of hole carriers. An N-channel transistor contains an N-channel between its source and drain, which is a channel composed of the majority of electron carriers.

[0065] While the foregoing written description of the methods and systems enables those skilled in the art to make and use what is currently considered the best mode, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the particular embodiments, methods, and examples described herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of this disclosure.

[0066] Any reference in the singular to an embodiment or element or action of the system or method mentioned herein may also cover embodiments that include multiple such elements, and any reference in the plural to any embodiment or element or action herein may also cover embodiments that include only a single element. The terms first and second are labels and, unless expressly stated otherwise, do not assign priority, order, importance, etc. References in the singular or plural form are not intended to limit the currently disclosed system or method, its components, actions, or elements to a single or multiple configurations. A reference to any action or element based on any information, action, or element may include an embodiment in which the action or element is at least in part based on any information, action, or element.

[0067] Any embodiment disclosed herein may be combined with any other embodiment, and references to “implementation,” “some embodiments,” “alternative embodiments,” “various embodiments,” “one embodiment,” etc., are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the described embodiment may be included in at least one embodiment. Such terms used herein do not necessarily refer to the same embodiment. Any embodiment may be combined with any other embodiment in any manner consistent with the aspects and embodiments disclosed herein, inclusively or exclusively. In the foregoing description, numerous details are set forth for purposes of explanation to provide a thorough understanding of the described embodiments. However, those skilled in the art will understand that other embodiments may be practiced without some of these details. In other instances, structures and apparatuses are shown in block diagram form. Several embodiments are described herein, and while various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, no single or multiple features of any described embodiment should be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0068] Furthermore, for ease of description, the methods and processes discussed herein may be described in a specific order. However, it should be understood that, unless the context otherwise indicates, intermediate processes may occur before and / or after any part of the described process, and various procedures may be reordered, added, and / or omitted according to various embodiments.

[0069] Similarly, when an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element may be directly connected to the other element or have an intermediary element present between the elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there is no intermediary element in the "direct" connection between the elements. However, the presence of a direct connection does not preclude other connections in which intermediary elements may be present.

[0070] Furthermore, for ease of description, the methods and processes discussed herein may be described in a specific order. However, it should be understood that, unless the context otherwise specifies, intermediate processes may occur before and / or after any part of the described process, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0071] Unless otherwise indicated, all figures used herein to indicate quantities, dimensions, etc., should be understood as being modifiable to application parameters or system standards. In this application, the use of the singular includes the plural unless otherwise expressly stated, and the terms “and” and “or” mean “and / or” unless otherwise indicated. Furthermore, the use of the term “including” and other forms such as “includes” and “included” should be considered non-exclusive. Additionally, unless otherwise expressly stated, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit. In some embodiments, the term association may refer to a relationship (e.g., location, signal, etc.). For example, in some embodiments, a branch may be associated with an output because the branch is coupled to or near the output. In another instance, a signal may be provided based on another signal because in some embodiments, the signals are at least partially associated (e.g., by function, logical operation, enable, disable, or other means). In some embodiments, a port may refer to a node used to receive or provide signals to any circuit (e.g., an input node or an output node).

[0072] Hardware systems can be implemented in many different ways and in many different combinations of hardware, software, and circuit designs. For example, all or part of an implementation may be a circuit system that includes an instruction processor, such as a central processing unit (CPU), microcontroller, or microprocessor; an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a field-programmable gate array (FPGA); or a circuit system that includes discrete logic or other circuit components, including analog circuit components, digital circuit components, or both; or any combination thereof.

[0073] As an example, the circuit system may include discrete interconnect hardware components and / or be implemented in a multi-chip module (MCM) that can be combined on a single integrated circuit die, distributed across multiple integrated circuit dies, or in a co-package of multiple integrated circuit dies. In some embodiments, the integrated circuit package may be a combination of two or more packages. In some embodiments, the last period of a clock cycle may refer to a portion of the clock cycle at the end of the clock cycle (e.g., a period of time that ends at the end of the clock cycle or exactly before the end of the clock cycle).

[0074] The circuit system may further include or access instructions (e.g., software or firmware) that are executed by the circuit system. The instructions may be stored in a tangible storage medium other than transient signals, such as flash memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM); or stored on a magnetic disk or optical disk, such as an optical disc read-only memory (CDROM), hard disk drive (HDD), or other magnetic disk or optical disk; or stored in or on another machine-readable medium. For example, a computer program product may include a storage medium and instructions stored in or on said medium, and when executed by the circuit system in the device, the instructions may cause the device to perform any of the processes described above or illustrated in the figures.

[0075] Various implementation schemes have been described in detail. However, many other implementation schemes are also feasible.

Claims

1. A converter comprising: First input; Second input; and A plurality of digital-to-analog converter (DAC) units, wherein the DAC unit includes a first circuit, a first branch associated with a first output of the DAC unit, and a second branch associated with a second output of the DAC unit, wherein the first circuit is configured to provide a zero-return operation during a first time period within a clock cycle, wherein the DAC unit is configured to provide a signal having a data amplitude of a certain polarity on at least one of the first branch or the second branch during at least a portion of the clock cycle, wherein a first signal at a first input indicates the polarity and a second signal at a second input indicates the data amplitude.

2. The converter according to claim 1, wherein the first signal is a positive or negative sign signal indicating the polarity and the second signal is a data signal indicating the data amplitude.

3. The converter of claim 1, wherein the first circuit includes a first pair of transistors and a second pair of transistors coupled between the first branch and the second branch, wherein each of the first pair of transistors is an N-channel transistor and each of the second pair of transistors is a P-channel transistor.

4. The converter of claim 1, wherein the first circuit is configured to couple the first branch to the second branch for the zeroing operation during the first time period within the clock cycle.

5. The converter of claim 1, further comprising a second circuit configured to select the same DAC unit for up- and down-conversion, such that the rising and falling edges at the first output and the second output are correlated.

6. The converter of claim 1, wherein the first time period is 25% of the clock cycle.

7. The converter of claim 1, wherein the first signal is a positive or negative sign signal indicating the polarity and the second signal is a data signal indicating the data amplitude, wherein the transition of the positive or negative sign signal is provided during the first time period.

8. The converter according to claim 1, wherein the first time period is the last time period of the clock cycle.

9. The converter of claim 1, wherein the first signal includes a positive or negative sign signal indicating the polarity and the second signal includes a data signal indicating the data amplitude, wherein the first signal is provided to a first transistor disposed on the first branch and the data signal is combined with a clock signal associated with the clock cycle and provided to a second transistor.

10. The converter of claim 9, wherein the first transistor is disposed between the second transistor and the first output.

11. The converter of claim 9, wherein the first transistor is disposed between the second transistor and the cascaded transistor coupled to the first output.

12. A converter comprising: A plurality of digital-to-analog converter (DAC) units, each of which includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor is configured to provide a first signal at a first node in response at least partially to a data signal, the second transistor is configured to provide the first signal to a first output in response to a positive or negative signal, the third transistor is configured to provide the first signal to a second output in response to the inverse of the positive or negative signal, and wherein the fourth transistor is configured to couple a second node coupled to the second transistor to a third node coupled to the third transistor during a first time period within a clock cycle.

13. The converter of claim 12, wherein the transition of the positive and negative signals is provided during the first time period.

14. The converter of claim 13, wherein the gate of the first transistor receives the data signal combined with a clock signal in a logical AND operation.

15. The converter of claim 14, further comprising a cascaded transistor coupled to the first output, the cascaded transistor being disposed between the first output and the second transistor.

16. A method for converting digital positive / negative signals and digital amplitude signals into analog signals, the method comprising: At least in part, in response to a data signal being at a first logic level of the data signal and a positive / negative signal being at a first logic level of the positive / negative signal, a first current signal is provided to a first branch coupled to a first port of a digital-to-analog converter (DAC) unit; During a first time period within a first clock cycle, the first branch is coupled to the second branch of the DAC unit, the first time period being after the first current signal is provided to the first branch; The second current signal is provided to the second branch coupled to the second port, at least in part in response to the data signal being at the first logic level of the data signal and the positive / negative signal being at the second logic level of the positive / negative signal; and The first branch is coupled to the second branch during a second time period within the second clock cycle, the second time period being after the second current signal is provided to the second branch.

17. The method of claim 16, further comprising: In response to the data signal being at a second level of the data signal, the first current signal is not provided to the first branch or the second current signal is not provided to the second branch.

18. The method of claim 16, further comprising: A first circuit is used to provide the data signal to the DAC unit, wherein the first circuit is configured to select the DAC unit to receive the data signal such that the rising and falling edges of the signals at the first and second outputs are correlated.

19. The method of claim 16, further comprising: Current is supplied from the power node via the third branch, at least in part, in response to the data signal being at the second level.

20. The method of claim 16, wherein the first time period is between 10% and 40% of the first clock cycle.

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