Chip wiring method and device, computer device and storage medium

Abstract

The application relates to the technical field of chip design, and discloses a chip wiring method, a chip wiring device, computer equipment and a storage medium, the method comprising the following steps: acquiring each path from an input port to an output port for each chip component unit; acquiring and storing wiring resources of the chip component unit according to each path; and completing wiring connection between the chip component units based on the stored wiring resources of the chip component unit. Compared with traditional wiring resources, the abstracted wiring resources do not have irrelevant points between the start point and the end point, any connection between two points is a complete path between the two points, the generated wiring resources are not less and are not redundant. In the subsequent wiring process, the path can be directly acquired through the start point and the end point, so that the number of search times required for finding a path is smaller, and the wiring speed is higher.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to a chip wiring method, apparatus, computer equipment, and storage medium. Background Technology

[0002] Routing in a Field Programmable Gate Array (FPGA) chip refers to the process of connecting the logic elements (such as lookup tables and registers) on the FPGA using routing resources to complete the routing of the user-designed digital circuit. This is a crucial step in FPGA design, determining the performance of the user's design implemented on the FPGA. Routing resources refer to the hardware resources in the FPGA that can be used to interconnect logic resources. These resources include communication channels, switch boxes, and wires. They form the basis of routing, determine the available paths and connection methods, and play a vital role in FPGA routing.

[0003] In FPGA design, routing resources are automatically generated by the FPGA design tools. Routing resources are an abstraction of FPGA hardware resources and a crucial means for FPGA design tools to understand these resources. They play a vital role in resource allocation, congestion management, performance and resource utilization optimization, and timing optimization during the routing process. Proper abstraction of routing resources ensures successful routing.

[0004] However, current methods of abstracting cabling resources result in long cabling times. Summary of the Invention

[0005] In view of this, the present invention provides a chip wiring method, apparatus, computer device and storage medium to solve the problem that current wiring resource abstraction methods lead to long wiring times.

[0006] In a first aspect, the present invention provides a chip wiring method, the method comprising:

[0007] For each type of chip component, obtain each path from the input port to the output port;

[0008] Based on each obtained path, acquire and store the wiring resources of the chip's constituent units;

[0009] The wiring resources of the memory chip components are used to complete the wiring connection between the chip components.

[0010] The routing method proposed in this embodiment, compared to traditional routing resources, abstracts routing resources where there are no unrelated points between the start and end points. Any line connecting two points forms a complete path between them, resulting in no shortage or redundancy in the generated routing resources. Furthermore, in subsequent routing processes, paths can be directly obtained from the start and end points, thus reducing the number of searches required to find a path and making routing faster. In addition, the routing method provided in this embodiment is universal and can be used in various hardware and software architectures.

[0011] In one alternative implementation, a chip component unit may have one or more input ports and one or more output ports.

[0012] In one alternative implementation, the chip assembly includes one or more logic function blocks, or the chip assembly includes one or more switch boxes.

[0013] In one alternative implementation, there are one or more logic function blocks.

[0014] In one alternative implementation, the logic function block includes one or more functional components.

[0015] In one alternative implementation, the switch box includes a multiplexer.

[0016] In one optional implementation, before completing the wiring connection between the chip components based on the wiring resources of the memory chip components, the method further includes:

[0017] The relative positions of each component in the storage cabling resources;

[0018] The wiring resources of the memory chip components are used to complete the wiring connections between the chip components, including:

[0019] Obtain the target location of the target chip component within the chip; the target location is the absolute location within the chip.

[0020] Based on the relative positions of each component in the wiring resources of the target chip's constituent units, the wiring resources are translated to their absolute positions.

[0021] The routing method provided in this embodiment employs a pattern-based routing resource abstraction approach. It combines the basic logic units (i.e., chip components) of the FPGA and their connections into individual patterns, while reusing routing resources of the same type of functional logic blocks and switch boxes. This significantly reduces the size of the routing resources, achieving compressed storage of FPGA routing resources without affecting the number of available resources. This greatly reduces irrelevant or redundant routing resources when FPGA design tools use routing resources to route between two points, significantly reducing the complexity and runtime of subsequent routing processes. This allows FPGA design tools to calculate better routing results at a faster speed.

[0022] In a second aspect, the present invention provides a chip wiring apparatus, the apparatus comprising:

[0023] The path acquisition module is used to acquire each path from the input port to the output port for each type of chip component;

[0024] The abstract module is used to obtain and store the wiring resources of the chip's constituent units based on each obtained path;

[0025] The wiring module is used to complete the wiring connection between the chip components based on the wiring resources of the memory chip components.

[0026] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip wiring method of the first aspect or any corresponding embodiment described above.

[0027] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the chip wiring method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a typical schematic diagram of FPGA hardware structure;

[0030] Figure 2This is a schematic diagram of a partial wiring path of an FPGA chip;

[0031] Figure 3 This is a schematic diagram of the structure of a switch box for an FPGA chip;

[0032] Figure 4 yes Figure 3 The diagram shown includes connection relationship markings for the switch box.

[0033] Figure 5 yes Figure 3 and Figure 4 The wiring resources of the switch box shown are abstracted into a directed acyclic graph.

[0034] Figure 6 This is a schematic flowchart of a chip wiring method according to an embodiment of the present invention;

[0035] Figure 7 yes Figure 3 , Figure 4 The diagram shows the path from port b to port e of the switch box.

[0036] Figure 8 According to an embodiment of the present invention Figure 3 , Figure 4 The diagram shown illustrates the wiring resources between port b and port e of the switch box, abstracted as pat_1.

[0037] Figure 9 According to an embodiment of the present invention Figure 3 , Figure 4 A schematic diagram of the wiring resources of the switch box shown;

[0038] Figure 10 This is a flowchart illustrating another chip wiring method according to an embodiment of the present invention;

[0039] Figure 11 This is a structural block diagram of a chip wiring apparatus according to an embodiment of the present invention;

[0040] Figure 12 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] like Figure 1 The diagram shows a typical FPGA hardware structure. The logic function block Log mainly consists of basic functional components (such as lookup tables, dividers, DSP cores, etc.), and the connections between these components (including multiplexers (MUX)) are called local connections. The switch box Swh consists of multiplexers (MUX). Each logic function block Log is connected to one or more switch boxes Swh, and each switch box Swh is connected to one and only one logic function block Log. Within the switch box Swh, the connections to the multiplexers are also called local connections, while the connections between different switch boxes are called global connections, such as... Figure 1 As shown by the solid black line in the middle.

[0043] Global lines have different directions (e.g., east, west, north, south; some special lines may go southeast, northeast, etc.) and different lengths (e.g., line 1 connects to an adjacent switch box; line 2 connects to a switch box spaced 1 apart, etc.). Therefore, switch boxes can be connected to other switch boxes in different locations via global lines. In this way, a logic function block can be connected to logic function blocks in different locations on the FPGA through a connection relationship of "logic function block -> switch box -> global line -> ... -> global line -> switch box -> logic function block". By changing the control terminal of the multiplexer selector in the switch box, the signal connection relationship can be changed, thereby realizing the "field-programmable" nature of the FPGA.

[0044] FPGA wiring is divided into two parts.

[0045] The first part is called "local routing". Local routing involves selecting a path from the output of a specific logic function within a logic function block to reach the output port of the switch box, such as... Figure 2 Example of a partial wiring path shown ( Figure 2 What is shown is Figure 1 (Partial chip structure within the mid-frame).

[0046] The second part is called "global routing". In global routing, it is necessary to complete the routing from the output port of the switch box, through several global lines, to other switch boxes at a specific location. Of course, it will also pass through other switch boxes in the process. The specific path is: "Swh0->GlobalWire->Swh1->GlobalWire->……->GlobalWire->Swhn".

[0047] In this way, a local connection, a global connection, and finally another local connection can form a path like "logic function block -> switch box -> global line -> ... -> global line -> switch box -> logic function block".

[0048] In reality, whether it's local or global cabling, path selection is achieved by configuring multiplexer control terminals. And the so-called cabling resources are actually these multiplexers.

[0049] A common method for abstracting routing resources is to abstract all components and routing resources into a Directed Acyclic Graph (DAG).

[0050] A directed acyclic graph (DAG) is a graph structure consisting of vertices and edges. Here, we take... Figure 3 Take the wiring resources in the switch box shown as an example. In the traditional process of wiring resource abstraction, the connection relationship between logic ports and components is often abstracted as points, and the routing resources are abstracted as edges.

[0051] then, Figure 4 The switch box ports a, b, c, d, e, f, and the connection relationships between ports and devices 0, 1, 2, 3, 4, 5, 6, 7 are abstracted as points, and the multiplexers g, h, i are abstracted as edges on the DAG. Figure 3 and Figure 4 The wiring resources of the switch box shown are abstracted as Figure 5 The diagram shows a directed acyclic graph.

[0052] When wiring, if it is necessary to connect two points, it is necessary to traverse one of the points and the points connected to it to find a path. For example, when it is necessary to connect port d and port e, first, it is found that port b can be connected to multiplexer h through connection relationship 3. Multiplexer h has two connection relationships 5 and 6.

[0053] First, we traverse connection 5. Connection 5 connects to multiplexer i. Multiplexer i, through connection 7, connects to the destination e. Therefore, this path meets the condition. We then need to traverse connection 6, but find that it connects to port f, which is not the required destination, so this path is invalid. Finally, we find one path: "b->5->7->e".

[0054] This routing method essentially involves traversing all connections from the starting point in a directed acyclic graph (DAG) to find all paths leading to a specific endpoint. However, this method requires traversing every relevant point during routing. As routing resources accumulate, many more points become unreachable, and the algorithm cannot predict whether a given point is achievable, necessitating a traversal of each point. Therefore, when routing between two points, the routing time becomes very long and memory consumption is significant because these routing resources store many paths unrelated to those two points.

[0055] According to an embodiment of the present invention, a chip wiring method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of executable computer instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0056] This embodiment provides a chip wiring method that can be used in computer devices. Figure 6 This is a flowchart of a chip wiring method according to an embodiment of the present invention, such as... Figure 6 As shown, the process includes the following steps:

[0057] Step S601: For each type of chip component, obtain each path from the input port to the output port.

[0058] Specifically, a chip unit may have one or more input ports and one or more output ports. The chip unit may include one or more logic function blocks, or it may include one or more switch boxes. There may be one or more logic function blocks. That is, a chip unit may have only one logic function block or multiple logic function blocks. Different logic function blocks result in different chip units. A logic function block may include one or more functional components, and may also include a multiplexer (MUX). A switch box may include a multiplexer.

[0059] Step S602: Based on each obtained path, acquire and store the wiring resources of the chip component unit.

[0060] In this embodiment, a "Pattern" can be defined to describe the routing resources in the FPGA, thereby reducing storage space and improving routing speed. Figure 3 , Figure 4 Taking the switch box shown as an example, assuming we want to extract the wiring resources from port b to port e, we first perform a traversal search and find that there is only one path from b to e (e.g., Figure 7(As shown). Therefore, the wiring resources between ports b and e can be abstracted into a Pattern:pat_1. In this embodiment, this Pattern will be stored as a whole wiring resource (the multiplexing selector information will also be stored during storage), resulting in the wiring resources as shown. Figure 8 As shown. Similarly, by finding the patterns of any other ports that may have connection relationships, we can ultimately obtain... Figure 9 The wiring resources shown are different from traditional routes. In this embodiment, storing the multiplexer information is only to ensure information integrity, while a traditional route would traverse the inputs or outputs of the multiplexer during wiring. For example:

[0061] In this embodiment, the path is stored as logic device port A->Mux0->Mux1->logic port B. The index is (A, B), and the value is this pattern. Therefore, given the start and end points, this pattern can be obtained without traversing from A to obtain the path.

[0062] In other words, in this embodiment, a path composed of several basic wiring components is considered a Pattern. Unlike traditional wiring resources, a Pattern is not stored in units of basic components (such as muxes), but rather in units of a path composed of several basic components. In traditional wiring, given a port of a basic component, only several other ports directly connected to that port can be obtained. However, when retrieving wiring resources from a Pattern, based on the given start and end ports, several paths connecting the two points can be obtained.

[0063] This embodiment provides a method for abstracting wiring resources based on the connection relationships of components, using Pattern as the basic unit. Specifically, it analyzes the connection relationships of components, abstracting several multiplexers and the connections between multiplexers and between multiplexers and ports into a Pattern. This Pattern is represented as an edge in a directed acyclic graph. The signal senders and receivers (inputs and outputs of logic components, or ports of switch boxes) are abstracted as points in the directed acyclic graph.

[0064] In this embodiment, for the same type of FPGA, only one routing resource extraction is required. Subsequently, the extracted and stored routing resources can be read from a file to complete the routing for the same type of FPGA.

[0065] Step S603: Complete the wiring connection between the chip components based on the wiring resources of the memory chip components.

[0066] In this embodiment, during the routing process, when it is necessary to connect two components (referring to basic logic components, such as LUT, DSP, BRAM, etc., not routing resource components, such as Mux), it is only necessary to check whether there is a connection between the two corresponding points in the routing resources to confirm whether the two points can be connected and how many connection paths there are.

[0067] For example, such as Figure 9 As shown, if connecting ports b and e is required during cabling, then by using b and e as indices to search the cabling resources, all edges starting from b and ending at e—that is, paths—can be obtained. In this embodiment, cabling resources are stored in the form of a Map (a computer data type). A Map can store several data entries, each consisting of two parts: 1. Key (index) and 2. Value. Given an index, the Map can immediately return the value corresponding to that index. In the storage of Patterns, the start and end point information of the Pattern is used as the Key, and the Pattern itself (more precisely, zero, one, or multiple Patterns with the same start and end points but different paths) is used as the Value. Therefore, given the start and end points, several paths that can connect the two points can be obtained.

[0068] Clearly, compared to traditional routing resources, the routing resource proposed in this embodiment has no unrelated points between the starting point (input port) and the ending point (output port). Any connection between two points is a complete path between them, resulting in no shortage of routing resources and no redundancy. Moreover, in subsequent routing processes, the path can be directly obtained from the starting and ending points, thus reducing the number of searches required to find a path and making routing faster. In addition, the routing method provided in this embodiment is universal and can be used in various hardware and software architectures.

[0069] This embodiment provides a chip wiring method that can be used in computer devices. Figure 10 This is a flowchart of a chip wiring method according to an embodiment of the present invention, such as... Figure 10 As shown, the process includes the following steps:

[0070] Step S1001: For each type of chip component, obtain each path from the input port to the output port.

[0071] Specifically, a chip unit may have one or more input ports and one or more output ports. The chip unit may include one or more logic function blocks, or it may include one or more switch boxes. There may be one or more logic function blocks. That is, a chip unit may have only one logic function block or multiple logic function blocks. Different logic function blocks result in different chip units. A logic function block may include one or more functional components, and may also include a multiplexer (MUX). A switch box may include a multiplexer.

[0072] Step S1002: Based on each obtained path, acquire and store the wiring resources of the chip component unit.

[0073] See step S602 in the above embodiments for details.

[0074] Step S1003: Store the relative positions of each component in the wiring resources.

[0075] Step S1004: Obtain the target position of the target chip component in the chip. The target position is the absolute position in the chip.

[0076] Step S1005: Based on the relative positions of each component in the wiring resources of the target chip's constituent units, the wiring resources are translated to their absolute positions.

[0077] For example, from Figure 1 As can be seen, each switch box in the FPGA is identical. For traditional routing resource abstraction methods, the routing resources for each switch box are obtained by traversing the routing process separately. Therefore, even for two identical switch boxes, their routing resources need to be generated twice. This results in a very large memory footprint for routing resources and a long generation time.

[0078] In this embodiment, for switch boxes with the same structure but different locations, only one routing resource is extracted. When storing this routing resource, the component positions are only stored as relative positions, so this routing resource is a universal routing resource for all switch boxes. When routing a switch box, the absolute position of the switch box in the FPGA is first obtained. Using this absolute position and the relative positions stored in the routing resource, the universal switch box routing resource is translated to the exact position of the switch box, and the coordinate information in the routing resource is restored to the exact coordinates. The same applies to logic function blocks. A universal routing resource can be generated for each type of logic function block. When routing a certain logic function block is required, its coordinates are restored to the exact coordinates to obtain a routing resource with a precise position. For example, the routing resource records a pattern like this: "Unit type A coordinate (0,0): Device a -> Unit type A coordinate (0,0): Device b". During routing, if it is necessary to route "cell type A coordinate (10,10): device a" and "cell type A coordinate (10,10): device b", then the aforementioned pattern will be retrieved and its coordinates will be translated (10,10), thus obtaining the target path.

[0079] Therefore, the size of the wiring resources in this embodiment is only related to the type of functional block and switch box. Regardless of the size of the FPGA, the size of the wiring resources in this embodiment remains basically unchanged. The larger the FPGA, the smaller the size of the wiring resources in this embodiment compared to traditional wiring resources.

[0080] In summary, the routing method provided in this embodiment employs a pattern-based routing resource abstraction approach. It combines the basic logic units (i.e., chip components) of the FPGA and their connections into individual patterns, while reusing routing resources of the same type of functional logic blocks and switch boxes. This significantly reduces the size of the routing resources, achieving compressed storage of FPGA routing resources without affecting the number of available resources. This greatly reduces irrelevant or redundant routing resources when FPGA design tools use routing resources to route between two points, significantly reducing the complexity and runtime of the subsequent routing process. This allows FPGA design tools to calculate better routing results at a faster speed.

[0081] This embodiment also provides a chip wiring device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0082] This embodiment provides a chip wiring device, such as Figure 11 As shown, it includes:

[0083] The path acquisition module 1101 is used to acquire each path from the input port to the output port for each type of chip component;

[0084] Abstract module 1102 is used to obtain and store the wiring resources of the chip constituent units based on each obtained path;

[0085] The wiring module 1103 is used to complete the wiring connection between chip components based on the wiring resources of the memory chip components.

[0086] In some alternative implementations, a chip component may have one or more input ports and one or more output ports.

[0087] In some alternative implementations, the chip assembly includes one or more logic function blocks, or the chip assembly includes one or more switch boxes.

[0088] In some alternative implementations, there are one or more logical function blocks.

[0089] In some alternative implementations, a logic function block includes one or more functional components.

[0090] In some alternative implementations, the switch box includes a multiplexer.

[0091] In some alternative embodiments, the device further includes:

[0092] The relative position storage unit is used to store the relative positions of each component in the wiring resources;

[0093] The wiring module 1103 includes:

[0094] The absolute position acquisition unit is used to acquire the target position of the target chip component in the chip, and the target position is the absolute position in the chip.

[0095] The translation unit is used to translate the wiring resources to an absolute position based on the relative positions of each component in the wiring resources of the target chip's constituent units.

[0096] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0097] In this embodiment, the chip wiring device is presented in the form of chip components. Here, a component refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0098] This invention also provides a computer device having the above-described features. Figure 11 The chip wiring device shown.

[0099] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 12 As shown, this computer device can run FPGA design tools. The computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 12 Take a processor 10 as an example.

[0100] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0101] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0102] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0103] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0104] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0105] The computer device also includes input and output devices. The processor 10, memory 20, input devices, and output devices can be connected via a bus or other means. Figure 12 Taking the example of a connection between China and Israel via a bus.

[0106] Input devices can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as touchscreens, keypads, mice, trackpads, touchpads, joysticks, one or more mouse buttons, trackballs, joysticks, etc. Output devices may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0107] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0108] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method of routing a chip, characterized by, The method comprises: For each chip component unit, each path from an input port to an output port is acquired; the chip component unit comprises a plurality of logic function blocks, or the chip component unit comprises a plurality of switch boxes; the logic function block comprises one or more functional components; the switch box comprises a multiplexer selector; the logic function block is composed of basic functional components, each logic function block is connected to one or more switch boxes, and each switch box is connected to one and only one logic function block; the functional component comprises a lookup table, a divider or a DSP core; According to each acquired path, the wiring resources of the chip component unit are acquired and stored; The wiring connection between the chip component units is completed based on the stored wiring resources of the chip component unit; Before the wiring connection between the chip component units is completed based on the stored wiring resources of the chip component unit, the method further comprises: The relative positions of the components in the wiring resources are stored; The wiring connection between the chip component units based on the stored wiring resources of the chip component unit comprises: The target position of the target chip component unit in the chip is acquired, and the target position is an absolute position in the chip; Based on the relative positions of the components in the wiring resources of the target chip component unit, the wiring resources are translated to the absolute position.

2. The method of claim 1, wherein, The input port of the chip component unit is one or more, and the output port is one or more.

3. The method of claim 1, wherein, The logic function block has one or more.

4. A chip wiring device, characterized by The device comprises: A path acquisition module is configured to acquire each path from an input port to an output port for each chip component unit; the chip component unit comprises a plurality of logic function blocks, or the chip component unit comprises a plurality of switch boxes; the logic function block comprises one or more functional components; the switch box comprises a multiplexer selector; the logic function block is composed of basic functional components, each logic function block is connected to one or more switch boxes, and each switch box is connected to one and only one logic function block; the functional component comprises a lookup table, a divider or a DSP core; An abstraction module is configured to acquire and store the wiring resources of the chip component unit according to each acquired path; A wiring module is configured to complete the wiring connection between the chip component units based on the stored wiring resources of the chip component unit; The device further comprises: A relative position storage unit is configured to store the relative positions of the components in the wiring resources; The wiring module comprises: An absolute position acquisition unit is configured to acquire the target position of the target chip component unit in the chip, and the target position is an absolute position in the chip; A translation unit is configured to translate the wiring resources to the absolute position based on the relative positions of the components in the wiring resources of the target chip component unit.

5. A computer device, comprising: Comprise: A memory and a processor, which are connected in communication with each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the chip wiring method of any one of claims 1 to 3.

6. A computer readable storage medium characterized by, The computer readable storage medium stores computer instructions for causing a computer to perform the chip wiring method of any one of claims 1 to 3.

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