Method for preparing stacked transistor, stacked transistor, device and equipment

Abstract

The present application provides a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus, the method comprising: providing a substrate; etching a top substrate, an intermediate sacrificial layer and a bottom substrate in sequence to form an active structure, the active structure comprising a first active structure and a second active structure, the intermediate sacrificial layer after etching being located between the first active structure and the second active structure; forming a first pseudo-gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure; removing the intermediate sacrificial layer after etching to form a first gap; filling the first gap with an insulating material to form an intermediate dielectric isolation layer, the intermediate dielectric isolation layer being used to isolate the first active structure from the second active structure; forming a first transistor and a second transistor based on the first active structure and the second active structure. Through the present application, electrical isolation between the first active structure and the second active structure can be achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When a stacked transistor is prepared using a conventional monolithic stacking solution, the following technical difficulties exist: it is difficult to achieve electrical isolation of the active region. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor, a device and an apparatus to achieve electrical isolation between a first active structure and a second active structure.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, the method comprising: providing a substrate, the substrate comprising a top substrate, an intermediate sacrificial layer and a bottom substrate stacked in sequence; etching the top substrate, the intermediate sacrificial layer and the bottom substrate in sequence to form an active structure, the active structure comprising a first active structure and a second active structure, the intermediate sacrificial layer after etching being located between the first active structure and the second active structure; forming a first dummy gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure; removing the intermediate sacrificial layer after etching to form a first gap; filling the first gap with an insulating material to form an intermediate dielectric isolation layer, the intermediate dielectric isolation layer being used to isolate the first active structure and the second active structure; forming a first transistor and a second transistor based on the first active structure and the second active structure, the first transistor and the second transistor being self-aligned in a direction perpendicular to the channel.

[0006] In some possible embodiments, a first dummy gate structure spaced apart on a surface of a first active structure and a first shallow trench isolation structure wrapping a second active structure are formed, including: forming a second shallow trench isolation structure wrapping the active structure; removing a portion of the second shallow trench isolation structure to expose the first active structure and the etched intermediate sacrificial layer, and forming a first shallow trench isolation structure; and forming a first dummy gate structure based on the first active structure.

[0007] In some possible embodiments, forming a first transistor and a second transistor based on a first active structure and a second active structure includes: forming a first transistor based on the first active structure; flipping and removing the bottom substrate; removing the first shallow trench isolation structure to expose the second active structure; and forming a second transistor based on the second active structure.

[0008] In some possible implementations, before flipping the wafer and removing the bottom substrate, the method further includes: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0009] In some possible implementations, flipping the wafer and removing the bottom substrate includes: flipping the first transistor; and performing wafer thinning and planarization on the bottom substrate to expose the bottom of the second active structure.

[0010] In some possible embodiments, a first transistor is formed based on a first active structure, including: etching a portion of the first active structure along an extension direction of the first active structure to form a first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; removing the first dummy gate structure to form a first gate structure; removing a portion of the first interlayer dielectric layer to form a first source-drain metal; and performing a post-process on top of the first interlayer dielectric layer to form a first metal interconnection layer.

[0011] In some possible embodiments, a second transistor is formed based on a second active structure, including: forming a second dummy gate structure spaced apart on the surface of the second active structure; etching a portion of the second active structure along an extension direction of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; removing the second dummy gate structure and forming a second gate structure; removing a portion of the second interlayer dielectric layer to form a second source-drain metal; and performing a post-process on top of the second interlayer dielectric layer to form a second metal interconnect layer.

[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, comprising: a first transistor; a second transistor, the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel; an intermediate dielectric isolation layer, the intermediate dielectric isolation layer is located between a first active structure of the first transistor and a second active structure of the second transistor, and the intermediate dielectric isolation layer is used to isolate the first active structure and the second active structure.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, electrical isolation between the first active structure and the second active structure can be achieved by providing an intermediate dielectric isolation layer between the first active structure and the second active structure.

[0016] Furthermore, electrical isolation between the first active structure and the second active structure is achieved through an intermediate dielectric isolation layer, which can reduce preparation costs and process difficulty compared to an isolation method using a silicon on insulator (SOI) substrate and performing ion implantation between the first active structure and the second active structure.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;

[0020] Figure 2 This is a schematic diagram of a first structure of a stacked transistor in an embodiment of the present application;

[0021] FIG. 3A to FIG. 3F A schematic diagram of a first preparation process of a stacked transistor in an embodiment of the present application;

[0022] Figure 4 This is a schematic diagram of a second structure of a stacked transistor in an embodiment of the present application;

[0023] FIG. 5A to FIG. 5C A schematic diagram of a second preparation process of a stacked transistor in an embodiment of the present application;

[0024] The above pictures:

[0025] 10. stacked transistor; 11. first transistor; 111. first active structure; 112. first gate structure; 113. first source-drain structure; 114. first source-drain metal; 115. first interlayer dielectric layer; 116. first gate dielectric layer; 117. first spacer; 118. first metal interconnect layer; 12. second transistor; 121. second active structure; 122. second gate structure; 123. second source-drain structure; 124. second source-drain metal; 125. second interlayer dielectric layer; 126. second gate dielectric layer; 127. second spacer; 128. second metal interconnect layer Interconnection layer; 13, intermediate dielectric isolation layer; 14, shallow trench isolation layer; 15, first insulating layer; 16, carrier wafer; 21, substrate; 211, bottom substrate; 212, intermediate sacrificial layer; 213, top substrate; 22, fin-like structure; 221, first part of the fin-like structure; 222, second part of the fin-like structure; 231, second shallow trench isolation structure; 232, first shallow trench isolation structure; 241, first dummy gate structure; 242, second dummy gate structure; 25, columnar structure; 251, first part of the columnar structure; 252, second part of the columnar structure; 26, first inner sidewall. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0027] As Moore's Law continues to deepen, after the technology node of gate-all-around FET (GAA), continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0028] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic stacking scheme, and the second is a sequential scheme.

[0029] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0030] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0031] Among them, when using a monolithic stacked transistor, the active areas of the upper transistor and the lower transistor need to be electrically isolated. The current methods include: (1) using an SOI substrate and utilizing a BOX buried oxide layer to form a natural electrical isolation layer; (2) forming an electrical isolation layer by ion implantation of P-type ions, N-type ions or oxygen ions.

[0032] However, the cost of SOI substrates is very high, and it is difficult to obtain SOI substrates with suitable thickness of BOX layer and device layer; the process control of ion implantation is difficult, and the diffusion effect of implanted ions will have a great impact on the thermal budget of subsequent processes, and the implanted ions will also cause damage to the device structure.

[0033] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor to achieve electrical isolation between a first active structure and a second active structure.

[0034] In the embodiments of the present application, the stacked transistor can be applied to semiconductor devices such as memory and processor.

[0035] In one embodiment, the stacked transistor may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged back to back. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process, and the first active structure and the second active structure are self-aligned.

[0036] In the embodiment of the present application, the first transistor and the second transistor in the stacked transistor may be transistors of the same type, such as any one of the following: a fin-type field effect transistor, a nanosheet field effect transistor, a planar transistor, and a vertical field effect transistor.

[0037] Figure 2 It is a stacked transistor composed of fin field effect transistors, and the following is combined Figure 2 The structure of the stacked transistor shown is used to illustrate the method for preparing the stacked transistor provided in the embodiment of the present application.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application, see Figure 1 As shown, the method for preparing the stacked transistor may include:

[0039] S101, providing a substrate, wherein the substrate comprises a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence.

[0040] It can be understood that the preparation process of the substrate may include: epitaxially growing a layer of sacrificial layer material on the original substrate (i.e., the bottom substrate) to form an intermediate sacrificial layer; then, epitaxially growing the same semiconductor material as the bottom substrate on top of the intermediate sacrificial layer to form a top substrate. The substrate formed by the above preparation method includes a top substrate, an intermediate sacrificial layer, and a bottom substrate stacked in sequence. Among them, the top substrate is used to prepare the front transistor (i.e., the first transistor), and the bottom substrate is used to prepare the back transistor (i.e., the second transistor).

[0041] In some embodiments, the material of the intermediate sacrificial layer may be silicon germanium (SiGe) material, or other semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0042] In some embodiments, when the type of stacked transistor is different, the arrangement of the substrate is also different accordingly. For example, when the stacked transistor is any one of a fin field effect transistor, a planar transistor, and a vertical field effect transistor, the bottom substrate and the top substrate may be silicon (Si) material. When the stacked transistor is a nanosheet field effect transistor, the bottom substrate and the top substrate may be a stack formed by alternating deposition of silicon and silicon germanium.

[0043] In some embodiments, the height of the top substrate can be designed according to actual needs, such as 50 nm, the height of the bottom substrate is greater than the top substrate, and the height of the middle sacrificial layer is less than the height of the top substrate.

[0044] S102, etching the top substrate, the middle sacrificial layer and the bottom substrate in sequence to form an active structure.

[0045] The active structure includes a first active structure and a second active structure, and the etched intermediate sacrificial layer is located between the first active structure and the second active structure.

[0046] It is understandable that the active structure can be obtained by patterning the active structure through standard process steps, and etching the top substrate, the middle sacrificial layer and the bottom substrate in sequence. Since the active structure includes the first active structure in the first transistor and the second active structure in the second transistor, a larger etching depth can be used when etching the substrate. The height of the active structure should be greater than a preset height threshold. For example, the height of the active structure can be greater than 100nm. It should be noted that the height of the active structure can be designed according to actual needs, and the embodiments of the present application do not specifically limit this.

[0047] In some embodiments, when the stacked transistor is a fin-type field effect transistor, the specific steps of the above S102 may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form multiple fin structures; the upper half of the fin structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the fin structure (i.e., the bottom silicon substrate after etching) is the second active structure.

[0048] In some embodiments, when the stacked transistor is a nanosheet field effect transistor, the specific steps of S102 above may include: etching the top stacked substrate, the middle silicon germanium sacrificial layer and the bottom stacked substrate in sequence to form a columnar structure; the upper half of the columnar structure (i.e., the top stacked substrate after etching) is the first active structure, and the lower half of the columnar structure (i.e., the bottom stacked substrate after etching) is the second active structure.

[0049] In some embodiments, when the stacked transistor is a planar transistor, the specific steps of S102 above may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form a block structure; the upper half of the block structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the block structure (i.e., the bottom silicon substrate after etching) is the second active structure.

[0050] In some embodiments, when the stacked transistor is a vertical field effect transistor, the specific steps of S102 above may include: etching the top silicon substrate, the middle silicon germanium sacrificial layer and the bottom silicon substrate in sequence to form a columnar structure; the upper half of the columnar structure (i.e., the top silicon substrate after etching) is the first active structure, and the lower half of the columnar structure (i.e., the bottom silicon substrate after etching) is the second active structure.

[0051] In some embodiments, when the stacked transistor is a fin field effect transistor, after forming a plurality of fin structures, a fin cutting process may be performed on the plurality of fin structures so that the heights of the plurality of fin structures remain consistent.

[0052] In some possible implementations, after S102, the method may further include: filling oxide above the active structure to form a second shallow trench isolation (STI). The height of the second shallow trench isolation structure is greater than the height of the active structure.

[0053] In the embodiment of the present application, the oxide forming the second shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0054] In some embodiments, after forming the shallow trench isolation structure, the method may further include: performing a chemical-mechanical planarization (CMP) process on the second shallow trench isolation structure.

[0055] In an embodiment of the present application, chemical mechanical planarization is performed on the second shallow trench isolation structure, so that when the second shallow trench isolation structure is subsequently etched, the corresponding corrosion depths of the second shallow trench isolation structure in different areas are the same, thereby making the height of the exposed active structure the same.

[0056] S103, forming a first dummy gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure.

[0057] In some possible embodiments, after forming the second shallow trench isolation structure, the above S103 may include: removing a portion of the second shallow trench isolation structure to expose the first active structure and the etched intermediate sacrificial layer, and forming the first shallow trench isolation structure; based on the first active structure, forming a first dummy gate structure.

[0058] It is understandable that the second shallow trench isolation structure wraps the entire active structure, and a portion of the second shallow trench isolation structure can be removed by etching, so that the first active structure and the intermediate sacrificial layer after etching are exposed. For the sake of distinction, the second shallow trench isolation structure after etching can be referred to as the first shallow trench isolation structure, and the first shallow trench isolation structure wraps the second active structure. Then, a semiconductor material (such as polysilicon (poly Si)) is deposited in the gate region of the first transistor to form a first pseudo-gate structure of the first transistor.

[0059] It should be noted that the etching process mentioned in the embodiments of the present application may include but is not limited to any of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, and the embodiments of the present application do not specifically limit this.

[0060] In the embodiment of the present application, the solvent used for etching the second shallow trench isolation structure may be: DHF solution or BOE solution. The solvent used in the etching process in the embodiment of the present application may be selected according to actual conditions and is not limited to the above DHF solution or BOE solution.

[0061] In some embodiments, the method of forming the first dummy gate structure may include: photolithographically opening a gate region of the first transistor, and depositing a semiconductor material in the gate region of the first transistor to form the first dummy gate structure of the first transistor.

[0062] It can be understood that the first dummy gate structure and the first shallow trench isolation structure are interconnected at the middle sacrificial layer after etching.

[0063] S104, removing the etched middle sacrificial layer to form a first gap.

[0064] It is understandable that the etched intermediate sacrificial layer between the first active structure and the second active structure can be selectively removed to form a first gap. During the selective removal process, the first dummy gate structure can provide structural support for the first active structure, so that the position of the first active structure in the first transistor does not change, and the first active structure and the second active structure still maintain self-alignment.

[0065] S105, filling the first gap with an insulating material to form an intermediate dielectric isolation layer, wherein the intermediate dielectric isolation layer is used to isolate the first active structure from the second active structure.

[0066] It can be understood that an insulating material (such as a low K material) is filled in the first gap to form an intermediate dielectric isolation layer, and the intermediate dielectric isolation layer can achieve electrical isolation between the first transistor and the second transistor by isolating the first active structure from the second active structure.

[0067] In some embodiments, after the first dummy gate structure is formed, an insulating material may be deposited on both sides of the first dummy gate structure to form a first spacer.

[0068] It should be noted that the first spacer and the intermediate dielectric isolation layer can be prepared at the same time.

[0069] S106 , forming a first transistor and a second transistor based on the first active structure and the second active structure, wherein the first transistor and the second transistor are self-aligned in a direction perpendicular to the channel.

[0070] It can be understood that, based on the first active structure, subsequent processes can be performed to form a first transistor, and after flipping the first transistor, subsequent processes can be performed based on the second active structure to form a second transistor. The first transistor and the second transistor are self-aligned in a direction perpendicular to the channel.

[0071] In some possible implementations, the above S106 may include: forming a first transistor based on the first active structure; flipping the wafer and removing the bottom substrate; removing the first shallow trench isolation structure to expose the second active structure; and forming a second transistor based on the second active structure.

[0072] It can be understood that after the first active structure is formed, the first transistor is flipped over so that the bottom substrate is placed upward; the bottom substrate is removed by etching, and the first shallow trench isolation structure that wraps the second active structure is removed, so that the second active structure is exposed; then, subsequent processes are performed based on the second active structure to form a second transistor.

[0073] In some possible embodiments, a first transistor is formed based on a first active structure, including: etching a portion of the first active structure along an extension direction of the first active structure to form a first source-drain structure; depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; removing the first dummy gate structure to form a first gate structure; removing a portion of the first interlayer dielectric layer to form a first source-drain metal; and performing a post-process on top of the first interlayer dielectric layer to form a first metal interconnection layer.

[0074] In some embodiments, etching a portion of the first active structure along the extension direction of the first active structure and forming a first source-drain structure may include: removing a portion of the first active structure by etching to provide a source-drain groove of the first transistor. Using the first spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the first transistor by selective epitaxial growth to fill the source-drain groove of the first transistor, and then forming the first source-drain structure on the strained material by a heavy doping process.

[0075] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0076] In some embodiments, depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer may include: depositing an insulating material (such as silicon dioxide (SiO2)) above the first active structure and the first source-drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source-drain structure.

[0077] In some embodiments, removing the first dummy gate structure and forming a first gate structure may include: removing the first dummy gate structure by etching to expose the gate region of the first transistor, and depositing metal material in the gate region of the first transistor to form the first gate structure of the first transistor.

[0078] In an embodiment of the present application, the metal materials of the first gate structure and the second gate structure may include: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), and titanium aluminum nitride (TiAlN). The materials of the first gate structure and the second gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0079] In the embodiment of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0080] In some embodiments, before preparing the first gate structure, the method may further include: depositing a semiconductor material on the surface of the first active structure to form a first gate dielectric layer of the first transistor, wherein the first gate dielectric layer is used to isolate the first active structure from the first gate structure.

[0081] In some embodiments, removing a portion of the first interlayer dielectric layer to form a first source-drain metal may include: etching a portion of the first interlayer dielectric layer located above the first source-drain structure until an upper surface of the first source-drain structure is exposed to form a first source-drain metal groove. Depositing a metal material in the first source-drain metal groove to obtain the first source-drain metal.

[0082] In some embodiments, a back-end process is performed above the first interlayer dielectric layer to form a first metal interconnection layer, which may include: performing interconnection line dielectric deposition, metal line formation, lead pad formation and other processes on the first interlayer dielectric layer to form the first metal interconnection layer of the first transistor.

[0083] In some possible implementations, before flipping the wafer and removing the bottom substrate, the method may further include: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0084] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0085] In some possible implementations, the flipping and removing the bottom substrate may include: flipping the first transistor; and performing wafer thinning and planarization on the bottom substrate to expose the bottom of the second active structure.

[0086] It can be understood that after the first transistor is flipped, the bottom substrate is placed upward and the bottom substrate can be removed by wafer thinning and planarization (such as CMP), wherein the CMP process stops at the surface of the first shallow trench isolation structure, so that the surface of the second active structure is also exposed.

[0087] In some embodiments, after removing the bottom substrate, the first shallow trench isolation structure can be removed by etching to expose the second active structure for subsequent preparation of the second transistor.

[0088] It should be noted that during the etching of the first shallow trench isolation structure, a shallow trench isolation structure of a preset height may be left as a shallow trench isolation layer, which is located between the first gate structure and the second gate structure and is used to isolate the first gate structure from the second gate structure.

[0089] In some possible embodiments, the formation of the second transistor based on the second active structure may include: forming a second dummy gate structure spaced apart on the surface of the second active structure; etching a portion of the second active structure along an extension direction of the second active structure to form a second source-drain structure; depositing semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; removing the second dummy gate structure and forming a second gate structure; removing a portion of the second interlayer dielectric layer to form a second source-drain metal; and performing a post-process on top of the second interlayer dielectric layer to form a second metal interconnect layer.

[0090] In some embodiments, forming a second dummy gate structure spaced apart on the surface of the second active structure may include: photolithographically opening a gate region of the second transistor, and depositing a semiconductor material in the gate region of the second transistor to form a second dummy gate structure of the second transistor.

[0091] It should be noted that the first dummy gate structure and the second dummy gate structure may be prepared using the same semiconductor material or different semiconductor materials, and this embodiment of the present application does not specifically limit this.

[0092] In some embodiments, after forming the second dummy gate structure, the method may further include: depositing an insulating material on both sides of the second dummy gate structure to form a second spacer.

[0093] It should be noted that the first spacer and the second spacer may be prepared using the same insulating material or different insulating materials, which is not specifically limited in the embodiments of the present application.

[0094] In some embodiments, etching a portion of the second active structure along the extension direction of the second active structure to form a second source-drain structure may include: removing a portion of the second active structure by etching to provide a source-drain groove of the second transistor. Using the second spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain groove of the second transistor by selective epitaxial growth to fill the source-drain groove of the second transistor, and then forming the second source-drain structure on the strained material by a heavy doping process.

[0095] In some embodiments, depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer may include: depositing an insulating material above the second active structure and the second source-drain structure to form a second interlayer dielectric layer; the second interlayer dielectric layer may cover the second active structure and the second source-drain structure.

[0096] It should be noted that the first interlayer dielectric layer and the second interlayer dielectric layer may be prepared using the same semiconductor material or different semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0097] In some embodiments, removing the second dummy gate structure and forming a second gate structure may include: removing the second dummy gate structure by etching to expose the gate region of the second transistor, and depositing metal material in the gate region of the second transistor to form a second gate structure of the second transistor.

[0098] It should be noted that the first gate structure and the second gate structure may be prepared using the same metal material or different metal materials, and this embodiment of the present application does not specifically limit this.

[0099] In some embodiments, before preparing the second gate structure, the method may further include: depositing a semiconductor material on the surface of the second active structure to form a second gate dielectric layer of the second transistor, wherein the second gate dielectric layer is used to isolate the second active structure from the second gate structure.

[0100] It should be noted that the first gate dielectric layer and the second gate dielectric layer may be prepared using the same semiconductor material or different semiconductor materials, and this embodiment of the present application does not specifically limit this.

[0101] In some embodiments, removing a portion of the second interlayer dielectric layer to form a second source-drain metal may include: etching a portion of the second interlayer dielectric layer located above the second source-drain structure until the upper surface of the second source-drain structure is exposed to form a second source-drain metal groove. Depositing a metal material in the second source-drain metal groove to obtain the second source-drain metal.

[0102] In some embodiments, a back-end process is performed above the second interlayer dielectric layer to form a second metal interconnect layer, which may include: performing interconnect line dielectric deposition, metal line formation, lead pad formation and other processes on the second interlayer dielectric layer to form a second metal interconnect layer of the second transistor.

[0103] Below, the stacked transistor provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a schematic diagram of the first structure of a stacked transistor in an embodiment of the present application. Figure 2 (a) is a top view of the stacked transistor. It should be noted that, for ease of understanding, the top view only shows the fin structure, gate structure, and source-drain structure; (b) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0104] See also Figure 2 As shown, the stacked transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the stacked transistor 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, upper and lower, respectively denoted as a first part and a second part, the first part is used as a first active structure 111 in the first transistor 11, and the second part is used as a second active structure 121 in the second transistor 12. An intermediate dielectric isolation layer 13 is provided between the first active structure 111 and the second active structure 121, and the intermediate dielectric isolation layer 13 is used to isolate the first active structure 111 and the second active structure 121.

[0105] In combination with the above preparation method, Figure 2 The manufacturing process of the stacked transistor 10 is described below. Figure 2 The stacked transistor 10 shown may be FIG. 3A to FIG. 3F The process shown is prepared FIG. 3A to FIG. 3F It is a schematic diagram of the first preparation process of the stacked transistor in the embodiment of the present application.

[0106] In an example, taking the first transistor 11 and the second transistor 12 as fin-type field effect transistors as an example, a first preparation process of the stacked transistor 10 may include the following steps:

[0107] Step 1: Provide a bottom substrate 211 (such as a Si substrate); epitaxially grow a layer of SiGe material on the bottom substrate 211 as an intermediate sacrificial layer 212; and then epitaxially grow Si material on the intermediate sacrificial layer 212 to form a top substrate 213 (see Figure 3A (a) in the figure.

[0108] The bottom substrate 211 , the middle sacrificial layer 212 and the top substrate 213 together constitute the substrate 21 .

[0109] Step 2: The top substrate 213, the middle sacrificial layer 212 and the bottom substrate 211 are sequentially etched to form a plurality of fin structures 22 (see Figure 3A (b) in the figure.

[0110] The height of the fin structure 22 is greater than 100 nm.

[0111] Step 3: Fill the fin structure 22 with oxide to form a second shallow trench isolation structure 231; then, perform chemical mechanical planarization on the second shallow trench isolation structure 231 (see Figure 3A (c) in the figure.

[0112] The height of the second shallow trench isolation structure 231 is greater than the height of the fin structure 22 , and can cover a plurality of fin structures 22 .

[0113] Step 4: Etch a portion of the second shallow trench isolation structure 231 until the first portion 221 of the fin structure and the etched intermediate sacrificial layer 212 are exposed (see Figure 3B (a) in the figure.

[0114] The etched second shallow trench isolation structure 231 wraps the second portion 222 of the fin-shaped structure, and for the sake of distinction, may be referred to as a first shallow trench isolation structure 232 .

[0115] Step 5: Photolithography opens the gate region of the first transistor 11, and deposits polysilicon at the gate region of the first transistor 11 to form a first dummy gate structure 241 (see Figure 3B(b) in the figure.

[0116] The first dummy gate structure 241 spans across the first portion 221 of the fin structure and is spaced apart on the surface of the first portion 221 of the fin structure.

[0117] Step 6: Selectively remove the etched middle sacrificial layer 212 to form a first gap (see Figure 3B (c) in the figure.

[0118] In the process of removing the etched middle sacrificial layer 212 , the first dummy gate structure 241 provides structural support for the first portion 221 of the fin structure.

[0119] Step 7: Fill the first gap with lowK material to form an intermediate dielectric isolation layer 13. At the same time, first spacers 117 are formed on both sides of the first dummy gate structure 241 (see Figure 3C (a) in the figure.

[0120] Step 8: Etch a portion of the fin structure to form a source-drain groove of the first transistor 11, and perform source-drain epitaxial growth at the source-drain groove of the first transistor 11 to form a first source-drain structure 113. Then, a semiconductor material is deposited above the first portion 221 of the fin structure to form a first interlayer dielectric layer 115 (see Figure 3C (b) in the figure.

[0121] Step 9: Remove the first dummy gate structure 241, then deposit an insulating material on the surface of the first portion 221 of the fin structure to form a first gate dielectric layer 116, and then deposit a metal in the gate region of the first transistor 11 to form a first gate structure 112 (see Figure 3C (c) in the figure.

[0122] Step 10: Prepare a first source-drain metal 114 on the first source-drain structure 113, and then perform a back-end process on the first interlayer dielectric layer 115 to form a first metal interconnect layer 118 (see Figure 3D (a) in the figure.

[0123] Step 11: Deposit oxide on the first metal interconnect layer 118 to form a first insulating layer 15; then bond the first insulating layer 15 to the carrier wafer 16; then, flip the first transistor 11 bonded to the carrier wafer 16 so that the bottom substrate 211 is placed upward (see Figure 3D (b) in the figure.

[0124] Step 12: Use wafer thinning and CMP process to remove the bottom substrate 211 until the bottom of the fin structure 22 is exposed (see Figure 3D (c) in the figure.

[0125] Step 13: Selectively etch the first shallow trench isolation structure 232 until the second portion 222 of the fin structure is exposed (see Figure 3E (a) in the figure.

[0126] A first shallow trench isolation structure 232 of a certain thickness is retained as a shallow trench isolation layer 14, and the shallow trench isolation layer 14 is used to isolate the first gate structure 112 from the second gate structure 122.

[0127] Step 14: Photolithography is performed to open the gate region of the second transistor 12, and polysilicon is deposited at the gate region of the second transistor 12 to form a second dummy gate structure 242 (see Figure 3E (b) in the figure.

[0128] Step 15: Form the second spacer 127, the second source-drain structure 123 and the second interlayer dielectric layer 125 of the second transistor 12 (see Step 7 and Step 8 for the specific preparation process) (see Step 15). Figure 3E (c) in the figure.

[0129] Step 16: forming the second gate structure 122 of the second transistor 12 (the specific preparation process can refer to step 9).

[0130] Step 17: forming the second source-drain metal 124 and the second metal interconnection layer 128 of the second transistor 12 (the specific preparation process can refer to step 10).

[0131] At this point, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are fin-type field effect transistors is completed.

[0132] Below, the stacked transistor provided in the embodiment of the present application is described by taking the first transistor and the second transistor as nanosheet field effect transistors as an example. Figure 4 This is a schematic diagram of the second structure of the stacked transistor in the embodiment of the present application. Figure 4 (a) is a top view of the stacked transistor. It should be noted that, for ease of understanding, the top view only shows the nanosheet structure, gate structure, and source-drain structure; (b) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the nanosheet structure (i.e., CC' direction).

[0133] See also Figure 4As shown, the stacked transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the stacked transistor 10 is a plurality of nanosheet structures. The nanosheet structure is divided into two parts, upper and lower, respectively denoted as the first part and the second part, the first part is used as the first active structure 111 in the first transistor 11, and the second part is used as the second active structure 121 in the second transistor 12. An intermediate dielectric isolation layer 13 is provided between the first active structure 111 and the second active structure 121, and the intermediate dielectric isolation layer 13 is used to isolate the first active structure 111 and the second active structure 121.

[0134] In combination with the above preparation method, Figure 4 The manufacturing process of the stacked transistor 10 is described below. Figure 4 The stacked transistor 10 shown may be FIG. 5A to FIG. 5C The process shown is prepared FIG. 5A to FIG. 5C Schematic diagram of the second preparation process of the stacked transistor in the embodiment of the present application.

[0135] In one example, taking the first transistor 11 and the second transistor 12 as nanosheet field effect transistors as an example, the second preparation process of the stacked transistor 10 may include the following steps:

[0136] Step 1: Provide a bottom substrate 211, the bottom substrate 211 is a stacked layer formed by alternately depositing Si material and SiGe 1 material (i.e., a stacked layer composed of Si layer and SiGe 1 layer); deposit SiGe 2 material on the bottom substrate 211 as an intermediate sacrificial layer 212; then alternately deposit Si material and SiGe 1 material on the intermediate sacrificial layer 212 to form a top substrate 213 (see Figure 5A (a) in the figure.

[0137] In order to facilitate subsequent selective etching, the Ge concentration in the SiGe 1 material is different from the Ge concentration in the SiGe 2 material.

[0138] In the embodiment of the present application, the above-mentioned deposition of SiGe 2 material as the middle sacrificial layer 212 is only an example, and other semiconductor materials can also be selected to prepare the middle sacrificial layer 212, or other forms of material layers (such as stacked layers) can be selected to prepare the middle sacrificial layer, and the embodiment of the present application does not specifically limit this. For example, Si material, SiGe 2 material and Si material are alternately deposited in sequence to form a stacked layer, and the stacked layer is used as the middle sacrificial layer 212. Among them, the stacked layer formed by Si material, SiGe 2 material and Si material can improve the etching selectivity.

[0139] Step 2: The top substrate 213, the middle sacrificial layer 212 and the bottom substrate 211 are sequentially etched to form a columnar structure 25; oxide is filled above the columnar structure 25 to form a second shallow trench isolation structure 231; then, the second shallow trench isolation structure 231 is chemically and mechanically planarized; a portion of the second shallow trench isolation structure 231 is etched until the first portion 251 of the columnar structure and the etched middle sacrificial layer 212 are exposed to form a first shallow trench isolation structure 232; then, a first dummy gate structure 241 is formed (see Figure 5A (b) in the figure) (For the specific process, please refer to the fifth step of the first preparation process of the stacked transistor).

[0140] Step 3: Selectively remove the etched middle sacrificial layer 212 to form a first gap (see Figure 5A (c) in the figure.

[0141] Step 4: Selectively remove a portion of the first portion 251 of the columnar structure located in the first source-drain region of the first transistor 11 to expose the first source-drain region for subsequent preparation of the first source-drain structure 113 (see Figure 5B (a) in the figure.

[0142] Step 5: Etch the SiGe 1 material layer at the junction of the first portion 251 of the columnar structure (i.e., the upper half of the stack) and the first source / drain region to form a first inner sidewall 26 (see Figure 5B (b) in the figure.

[0143] Step 6: Fill the first gap with lowK material to form an intermediate dielectric isolation layer 13, and fill the first inner sidewall 26 with lowK material to achieve isolation between the SiGe 1 material layer and the first source-drain structure 113; at the same time, form first spacers 117 on both sides of the first dummy gate structure 241 (see Figure 5B (c) in the figure.

[0144] Step 7: Form a first source-drain structure 113, a first interlayer dielectric layer 115, a first gate structure 112, a first gate dielectric layer 116 and a first metal interconnect layer 118 (see Figure 5C (a) in the figure) (For the specific process, please refer to the eighth to tenth steps of the first preparation process of the stacked transistor).

[0145] Step 8: After flipping, remove the bottom substrate 211 until the upper surface of the second portion 252 of the columnar structure is exposed (see Figure 5C (b)) (For the specific process, please refer to the eleventh and twelfth steps of the first preparation process of the stacked transistor).

[0146] Step 9: Form the second transistor according to the standard process (see Figure 5C(c) in the figure) (For the specific process, please refer to steps 13 to 17 of the first preparation process of the stacked transistor).

[0147] At this point, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are nanosheet field effect transistors is completed.

[0148] In an embodiment of the present application, when the first transistor and the second transistor are planar transistors or vertical field effect transistors, except that the active structure is different from the active structure of the stacked transistor composed of the above-mentioned fin-type field effect transistors and the active structure of the stacked transistor composed of the above-mentioned nanosheet field effect transistors, the other structures are the same as the stacked transistor composed of the above-mentioned fin-type field effect transistors and the stacked transistor composed of the above-mentioned nanosheet field effect transistors; accordingly, except for the different preparation process of the active structure, the preparation process of the remaining structures is the same as the preparation process shown in the above-mentioned example, and the embodiment of the present application will not elaborate on this.

[0149] In the embodiment of the present application, electrical isolation between the first active structure and the second active structure can be achieved by providing an intermediate dielectric isolation layer between the first active structure and the second active structure.

[0150] Furthermore, electrical isolation between the first active structure and the second active structure is achieved through an intermediate dielectric isolation layer, which can reduce preparation costs and process difficulty compared to an isolation method using an SOI substrate and performing ion implantation between the first active structure and the second active structure.

[0151] In the embodiment of the present application, the above-mentioned method for preparing the stacked transistor not only optimizes the process flow of the stacked transistor, but also takes into account the consistency, defect density and alignment of the active regions of the upper and lower transistors (i.e., the first transistor and the second transistor). In addition, the above-mentioned method for preparing the stacked transistor further solves the long-standing problems existing in the mainstream technical solutions of the stacked transistor, such as complex process, fixed type (monolithic solution), difficult alignment, and high defect density of the upper semiconductor material (sequential solution), thereby promoting the industrialization of the stacked transistor technology.

[0152] Secondly, the preparation method of the stacked transistor described in the embodiment of the present application is also an organic fusion of the current sequential and monolithic stacked transistor solutions. The mature technology has high reuse, can avoid a large amount of expensive process development to save costs, and has high feasibility. At the same time, in the embodiment of the present application, the stacked transistor adopts a self-aligned "back-to-back" active area and metal gate design, and the front and back transistors (i.e., the first transistor and the second transistor) have independent signal and power supply networks, and are connected through local interconnection. Without changing the extremely miniaturized 4T track unit design, the metal wiring resources are greatly released (can be increased by more than 60%), and there is huge space in the direction of collaborative optimization of process design. Finally, the isolation method of the stacked transistor is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, fin field effect transistors, nanosheet field effect transistors and even vertical field effect transistors (VTFETs) without the need for special process development for specific device architectures. It has strong flexibility and is highly extensible from the perspective of semiconductor process node iteration. The inverted stacked transistor is very advanced in concept, has important industrial value, and has strong practicality and broad prospects for expansion.

[0153] The present application embodiment provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be found in the above Figure 2 The stacked transistors shown are not described in detail here.

[0154] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above stacked transistor. The specific definition of the stacked transistor can be found in the above Figure 2 The stacked transistors shown are not described in detail here.

[0155] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0156] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: Providing a substrate, the substrate comprising a top substrate, a middle sacrificial layer and a bottom substrate stacked in sequence; Sequentially etching the top substrate, the middle sacrificial layer and the bottom substrate to form an active structure, wherein the active structure includes a first active structure and a second active structure, and the etched middle sacrificial layer is located between the first active structure and the second active structure; forming a first dummy gate structure spaced apart on a surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure; Removing the etched middle sacrificial layer to form a first gap; Filling the first gap with an insulating material to form an intermediate dielectric isolation layer, wherein the intermediate dielectric isolation layer is used to isolate the first active structure from the second active structure; forming a first transistor and a second transistor based on the first active structure and the second active structure, wherein the first transistor and the second transistor are self-aligned in a direction perpendicular to a channel; The process of forming a first dummy gate structure spaced apart on the surface of the first active structure and a first shallow trench isolation structure wrapping the second active structure comprises: forming a second shallow trench isolation structure wrapping the active structure; removing a portion of the second shallow trench isolation structure to expose the first active structure and the etched intermediate sacrificial layer, and forming the first shallow trench isolation structure; forming the first dummy gate structure based on the first active structure; and connecting the first dummy gate structure and the first shallow trench isolation structure at the etched intermediate sacrificial layer.

2. The method for preparing a stacked transistor according to claim 1, characterized in that: The forming of a first transistor and a second transistor based on the first active structure and the second active structure comprises: Based on the first active structure, forming the first transistor; Flipping the wafer and removing the bottom substrate; removing the first shallow trench isolation structure to expose the second active structure; Based on the second active structure, the second transistor is formed.

3. The method for preparing a stacked transistor according to claim 2, characterized in that: Before flipping the wafer and removing the bottom substrate, the method further includes: Depositing an insulating material on an upper surface of the first transistor to form an insulating layer; The insulating layer is bonded to a carrier wafer.

4. The method for preparing a stacked transistor according to claim 2, characterized in that: The flipping and removing the bottom substrate comprises: Flipping the first transistor; The bottom substrate is subjected to wafer thinning and planarization processes to expose the bottom of the second active structure.

5. The method for preparing a stacked transistor according to claim 2, wherein: The forming of the first transistor based on the first active structure includes: Etching a portion of the first active structure along an extension direction of the first active structure to form a first source-drain structure; Depositing a semiconductor material on the first active structure and the first source-drain structure to form a first interlayer dielectric layer; removing the first dummy gate structure and forming a first gate structure; removing a portion of the first interlayer dielectric layer to form a first source-drain metal; A back-end process is performed on the first interlayer dielectric layer to form a first metal interconnection layer.

6. The method for preparing a stacked transistor according to claim 2, characterized in that: The forming of the second transistor based on the second active structure comprises: forming a second dummy gate structure spaced apart on the surface of the second active structure; Etching a portion of the second active structure along an extension direction of the second active structure to form a second source-drain structure; Depositing a semiconductor material on the second active structure and the second source-drain structure to form a second interlayer dielectric layer; removing the second dummy gate structure and forming a second gate structure; removing a portion of the second interlayer dielectric layer to form a second source / drain metal; A back-end process is performed on the second interlayer dielectric layer to form a second metal interconnection layer.

7. A stacked transistor, characterized in that: The stacked transistor is prepared by the method for preparing the stacked transistor according to any one of claims 1 to 6, wherein the stacked transistor comprises: a first transistor; a second transistor, the first transistor and the second transistor being self-aligned in a direction perpendicular to a channel; an intermediate dielectric isolation layer, the intermediate dielectric isolation layer being located between a first active structure of the first transistor and a second active structure of the second transistor, the intermediate dielectric isolation layer being used to isolate the first active structure from the second active structure; The intermediate dielectric isolation layer is formed by removing the intermediate sacrificial layer of the substrate and then filling it with insulating material.

8. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 7.

9. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 8, wherein the semiconductor device is arranged on the circuit board.

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