Methods for making Josephson junctions

Abstract

A method for reducing junction resistance variation of a junction in a quantum information processing device fabricated using a two-step deposition process. In one aspect, the method includes providing a dielectric substrate (208); forming a first resist layer (210) on the dielectric substrate; forming a second resist layer (212) on the first resist layer; and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through the thickness of the first resist layer, the second resist layer includes a second opening (218) aligned above the first opening and extending through the thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned above the second opening and extending through the thickness of the third resist layer.

Description

[0001] This application is a divisional application of a patent application with an application date of September 18, 2017, application number 201780096732.7, and invention name “Method for manufacturing a Josephson junction”. Technical Field

[0002] The present disclosure relates to reducing junction resistance variation in a two-step deposition process. Background Art

[0003] Quantum computing is a relatively new computing method that exploits quantum effects such as superposition of ground states and entanglement to perform certain calculations more efficiently than traditional digital computers. In contrast to digital computers that store and manipulate information in the form of bits (e.g., "1" or "0"), quantum information processing devices are able to manipulate information using quantum bits (qubits). A quantum bit can refer to a quantum device that is capable of a superposition of multiple states (e.g., data in both "0" and "1" states) and / or is capable of superimposing data in multiple states itself. According to conventional terminology, the superposition of "0" and "1" states in a quantum system can be expressed, for example, as α│0>+β│1>. The "0" and "1" states of a digital computer are analogous to the │0> ground state and │1> ground state of a quantum bit, respectively. Value │α│ 2 represents the probability that the qubit is in the │0> state, and the value │β│ 2 represents the probability that the qubit is in the ground state │1>. Summary of the Invention

[0004] Generally, one innovative aspect of the subject matter described herein can be embodied as a method comprising the following acts: providing a dielectric substrate; forming a first resist layer on the dielectric substrate; forming a second resist layer on the first resist layer; and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through the thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through the thickness of the third resist layer.

[0005] Implementations of these methods can optionally include one or more of the following features. In some implementations, a thickness of each of the first opening, the second opening, and the third opening extends along a first direction perpendicular to a surface of the dielectric substrate, wherein each of the first opening, the second opening, and the third opening has a respective width extending along a second direction orthogonal to the first direction, and wherein the width of the second opening is less than the width of the first opening and less than the width of the third opening.

[0006] In some embodiments, the first opening in the first resist layer and the third opening in the third resist layer are defined by exposing the first, second, and third resist layers in a first pattern, and the second opening in the second resist layer is defined by exposing the first, second, and third resist layers in a second pattern. The first, second, and third resist layers are then subsequently developed.

[0007] In some embodiments, a first material layer is deposited through the first, second, and third openings at a first deposition angle relative to the substrate, and a second material layer is deposited through the first, second, and third openings at a second deposition angle relative to the substrate. The first and second material layers may be superconducting materials.

[0008] In some embodiments, prior to depositing the second material layer, surface oxidation of the first material layer is performed to provide an oxidized region of the first material layer. In some embodiments, a portion of the first material layer, a portion of the oxidized region, and a portion of the second material layer form a portion of a quantum information processing device (e.g., a Josephson junction), where the quantum information processing device can be a qubit.

[0009] In some embodiments, the first resist layer, the second resist layer, the third resist layer, and excess deposited material are removed, for example, using an etching process.

[0010] In some embodiments, the dielectric substrate and the material deposition source are arranged according to a first orientation relative to each other during deposition of a first material layer, and according to a second orientation relative to each other during deposition of a second material layer, wherein the first orientation is different from the second orientation. The substrate may be rotated after deposition of the first material layer and before deposition of the second material layer. Alternatively, the position of the material deposition source may be changed relative to the dielectric substrate after deposition of the first material layer and before deposition of the second material layer.

[0011] In some embodiments, the first opening, the second opening, and the third opening define a mask opening region that exposes the surface of the dielectric substrate. The first undercut width may be defined by the distance between a first edge of the second opening on a first side of the mask opening region and a first edge of the third opening. The second undercut width may be defined by the distance between a second edge of the second opening on a second side of the mask opening region opposite the first side of the mask opening region and a second edge of the third opening. The first undercut width may be approximately zero.

[0012] In some embodiments, the second undercut width is greater than a thickness of a material deposited on a sidewall of the third resist layer during the first deposition process.

[0013] In some embodiments, during deposition of the first material layer, a first side of the mask opening region is closer to a material deposition source than a second side of the mask opening region.

[0014] Certain embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. For example, in some embodiments, the techniques disclosed herein can be used to reduce junction variation and / or improve performance uniformity between adjacent Josephson junctions on a substrate. In some embodiments, the presently disclosed techniques improve the overall uniformity of performance of a quantum information processing device by reducing dimensional variation in the opening region within a mask layer, which may be caused by deposition parameters (e.g., deposition angle) and / or accidental deposition on the sidewalls of the mask layer. Additionally, the overall uniformity of performance of a quantum information processing device can be improved by reducing dimensional variation in the opening region within the mask layer (e.g., waviness in the opening region due to deposition roughness), which may be caused by the effects of grain growth and grain morphology (e.g., aluminum grain growth) in the deposited layer. By reducing the dimensional variation in the openings within the mask layer, the form and shape of quantum information processing devices (such as Josephson junctions and qubits) fabricated using the mask layer can be made more uniform. Consequently, the resulting quantum information processing device exhibits more uniform operating characteristics, which facilitates the use and design of global microwave actuation methods for driving / operating a group of two or more qubits using a single controller. In some embodiments, reducing grain growth effects in deposited layers improves the yield of quantum information processing devices (e.g., Josephson junctions and qubits) by reducing the number of junctions disrupted by grain growth and grain morphology (e.g., grain boundaries) of the deposited layers.

[0015] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A-1C are diagrams showing various views of an exemplary two-step deposition process through a two-layer resist mask.

[0017] Figures 2A-2C is a diagram showing various views of an exemplary two-step deposition process through a three-layer resist mask.

[0018] Figures 3A-3D are diagrams of cross-sectional views of a two-step deposition process for various exemplary triple-layer resist masks.

[0019] Figures 4A-4C is a diagram showing various views of another exemplary two-step deposition process through a three-layer resist mask.

[0020] Figure 5 is a flow chart of an exemplary process for forming a multi-layer resist mask.

[0021] Figure 6 is a flow chart of an exemplary process for forming a Josephson junction using a multi-layer resist mask. DETAILED DESCRIPTION

[0022] The subject matter of the present disclosure relates to techniques for reducing junction resistance across a junction. In particular embodiments, the present disclosure relates to achieving uniform Josephson junction resistance across a substrate.

[0023] Quantum computing requires coherently processing the quantum information stored in the quantum bits (qubits) of a quantum computer. Superconducting quantum computing is a promising embodiment of quantum computing technology, in which quantum information processing devices are partially formed of superconducting materials. Superconducting quantum computers are typically multi-level systems, in which only the first two levels are used as the basis for calculation. In certain embodiments, quantum information processing devices (such as qubits) are operated at very low temperatures, making it possible to achieve superconductivity and making it so that thermal fluctuations do not cause transitions between energy levels. In addition, it may be preferred that the quantum information processing device operates with low energy loss and dissipation (for example, quantum circuit elements exhibit a high quality factor Q). Low energy loss and dissipation can help avoid, for example, quantum decoherence.

[0024] The fabrication of integrated quantum information processing devices with superconducting components typically involves depositing and patterning layers of superconducting materials, dielectrics, and metals. Some quantum information processing devices, such as qubits, use a Josephson junction structure. A Josephson junction can be made by sandwiching a thin layer of non-superconducting material between two layers of superconducting material.

[0025] Refer to the following Figures 1A-1C An exemplary process for fabricating a Josephson junction using a two-layer resist mask is described. Figures 1A-1C is a diagram showing various views of an exemplary two-step deposition process through a two-layer resist mask 100 . Figure 1AA schematic diagram of a two-layer resist mask 100 is shown in plan view 102, cross-sectional view 104 through axis AA, and cross-sectional view 106 through axis BB. The two-layer resist mask 100 is deposited on a substrate 108 and includes two layers of resist 110 and 112, wherein the first resist layer 110 has a first thickness 111 and the second resist layer 112 has a second thickness 113, wherein the thickness is defined in a direction perpendicular to the surface of the substrate 108 on which the resist layers are formed. The two resist layers 110 and 112 can be different materials, such as poly(methyl methacrylate) (PMMA), poly(methyl methacrylate-co-methacrylic acid) (P(MMA-MAA)), ZEP520, UV5 / UVIII, or similar resist compositions. In one example, the first resist layer 110 is P(MMA-MAA) and the second resist layer 112 is PMMA. The first thickness 111 of the first resist layer 110 and the second thickness 113 of the second resist layer 112 can be the same or different thicknesses. For example, the first thickness 111 and the second thickness 113 can be in the range of 100-1000 nm thick.

[0026] A first resist layer 110 is deposited on substrate 108 and includes, for example, a P(MMA-MAA) layer. A second resist layer 112 is deposited on top of first resist layer 110 and includes, for example, a PMMA layer. In some embodiments, first resist layer 110 and second resist layer 112 are baked to remove solvent from the deposited layers.

[0027] The first resist layer 110 and the second resist layer 112 are patterned to define openings (e.g., opening 114 and opening 116) within the resist. The first opening 114 within the first resist layer 110 can be formed by selectively exposing the first resist layer 110 and the second resist layer 112 to a temperature in the range of 0-1000 μC / cm 2 The first dose range is defined by a source (e.g., light or electron beam, not shown) between 1 and 2, such that the exposed portions of the first resist layer 110 become soluble or insoluble when treated with a developer solution, while the exposed portions of the second resist layer 112 do not become soluble or insoluble. In one example, the first dose is 350 μC / cm 2 To expose the first resist layer P(MMA-MAA). A first opening 114 in the first resist layer 110 can be defined as extending from the top surface of the first resist layer 110 through the thickness of the first resist layer to the substrate 108 along a direction perpendicular to the surface of the substrate 108 (e.g., along the z-axis), and includes a width 118 extending along a direction orthogonal to the thickness of the first resist layer (e.g., along the x-axis and / or y-axis).

[0028] The second opening 116 in the second resist layer 112 can be formed by exposing the first resist layer 110 and the second resist layer 112 to an etchant at 1000-2000 μC / cm 2 The second dose range is defined by a source (e.g., light or electron beam, not shown) between 100 μC / cm and 1500 μC / cm, which is high enough to make the exposed portions of the second resist layer 112 soluble or insoluble when treated with a developer solution. In one example, the second dose is 1500 μC / cm 2 to expose the PMMA second resist layer 112. The second opening 116 in the second resist layer 112 can be defined along a direction perpendicular to the surface of the substrate 108 (e.g., along the z-axis) from the top surface of the second resist layer 112 through the thickness of the second resist layer to the top surface of the first resist layer 110, and include a width 120 extending along a direction orthogonal to the thickness of the second resist layer (e.g., along the x-axis and / or y-axis).

[0029] After deposition and exposure of each resist layer, the first resist layer 110 and the second resist layer 112 are then developed to selectively remove the exposed or unexposed areas of the respective resist layers, depending on the type of resist used (e.g., positive or negative resist). Developing the first and second resist layers removes the resist material from the respective openings defined in the first and second resist layers. In some embodiments, one or more development processes are used, depending in part on the composition of the respective resist layers. For example, the development process can include a 1:3 ratio of methyl isobutyl ketone:isopropyl alcohol (MIBK:IPA).

[0030] In some embodiments, at least a portion of the second opening 116 defined in the second resist layer 112 is aligned over at least a portion of the first opening 114 defined in the first resist layer 110 such that a portion of the substrate 108 is exposed.

[0031] In some embodiments, the width 120 of the second opening 116 is less than the width 118 of the first opening 114. For example, in some embodiments, the width 120 is 200 nm and the width 118 is 400 nm. The width 120 of the second opening 116 in the second resist layer 112 can define a characteristic dimension (e.g., width) of one or more deposited structures (e.g., a top contact or a bottom contact, such as a top or bottom contact of a Josephson junction).

[0032] After selectively removing the resist in the predetermined areas, the material that will form a portion of the quantum information processing device (e.g., a qubit comprising a Josephson junction) can be deposited within the open areas and on the remaining resist. In some embodiments, an angled shadow evaporation technique can be used to deposit the material that will form a portion of the quantum information processing device (e.g., a qubit comprising a Josephson junction). For example, a substrate with a patterned resist can be placed in a deposition chamber (e.g., a chamber of a physical vapor deposition system) and subjected to a first layer deposition process (in which a flux of material to be deposited is introduced at a non-perpendicular angle relative to the substrate such that a portion of the patterned resist layer can block or "shadow" at least some of the deposited material), and then subjected to a second layer deposition process (in which the orientation of the substrate relative to the material deposition source is changed).

[0033] Figure 1B A schematic diagram of the two-layer resist mask 100 is shown in plan view 122, cross-sectional view 124 through axis AA, and cross-sectional view 126 through axis BB after a first deposition of material for forming a portion of a Josephson junction from a first deposition flow direction 125. The first deposition of material from the first deposition flow direction 125 forms a first deposition structure (e.g., a bottom contact 128 for a Josephson junction) on the substrate 108 and within the opening region of the resist mask (e.g., the aligned portion of the first opening 114 and the second opening 116). The first deposition flow direction 125 of the deposited material (e.g., a material flux from a source) includes a component along the x-axis parallel to the surface of the substrate 108 and is oriented at an angle 130 relative to the z-axis perpendicular to the substrate 108, such that portions of the second resist layer 112 near the edges of the second opening 116 block at least some of the deposited material from the first deposition flow direction 125 within the opening region. The first deposition flow direction 125 can be oriented, for example, at an angle 130 between 10 and 80 degrees relative to the z-axis. In some embodiments, the first deposition of material results in a deposition layer 132 on the second resist layer 112. The deposition layer 132 may include a top surface region 132a on the top surface of the second resist layer 112 and a sidewall region 132b on the sidewalls of the second resist layer 112. Hereinafter, the first deposition flow direction may also be referred to as "first deposition" or "flux"; the second deposition flow direction may also be referred to as "second deposition" or "flux."

[0034] After the first layer deposition step, the substrate 108 can be transferred to air or to a separate chamber where surface oxidation of the deposited material is promoted. In some embodiments, the substrate can be left in the deposition chamber for in-situ oxidation. After oxidation, the substrate can then undergo a second layer deposition step where a second deposition material is deposited to form a second deposition structure (e.g., a top contact 148 for a Josephson junction).

[0035] In some embodiments, the orientation of substrate 108 relative to the deposition material source changes. For example, depending in part on the configuration of the deposition system, the deposition material source can be rotated relative to substrate 108 or substrate 108 can be rotated relative to the material deposition source.

[0036] Figure 1C A schematic diagram of the two-layer resist mask 100 after a second deposition of material for forming a Josephson junction is shown in plan view 142, cross-sectional view 144 through axis AA, and cross-sectional view 146 through axis BB. A second deposition flow direction 151 of the deposited material includes a component along the y-axis parallel to the surface of the substrate 108 and is oriented at an angle 150 relative to the z-axis, such that the second resist layer and / or a portion of the previously deposited first material layer from the first deposition process near the edge of the opening region blocks at least some of the deposited material from the second deposition flow direction 151 within the opening region. The second deposition flow direction 151 can, for example, be oriented at an angle 150 between 10 and 80 degrees relative to the z-axis. The orientation angle 150 during the second deposition can be different from the orientation angle 130 during the first deposition. For example, in some embodiments, the substrate surface can be oriented at an angle 130 relative to the first deposition flow direction 125 of the deposited material during the first deposition step and at an angle 150 relative to the second deposition flow direction 151 that is orthogonal to the first angle 130 during the first deposition step.

[0037] After the mask evaporation process, the resist can be removed in a stripping step to remove unwanted material and complete the fabrication of the quantum information processing device (e.g., a qubit including a Josephson junction). Depending on the chemical composition of the resist material, stripping can be performed using a variety of solvents and / or chemical methods.

[0038] In some cases, the deposition process (such as Figures 1A-1CThe shielded evaporation process described herein (described above) deposits material in a non-uniform manner and results in non-uniform performance of quantum information processing devices (e.g., qubits including Josephson junctions). For example, sidewall region 132b from a first deposition step can shield at least a portion of opening 116 (as shown in cross-sectional view 146), causing at least a portion of a second deposition layer (e.g., top contact 148) deposited during a second deposition step to have a width 152 that is different from the desired width 120 defined by opening 116 in second resist layer 112.

[0039] Variations in layer width caused by the shadowing effect of the first deposited layer may result in non-uniformities in the deposited layers. For example, the junction resistance of a Josephson junction is inversely proportional to the cross-sectional area where the first superconducting layer of the junction intersects the second superconducting layer of the junction. Non-uniformities in the deposition of the width of the second superconducting layer (e.g., width 152 is different from the desired width 120) may result in variations in junction resistance by changing the cross-sectional area of ​​overlap between the first and second superconducting layers of the junction. Additionally, due to variations in shadowing effects (e.g., variations in deposition angles 130, 150), the resistance may be non-uniform between different devices at different locations on substrate 108. In turn, non-uniform junction resistance may cause a quantum information processing device (such as a superconducting qubit) that includes the junction to exhibit non-uniform operating frequencies.

[0040] The technology disclosed herein can be used to reduce the shielding effect caused by material deposited on the sidewalls of the resist. The shielding effect occurs when the resist mask and / or accidental deposition on the resist mask inadvertently blocks or affects at least a portion of the incident material flux from being deposited through the openings in the resist mask. The shielding effect may cause the resulting structure deposited through the openings of the resist mask to have a final size that is different from one or more desired sizes, and may also cause roughening of the resulting structure deposited through the openings of the resist mask. The shielding effect may be caused by material accidentally deposited on one or more surfaces of the mask, where the material changes or blocks a portion of the opening of the resist mask. By reducing the shielding effect, in some embodiments, a structure with a final size that is closer to the desired size can be obtained. In addition, reducing the shielding effect can result in a final size that is more uniform between multiple structures, which in turn can result in more uniform operating characteristics (e.g., Josephson junction resistance) between multiple devices.

[0041] The technology disclosed herein includes the introduction of a three-layer resist stack to reduce shadowing effects caused by sidewall deposition. For example, a multi-layer shadow mask is defined on a substrate, comprising a first resist layer, a second resist layer, and a third resist layer, wherein each resist layer includes an opening having a respective width. The second resist layer includes an opening width that defines the desired feature size of the deposited junction. The third resist layer thickness and opening width are selected to prevent deposition on the sidewalls of the second resist layer, which would otherwise block material flux through the opening in the second resist layer during the second deposition step.

[0042] Figures 2A-2C is a diagram showing various views of an exemplary two-step deposition process through a three-layer resist mask 200 . Figure 2A A schematic diagram of a three-layer resist mask 200 is shown in a plan view 202, a cross-sectional view 204 through axis AA, and a cross-sectional view 206 through axis BB. The three-layer resist mask 200 is deposited on a substrate 208 and includes three layers of resist: a first resist layer 210 having a first thickness 211, a second resist layer 212 having a second thickness 213, and a third resist layer 214 having a third thickness 215, wherein the resist layer 214 is the top layer of the three-layer resist mask and is visible in the plan view 202 of the three-layer resist mask 200.

[0043] The first thickness 211 of the first resist layer 210, the second thickness 213 of the second resist layer 212, and the third thickness 215 of the third resist layer 214 can be the same or different thicknesses, for example, in the range of 100-1000 nm in a direction perpendicular to the substrate 108. In one example, the first resist layer 210 has a first thickness 211 of 500 nm, the second resist layer 212 has a thickness 213 of 300 nm, and the third resist layer 214 has a third thickness 215 of 500 nm.

[0044] The three resist layers 210, 212, and 214 can be poly(methyl methacrylate) (PMMA), poly(methyl methacrylate-co-methacrylic acid) (P(MMA-MAA)), ZEP520, UV5 / UVIIII, or similar resist compositions. Different resist materials are selected for the resist layers that contact each other to facilitate the formation of openings within the resist layers. For example, the first resist layer and the second resist layer have different resist compositions, and the second resist layer and the third resist layer have different resist compositions. In one example, the first resist layer 210 is P(MMA-MAA), the second resist layer 212 is PMMA, and the third resist layer 214 is P(MMA-MAA).

[0045] The first resist layer includes a first opening 216, wherein the first opening 216 extends from a top surface of the first resist layer 210 through a first thickness 211 to the substrate 208 in a direction perpendicular to the surface of the substrate 208 (e.g., along the z-axis). The second resist layer includes a second opening 218, wherein the second opening 218 extends from a top surface of the second resist layer 212 through a second thickness 213 to the top surface of the first resist layer 210 in a direction perpendicular to the surface of the substrate 208 (e.g., along the z-axis). The third resist layer 214 includes a third opening 220, wherein the third opening 220 extends from a top surface of the third resist layer 214 through a third thickness 215 to the top surface of the second resist layer 212 in a direction perpendicular to the surface of the substrate 208 (e.g., along the z-axis). Together, the openings 216, 218, and 220 are aligned relative to each other such that a portion of the substrate 208 is exposed, as depicted, for example, in cross-sectional view 204.

[0046] The first opening 216 in the first resist layer 210 includes a width 222, the second opening 218 in the second resist layer 212 includes a width 224, and the third opening 220 in the third resist layer 214 includes a width 226. Width 222, width 224, and width 226 can be different values, for example, between 10 nm and 10 microns. Other widths are also possible. Width 222, width 224, and width 226 extend along a direction (for example, along the x-axis and / or y-axis) orthogonal to the corresponding thickness of each corresponding resist layer 210, 212, 214.

[0047] In some embodiments, one or more dimensions (eg, width) of a deposited feature (eg, a top contact or a bottom contact, such as a bottom or top contact of a Josephson junction) can be defined by the width 224 of the second opening 218, as described below with reference to Figures 2B-2C discussed in more detail.

[0048] The resist layers of the three-layer resist mask 200 can be deposited and patterned as follows. A first resist layer 210 is deposited on (e.g., spun onto) the substrate 208. A second resist layer 212 is deposited (e.g., spun onto) the first resist layer 210. The second resist layer 212 is a different resist material than the first resist layer 210. A third resist layer 214 is deposited (e.g., spun onto) the second resist layer 212, wherein the third resist layer 214 is a different resist material than the second resist layer 212.

[0049] In some embodiments, after each resist layer is deposited and before the subsequent resist layer is deposited, a baking step is performed to bake out the solvent from each resist layer. The baking step can also include baking all deposited resist layers simultaneously. The baking temperature and baking time for each resist layer can depend in part on the material of the resist layer and the thickness of the resist layer.

[0050] In some embodiments, respective resist layers of the three-layer resist mask 200 are exposed to respective patterns to define one or more features (e.g., openings 216, 218, and 220) in each respective layer of the multilayer resist mask using electron beam lithography. The respective patterns for defining the one or more features (e.g., openings) in each layer can be defined by one or more write files for an electron beam lithography system. Each exposure for defining a pattern comprising one or more features (e.g., openings) can include an exposure dose, wherein the particular exposure dose depends in part on the resist material and the thickness of the resist layer. For example, the exposure dose for P(MMA-MAA) ranges from 0 to 1000 μC / cm 2 In another example, the exposure dose of PMMA is in the range of 1000-2000 μC / cm 2 .

[0051] The exposure dose can be selected to define features in certain resist layers of the multilayer resist mask but not in other resist layers. For example, a resist layer composed of P(MMA-MAA) requires a much lower exposure dose than a resist layer composed of PMMA, so that a sufficiently low exposure dose (e.g., 350 μC / cm 2 ) will expose the resist layer composed of P(MMA-MAA) and define one or more features, while the resist layer composed of PMMA will not be exposed and will not define one or more features.

[0052] In one example, the first exposure dose is selected such that the exposure dose is sufficient to define features corresponding to a pattern in the first resist layer 210 and the third resist layer 214 (e.g., a P(MMA-MAA) resist layer), but insufficient to define features corresponding to the pattern in the second resist layer 212 (e.g., a PMMA resist layer). The second exposure dose is selected such that the exposure dose is sufficient to define features corresponding to another pattern in the first resist layer 210, the second resist layer 212, and the third resist layer 214 (e.g., 1500 μC / cm 2 ).

[0053] In some embodiments, the triple-layer resist mask 200 is first exposed at a high dose to define features in all three resist layers, for example, in a single pattern, and then the triple-layer resist mask 200 is exposed at a low dose to define features in, for example, the first resist layer 210 and the third resist layer 214. The triple-layer resist mask 200 can be first exposed at a low dose and then exposed at a high dose.

[0054] In some embodiments, the first resist layer 210 and the third resist layer 214 have the same width of corresponding openings (e.g., opening 216 and opening 220) defined in the resist layers, and wherein the openings are aligned directly over each other (with the second resist layer 212 therebetween).

[0055] After deposition and exposure of each resist layer, depending on the type of resist used for each layer (e.g., positive or negative resist), the first resist layer 210, the second resist layer 212, and the third resist layer 214 are then developed to selectively remove the exposed or unexposed areas of each resist layer. The first resist layer 210, the second resist layer 212, and the third resist layer 214 are developed to remove the resist material from each opening defined in each of the first resist layer 210, the second resist layer 212, and the third resist layer 214. In some embodiments, one or more development processes are used, depending in part on the composition of each resist layer. In some embodiments, the development process is a single-step process and includes a developer, such as methyl isobutyl ketone:isopropyl alcohol (MIBK:IPA) (e.g., a ratio of 1:3), with a development time ranging from 45 to 90 seconds. In one example, the multilayer resist mask was developed in MIBK:IPA for 45 seconds to achieve an opening of 100 nm-1000 nm and an undercut width of 100 nm.

[0056] In some embodiments, a first resist layer 210 and a second resist layer 212 are deposited and patterned using electron beam lithography by exposing them to respective first and second doses, and subsequently a third resist layer 214 is then deposited and patterned by exposing the triple-layer resist mask 200 to a third dose.

[0057] In combination with or in place of electron beam lithography, deep ultraviolet lithography (DUV lithography) can be used to expose and pattern one or more openings in the resist layer of the three-layer resist mask 200. A resist material can be selected for each of the first resist layer, the second resist layer, and the third resist layer that is compatible with electron beam lithography (e.g., P(MMA-MAA), PMMA), compatible with DUV lithography (e.g., UV6), or compatible with both electron beam lithography and DUV lithography (e.g., P(MMA-MAA), PMMA). The range of exposure doses for patterning the UV6 resist layer using DUV lithography can include 18-28 mJ / cm 2 In one example, the exposure dose used to pattern the UV6 resist layer is 25 mJ / cm 2 The exposure dose for patterning the resist layer of PMMA using DUV lithography can include >500 mJ / cm 2 The dose is based in part on the sensitivity of PMMA at the wavelength of the DUV lithography system (e.g., 248 nm).

[0058] In one example, a first resist layer 210 and a second resist layer 212 compatible with electron beam lithography (e.g., P(MMA-MAA) and PMMA, respectively) are deposited, and a third resist layer compatible with DUV lithography (e.g., UV6) is deposited thereon. DUV lithography can be used to expose the third resist layer 214 using a mask defining a pattern. Subsequently, electron beam lithography can be used to expose and pattern the first resist layer 210 and the second resist layer 212 in the same manner as described above.

[0059] In another example, the first resist layer 210 and the second resist layer 212 can be deposited using a material compatible with electron beam lithography and patterned by exposure using electron beam lithography. Subsequently, a third resist layer 214 compatible with DUV lithography can be deposited on the second resist layer 212 and exposed using DUV lithography.

[0060] In another example, the first resist layer 210 and the second resist layer 212 can be deposited using a material compatible with DUV lithography and patterned using DUV lithography by exposure. In some embodiments, the second resist layer 212 is a resist material sensitive to ultraviolet light (e.g., UV6), and the first resist layer 210 is a lift-off layer (LOL). Subsequently, the third resist layer 214 is deposited on the second resist layer using a material compatible with electron beam lithography and patterned using electron beam lithography by exposure.

[0061] In another example, the first resist layer 210, the second resist layer 212, and the third resist layer 214 include a resist material compatible with DUV lithography (e.g., UV6, UV210) and a lift-off layer material (e.g., LOL, LOR, PMGI). The first resist layer 210 and the second resist layer 212 can be deposited and patterned using one or more masks in a DUV lithography system, and then the third resist layer can be deposited on top of the second resist layer and patterned by a mask in the DUV lithography system by exposure. The first resist layer 210, the second resist layer 212, and the third resist layer 214 can also all be deposited and then patterned in at least one exposure step using DUV lithography.

[0062] Once the first resist layer 210, the second resist layer 212, and the third resist layer 214 are deposited and patterned, one or more developing processes are used to develop the three-layer resist mask 200. The developing process can include using a developer such as MIBK:IPA (1:3) to remove the exposed or unexposed resist material (e.g., depending on the positive or negative resist). The developing process can also include using AZ300MIF, 0.26N developer (e.g., 2.38% tetramethylammonium hydroxide) or similar developer to develop, for example, a resist layer comprising a UV6 resist material and a LOL resist material. It should be noted that the developer for developing one or more resist layers must be compatible with the other resist layers (e.g., not eroding or damaging the other resist layers). For example, AZ300MIF is used to develop UV6 resist materials and does not damage or erode PMMA resist materials.

[0063] In some embodiments, the width 226 of the third opening 220 is wider than the width 224 of the second opening 218, wherein a portion of the third opening 220 is aligned over the second opening 218. The width 226 of the third opening 220 can be, for example, in the range of 20 nm to 20 μm, and the width 224 of the second opening 218 can be, for example, in the range of 10 nm to 10 μm. For example, the width 226 of the third opening 220 is 400 nm, and the width 224 of the second opening 218 is 200 nm. In another example, the width 226 is 500 nm, and the width 224 is 300 nm. Other widths may also be used.

[0064] In some embodiments, the width 226 of the third opening 220 is greater than the width 224 of the second opening 218. At least a portion of the third opening 220 in the third resist layer 214 of the three-layer resist mask 200 is aligned over at least a portion of the second opening 218 in the second resist layer 212, exposing a portion of the top surface of the second resist layer 212. In some embodiments, at least a portion of the third opening 220 in the third resist layer 214 is aligned over at least a portion of the second opening 218 in the second resist layer 212 and at least a portion of the first opening 222 in the first resist layer 210, exposing a portion of the surface of the substrate 208. For example, in the three-layer resist mask 200 shown in the schematic plan view 202, the alignment of the first opening 222, the second opening 224, and the third opening 226 exposes a portion 225 of the top surface of the second resist layer 212 and a portion 227 of the surface of the substrate 208.

[0065] In some embodiments, the first opening 216, the second opening 218, and the third opening 220 define a mask opening area 221 that exposes a surface of the substrate 208. A first side of the mask opening area 221 includes a first undercut width 228 defined by a distance between a first edge of the second opening 218 and a first edge of the third opening 220. A second side of the mask opening area 221, directly opposite the first side of the mask opening area 221, includes a second undercut width 230 defined by a distance between a second edge of the second opening 218 and a second edge of the third opening 220.

[0066] In some embodiments, the first side (including the first undercut width 228) and the second side (including the second undercut width 230) of the mask opening region 221 are defined in part based on their respective proximity to a material deposition source, with reference to FIG. Figures 2B-2C In some embodiments, the opening in the resist layer can be part of a larger design that defines at least a portion of a quantum information processing device (e.g., a qubit including a Josephson junction). For example, Figure 2A As shown in the plan view 202 , the opening defines the layout of a bottom contact of the Josephson junction and a top contact of the Josephson junction overlapping the bottom contact.

[0067] In some embodiments, by exposing the third resist layer to a pattern narrower than the pattern exposed on the first resist layer, the third resist layer can have a third opening width that is smaller than the width of the first opening of the first resist layer and can additionally be offset (e.g., not exactly aligned with the first opening, but still within the boundaries of the first opening), as described with reference to FIG. Figure 4A discussed in more detail.

[0068] After selectively removing the resist in predetermined areas of the three-layer resist mask 200 to provide first opening 216, second opening 218, and third opening 220, a shadowed evaporation technique can be used to deposit materials that will form portions of circuit elements. For example, shadowed evaporation can be used to form Josephson junctions that will form portions of quantum information processing devices (such as qubits). Specifically, the substrate with the patterned resist is placed in a deposition chamber (e.g., a chamber of a physical vapor deposition system) and subjected to a first layer deposition process. The deposited materials can include, for example, gold, silver, platinum, niobium, molybdenum, tantalum, aluminum, and indium.

[0069] Figure 2B A schematic diagram of the three-layer resist mask 200 after a first deposition of material for forming a Josephson junction from a first deposition flow direction 251 is shown in a plan view 240, a cross-sectional view 242 through the axis AA, and a cross-sectional view 244 through the axis BB. During the first deposition step, the first deposition flow direction 251 is oriented at an angle 250 relative to the z-axis, which is perpendicular to the surface of the substrate 208, so that a portion of the third resist layer 214 near the edge of the third opening 220 blocks at least some of the first deposited deposition material from the first deposition flow direction 251 within the opening area. The first deposition flow direction 251 can, for example, be oriented at an angle 250 between 10 and 80 degrees relative to the z-axis.

[0070] In some embodiments, the first side of the mask opening region 221 including the first undercut width 228 is defined by the distance difference between the respective edges of the second opening 218 and the third opening 220 that are closer to the material deposition source. Figure 2B As shown in the plan view 240 and the cross-sectional view 244 of the three-layer resist mask 200, for the first deposition flow direction 251, the first undercut width 228 and the second undercut width 230. As shown, for example, in Figure 2B In the plan view 240 and the cross-sectional view 244 of the three-layer resist mask 200, for the first deposition flow direction 251, the second side of the mask opening area 221 including the second undercut width 230 is defined by the distance difference between the corresponding edges of the second opening 218 and the third opening 220 away from the material deposition source.

[0071] The material deposited from the first deposition creates a first structure (eg, bottom contact 248 for a Josephson junction) on substrate 208 and within the opening area of ​​tri-layer resist mask 200 (see, e.g., Figure 2B242 in cross-sectional view). In some embodiments, the first deposition of material also results in a deposition layer 252 on the third resist layer 214. The deposition layer 252 can be deposited on the top surface of the third resist layer 214 (e.g., to form a top surface region 252a), or the deposition layer 252 can be deposited on the top surface of the third resist layer 214 and the sidewalls of the third resist layer 214 (e.g., to form a sidewall region 252b).

[0072] In some embodiments, during the first deposition step, e.g., Figure 2B As shown in cross-sectional view 242 in FIG, material from an incident flux from a first deposition flow direction 251 is deposited on the exposed top surface of the second resist layer 212. In some embodiments, the first flow deposition direction 251 is oriented at an angle 250 relative to the opening 220 in the third resist layer 214 such that a portion of the material flux from the first deposition is blocked by the edge of the opening 220. Sidewall regions 252b are deposited on sidewall regions of the opening 220 that are further away from the deposition source of the first flow deposition direction, such as Figure 2B As shown in the cross-sectional view 244 of FIG. Deposition on the sidewall region of the opening 220 is partially blocked along the entire third thickness 215 of the third resist layer 214 .

[0073] In some embodiments, a first layer is deposited on substrate 208 having a first deposition layer thickness (t dep )254 and depositing a second deposition layer with a thickness (t metal ) 256. The second deposited layer thickness 256 may be related to the first deposited layer thickness 254 as follows:

[0074] t metal =t dep (1-cosθ) (1)

[0075] Where θ is an angle 250. Angle 250 may be, for example, between 10 and 80 degrees.

[0076] After the first deposition step, the bottom contact 248 can be oxidized. For example, the substrate 208 can be transferred to air or a separate chamber where surface oxidation of the material comprising the bottom contact 248 occurs. In some embodiments, the substrate can remain in the deposition chamber for in-situ oxidation.

[0077] After the first deposition step and before the second deposition step, the orientation between the substrate and the deposition material source is changed. In some embodiments, the substrate 208 is rotated relative to the material source. Depending in part on the configuration of the deposition system, the source can be rotated relative to the substrate 208, or the substrate 208 and the source can be rotated relative to each other.

[0078] After oxidation, the substrate may then undergo a second deposition step, in which a second material (eg, a superconducting material) is deposited to form a second deposited structure (eg, a top contact 258 for a Josephson junction). Figure 2C A schematic diagram of the three-layer resist mask 200 after a second deposition of material for forming a Josephson junction is shown in plan view 260, cross-sectional view 262 through axis AA, and cross-sectional view 264 through axis BB. A second deposition flow direction 271 includes a component along the y-axis parallel to the surface of substrate 208. The second deposition flow direction 271 is oriented at an angle 270 relative to the z-axis, which is perpendicular to the surface of substrate 208. Angle 270 can be, for example, between 10 and 80 degrees relative to the z-axis. The angle 270 during the second deposition can differ from the angle 250 during the first deposition. For example, in some embodiments, the substrate surface can be oriented at a first angle 250 relative to the first deposition flow direction 251 of the deposited material during the first deposition step (e.g., where the first deposition flow direction 251 includes a component along the x-axis), and oriented at a second angle 270 relative to the second deposition flow direction 271 that is orthogonal to the first angle 250 (e.g., where the second deposition flow direction 271 includes a component along the y-axis) during the second deposition step.

[0079] A second layer is deposited from a second deposition flow direction 271 on the substrate 208 and in the opening area of ​​the three-layer resist mask 200 to form a second deposition structure (eg, a top contact 258 for a Josephson junction), for example, Figure 2C 264. In some embodiments, a second deposition structure can be deposited over the first deposition structure (eg, bottom contact 248), for example, to form a Josephson junction.

[0080] In some embodiments, a portion of the first deposited layer, a portion of the oxidized region above the first deposited layer, and a portion of the second deposited layer above the oxidized region form part of a quantum computing system (e.g., a qubit). In some embodiments, a portion of the first deposited layer, a portion of the oxidized region above the first deposited layer, and a portion of the second deposited layer above the oxidized region form part of a Josephson junction.

[0081] In some embodiments, the second deposited material also results in a deposited layer 272 on the previously deposited layer 252. The deposited layer 272 can be deposited on the top surface (e.g., top surface region 252a) of the previously deposited layer 252, or the deposited layer 272 can be deposited on the top surface of the previously deposited layer 252 and on the sidewall regions 252b, 252c of the previously deposited layer 252.

[0082] In some embodiments, for example, Figure 2C As shown in the cross-sectional view 264 in FIG, the material is deposited on the exposed top surface 272 c of the second resist layer 212 along the same direction as the second flow deposition direction 271 .

[0083] In some embodiments, material is deposited on sidewall regions 272b at an angle 270 relative to second flow deposition direction 271 such that a portion of third resist layer 214 and / or previously deposited layer 252 blocks deposition of at least some of the deposited material within opening 220. For example, Figure 2C Cross-sectional view 262 depicts second deposition flow direction 271 oriented at angle 270 relative to substrate 208 such that deposition on sidewall region 272 b is partially blocked from deposition along the entire third thickness 215 of third resist layer 214 .

[0084] In some embodiments, the second layer is deposited on the substrate 208 and has a first deposition layer thickness (t dep )274 and depositing a second deposition layer with a thickness (t metal ) 276. The second deposited layer thickness 276 may be related to the first deposited layer thickness 274 as follows:

[0085] t metal =t dep (1-cosθ) (1)

[0086] Here, θ is, for example, an angle 270. Angle 270 may be, for example, between 10 degrees and 80 degrees.

[0087] In some embodiments, the first deposition thickness (t dep ) 256 is smaller than the second undercut width 230, material is not deposited (or is negligibly deposited) on the exposed top surface of the second resist layer 212 having the second undercut width 230. In this case, the second deposition of material (e.g., the top contact 258) is not affected by the shadowing effect, for example, the width of the top contact 258 is the desired width 224 defined by the opening 218 of the tri-layer resist mask 200 rather than a width smaller than the width 224 of the opening 218.

[0088] In some embodiments, the first undercut width 228 and the second undercut width 230 are not equal in value. In addition, the first undercut width 228 defined by the first deposition flow direction 251 can have a different value than the first undercut width 228 defined by the second deposition flow direction 271, as described below with reference to Figure 4A discussed in further detail.

[0089] In some embodiments, one or more parameters of the triple-layer resist mask 200 and / or one or more parameters of the two-step deposition process can be adjusted to reduce shadowing effects (e.g., where one or more dimensions of the second deposited structure may differ from a desired dimension due to shadowing from material deposited during the first deposition step). Figures 3A-3D are diagrams of cross-sectional views of a two-step deposition process for various exemplary triple-layer resist masks. Figures 3A-3D The cross-sectional view shown is similar to Figure 2C The three-layer resist mask on the substrate 308 includes a first resist layer 310, a second resist layer 312, and a third resist layer 314 having corresponding openings 316, 318, and 320, similar to the reference numerals 264 and 265. Figures 2A-2C Furthermore, the first resist layer 310 , the second resist layer 312 , and the third resist layer 314 have thicknesses 311 , 313 , and 315 , respectively.

[0090] Although for simplicity, Figures 3A-3D The deposition from the second deposition step is not shown on the top surface of the cross-sectional view shown, but it is conceivable that the amount of material from the second deposition is similar to Figure 2C The second deposition layer 272 is shown deposited on at least a portion of the top surface of each cross-sectional view.

[0091] In general, the various parameters of the three-layer resist mask 200 and the two-step deposition process can be related as follows:

[0092]

[0093] t metal <uc2 (3)

[0094] where t metal is the thickness of the metal deposited on the sidewalls of the resist layer (e.g., thickness 356), θ is the deposition angle relative to the substrate for the first deposition step (e.g., angle 350), t3 is the thickness of the third resist layer (e.g., third thickness 315), w is the width of the second opening of the second resist layer (e.g., width 324), uc1 is the first undercut width (e.g., undercut width 328), and uc2 is the second undercut width (e.g., undercut width 330).

[0095] As discussed above with reference to equation (1), the thickness of the metal deposited on the sidewalls of the top resist layer (e.g., third resist layer 314) can be related to the thickness of the deposit by an angle θ (e.g., angle 350). As the angle increases to approximately 90 degrees relative to the z-axis perpendicular to the substrate surface, the thickness of the metal deposited on the sidewalls, t metal Close to the thickness of metal deposition t dep .

[0096] Figures 3A-3D A first deposition of material and a second deposition of material are shown, with the first deposition 351 and the second deposition 371 indicated in the same illustration, however, it will be understood that the first deposition step precedes the second deposition step, as shown with reference to FIG. Figure 2B and Figure 2C as well as Figure 6 As stated.

[0097] Figure 3A is similar to Figures 2A-2C FIG. 2 is a diagram of a cross-sectional view of a triple-layer resist mask 200, wherein the first undercut width 328 and the second undercut width 330 are non-zero and the first deposition angle 350 can be compared to the reference Figures 2B-2C The relevant values ​​are compared.

[0098] Figure 3B is a diagram illustrating a cross-sectional view of another example two-step deposition process for a three-layer resist mask, wherein the first undercut width 328 exceeds a threshold width such that the first deposition of material covers the sidewalls of the third resist layer 314 and at least a portion of the sidewalls of the second resist layer 312. The threshold width of the first undercut width (uc1) 328 may be defined as:

[0099]

[0100] In the event that sidewall deposition occurs on the second resist layer 312 due to exceeding a threshold width value, a shadowing effect may be observed on the second deposited layer 358 due to the narrowing of the opening in the second resist layer relative to the desired width of the second opening of the second resist layer. For example, at least a portion of the deposited second layer 358 may have a width 380 that is smaller than the desired width defined by the width 324 of the second opening 318 of the second resist layer 312.

[0101] Figure 3C is a diagram of a cross-sectional view of a two-step deposition process for a three-layer resist mask, wherein the amount of first deposited material deposited on the sidewalls of the third resist layer 314 exceeds the second undercut width 330. Where the width of the first deposited material deposited on the sidewalls of the third resist layer 314 exceeds the width of the second undercut width 330, a shadowing effect on the second deposited layer may be observed due to the narrowing of the opening in the second resist layer relative to the desired width of the second opening of the second resist layer 312. For example, at least a portion of the deposited second layer 358 may have a width 380 that is smaller than the desired width defined by the width 324 of the second opening 318 of the second resist layer 312.

[0102] Figure 3D312 , wherein the second undercut width is zero or approximately zero, such that any deposition on the sidewalls of the third resist layer 314 may cause a shadowing effect during the second deposition of the material. For a second undercut width of approximately zero, the width is a non-zero distance that is sufficiently small to have the same shadowing effect during the second deposition of the material as a second undercut width of zero. The shadowing effect can include blocking at least a portion of the second opening from view by a source (not shown) during the second deposition step, such that the opening through which deposition occurs on the substrate 308 is narrowed in one or more directions relative to a desired width defined by the second opening 318 of the second resist layer 312. For example, at least a portion of the deposited second layer 358 may have a width 380 that is smaller than a desired width defined by the width 324 of the second opening 318 of the second resist layer 312.

[0103] In some embodiments, other parameters can create a shadowing effect during the second deposition process. For example, a thickness of the third resist layer that is less than a threshold thickness relative to the deposition angle may result in sidewall deposition on the second resist layer (and the third resist layer) and cause a shadowing effect during the second deposition step. In another example, roughening in the first deposited layer (e.g., deposited aluminum) (which is caused in part by grain growth and / or grain morphology (e.g., grain boundaries) of the deposited material of the first deposited layer) may result in a non-uniform shadowing effect (e.g., non-uniform deposition from the sidewalls of the first deposited layer). The non-uniform deposition caused by the roughening of the first deposited layer may result in a second deposited layer that is non-uniformly shadowed along the length of the deposited structure (e.g., a Josephson junction).

[0104] After the mask evaporation process, the resist can be removed in a stripping step to remove unwanted material and complete the fabrication of the Josephson junction. Depending on the chemical composition of the resist material, stripping can be performed using a variety of different solvents and / or chemical methods.

[0105] In some embodiments, one or more shadowing effects resulting from the above-described layout of the three-layer resist mask (e.g., deposition from the first deposition step obstructing a portion of the opening of the resist mask) can be addressed by carefully selecting the first undercut width. In particular, referring to Figures 4A-4C Discussed in More Detail Selecting a first undercut width of zero or approximately zero can correct for one or more of the sensitivities to deposition parameters (eg, deposition angle, deposition thickness).

[0106] Figures 4A-4C is a diagram showing various views of another exemplary two-step deposition process through a triple-layer resist mask 400 . Figure 4AA schematic diagram of a triple resist mask 400 is shown in a plan view 402, a cross-sectional view 404 through axis AA, and a cross-sectional view 406 through axis BB. The triple resist mask 400 is configured such that a first undercut (uc1) width is equal to or nearly equal to zero.

[0107] The three-layer resist mask 400 includes a first resist layer 410, a second resist layer 412, and a third resist layer 414 having respective layer thicknesses 411, 413, and 415, and is configured similarly to the reference numerals. Figures 2A-2C 4. The three-layer resist mask 400 is described. However, the three-layer resist mask 400 differs in the position of the relative openings 416, 418, and 420 in the resist layers 410, 412, and 414, respectively. Specifically, as shown in the cross-sectional view 404 along the Y direction and as shown in the cross-sectional view 406 along the X direction, the mask opening area 421 is aligned so that the width of one or more of the undercut widths is zero and / or approximately zero. For example, as shown in the cross-sectional view 404, the width 422 of the opening 420 along the Y direction is equal to or approximately equal to the width 426 of the opening 418 along the Y direction (e.g., the first undercut width and the second undercut width are equal to zero). In another example, as shown in the cross-sectional view 406, the width 424 of the opening 420 along the X direction is defined so that the first undercut width is zero or approximately zero and the second undercut width 430 has a non-zero value. That is, the sidewall of the resist layer 414 on the side of the opening 424 is flush with the sidewall of the resist layer 412 on the side of the opening 428 .

[0108] In some embodiments, by exposing the third resist layer to a pattern narrower than the pattern exposed on the first resist layer 410, the third resist layer 414 can have a width of the third opening 420 (e.g., widths 422, 424) that is smaller than the width 417 of the first opening 416 of the first resist layer, and can be further offset (e.g., as shown in cross-sectional view 406, where the opening 424 is not exactly aligned with the first opening 417, but is still within the boundaries of the first opening 417).

[0109] Reference Figure 4B The advantages of a zero or nearly zero first undercut width are discussed. Figure 4B A schematic diagram of the three-layer resist mask 400 after the first deposition of the material for forming the Josephson junction is shown in plan view 440, cross-sectional view 442 through axis AA, and cross-sectional view 444 through axis BB. The relative orientation of the substrate with respect to the deposition material source is the same as above with reference to FIG. Figures 1A-1C and Figures 2A-2C The relative orientations discussed are the same.

[0110] As reference Figures 2A-2CAs discussed, the first undercut width is defined by the difference in distance between respective edges of the second opening 418 and the third opening 420 that are closer to the material deposition source (e.g., edges 419a and 421a, respectively, in cross-sectional view 444), and the second undercut width is defined by the difference in distance between respective edges of the second opening 418 and the third opening 420 that are farther from the material deposition source (e.g., 419b and 421b, respectively, in cross-sectional view 444). Figure 4B In the example of the three-layer resist mask 400 depicted in the cross-sectional view 444 of FIG, the first undercut width is zero or approximately zero, and the second undercut width 430 is a non-zero value.

[0111] The first layer deposition from the first deposition flow direction 451 forms a first deposition structure (e.g., a bottom contact 448 of a Josephson junction) extending along the x-axis in the plane of the substrate 408 and within the opening region of the tri-layer resist mask 400, e.g., as in Figure 4B 440 and in cross-sectional view 442. In some embodiments, the first deposition of material also results in a deposition layer 452 on the third resist layer 414. The deposition layer 452 can be deposited on a top surface of the third resist layer 414 (e.g., to form a top surface region 452a) and / or on sidewalls of the third resist layer 414 (e.g., to form a sidewall region 452b).

[0112] As shown in cross-sectional view 444, reducing the undercut width of the first side of opening 420 (i.e., the edge 421a of opening 420 closest to the material deposition source) for a particular deposition angle θ (e.g., angle 450) reduces the extent of material deposited on the opposing second sidewall of layer 414 within opening 420. That is, as the undercut width decreases, material from flux 451 is increasingly blocked by the upper corner of layer 414. Consequently, less material reaches the sidewall of layer 414 opposite the sidewall of the corner associated with blocking flux 451. As a result, the material deposited on the sidewall terminates away from layer 412. For a particular angle of incidence θ of flux 451, by reducing the undercut width of the first side of opening 420, a maximum distance between the upper surface of layer 412 and the terminated portion of material deposited on the sidewall can be achieved. In some embodiments, first undercut width 228 is approximately zero (e.g., a sufficiently small non-zero width) such that, for a particular angle of incidence θ of flux 451, a maximum distance between the upper surface of layer 412 and the termination portion of the material deposited on the sidewalls can be achieved as if the undercut width were equal to zero.

[0113] After the first layer deposition step, the first deposited layer may be oxidized (e.g., by transferring the substrate 408 to air, to a separate chamber, or leaving it in the deposition chamber for in-situ oxidation, which promotes surface oxidation of the deposited material), as described above with reference to Figures 2A-2C discussed in more detail.

[0114] Figure 4C A schematic diagram of the three-layer resist mask 400 after a second deposition for forming a Josephson material is shown in plan view 460, cross-sectional view 462 through axis AA, and cross-sectional view 464 through axis BB. Again, the substrate surface facing the material deposition source (not shown) can be oriented at an angle 470 relative to the flux direction 471 of the second deposition material, details of which are described in detail in FIG. Figure 4C Discuss in more detail.

[0115] A second layer is deposited from a second deposition flow direction 471 on the substrate 408 and in the opening area of ​​the three-layer resist mask 400 to form a second deposition structure (eg, a top contact 458 for a Josephson junction), for example, Figure 4C In some embodiments, similar to the above reference Figure 2C Discussing deposited layer 272 , the second deposition of material also results in deposited layer 472 over the previously deposited layer 452 from the first layer deposition.

[0116] In some embodiments, the second layer is deposited on the substrate 408 with a first deposition layer thickness (t dep ) 474 of the top contact 458 and deposited on the sidewall region 472b with a thickness (t metal )476 second deposition layer, where t dep and t metal Relationships and references Figure 2C The relationship described in Equation 1 is the same as the flux incident angle 470.

[0117] In some embodiments, the first deposition thickness (t dep ) 456 is smaller than the second undercut width 430, and material is not deposited (or is negligibly deposited) on the exposed top surface of the second resist layer 412 having the second undercut width 430. In this case, the second deposition of material (e.g., top contact 458) is not affected by a shadowing effect, for example, the width of the top contact 458 is the desired width 428 defined by the opening 418 of the tri-layer resist mask 400 rather than a width smaller than the width 428 of the opening 418.

[0118] Figure 5 is a flow chart of an exemplary process 500 for forming a multi-layer resist mask, such as a multi-layer resist mask. Figures 1A-1C 、 Figures 2A-2C and Figures 4A-4CThe two-layer and three-layer resist masks are described. A dielectric substrate (eg, substrate 208) is provided (502). The dielectric substrate may include silicon, sapphire, diamond, or another substrate material having similar dielectric properties.

[0119] A first resist layer (e.g., first resist layer 210 having a thickness of 211) is formed on a dielectric substrate (e.g., substrate 208) (504) comprising a first thickness. The first resist layer can be formed on a surface of the dielectric substrate, e.g., as described above with reference to Figure 2A The first resist layer can be made of an electron beam lithography compatible material (e.g., P(MMA-MAA), PMMA, ZEP520, UV5 / UVIII), a DUV lithography compatible material (e.g., UV6, UV210), a lift-off material (e.g., LOL, LOR, PMGI), or another resist material compatible with both electron beam lithography and DUV lithography (e.g., PMMA, P(MMA-MAA)). The first resist layer can be formed on the dielectric substrate using a deposition technique including spin coating.

[0120] A second resist layer (506) is formed on the first resist layer (e.g., first resist layer 210), the second resist layer comprising a second thickness (e.g., second resist layer 212 having a thickness of 213). The second resist layer and the second opening can be formed on the surface of the first resist layer, e.g., as described above with reference to Figure 2A The second resist layer can be made of an electron beam lithography compatible material (e.g., P(MMA-MAA), PMMA, ZEP520, UV5 / UVIII), a DUV lithography compatible material (e.g., UV6, UV210), a lift-off material (e.g., LOL, LOR, PMGI), or another resist material compatible with both electron beam lithography and DUV lithography (e.g., PMMA, P(MMA-MAA)), and is a material different from the resist material of the first resist layer. The second resist layer can be formed on the first resist layer using a deposition technique including spin coating.

[0121] A third resist layer (508) is formed on the second resist layer (e.g., second resist layer 212), the third resist layer comprising a third thickness (e.g., third resist layer 214 having a thickness of 215). The third resist layer can be formed on the surface of the second resist layer, e.g., as described above with reference to Figure 2AThe third resist layer can be made of an electron beam lithography compatible material (e.g., P(MMA-MAA), PMMA, ZEP520, UV5 / UVIII), a DUV lithography compatible material (e.g., UV6, UV210), a lift-off material (e.g., LOL, LOR, PMGI), or another resist material compatible with both electron beam lithography and DUV lithography (e.g., PMMA, P(MMA-MAA)), and is a material different from the resist material of the second resist layer. The third resist layer can be formed on the second resist layer using a deposition technique including spin coating.

[0122] The first resist layer, the second resist layer and the third resist layer are exposed in a first patterning step (510), for example as described with reference to Figure 2A The first patterning step may include a first exposure dose that is sufficient to define features corresponding to the pattern in the first resist layer, the second resist layer, and the third resist layer. One or more openings in the multilayer resist mask may be defined by the first patterning step. For example, an opening in the second resist layer (e.g., opening 218 having width 224 in second resist layer 212) may be defined. The first resist layer and the third resist layer may also be exposed during the first patterning step and then further exposed during the second patterning step.

[0123] The first resist layer, the second resist layer and the third resist layer are exposed in a second patterning step (512), for example as described with reference to Figure 2A The second patterning step may include a second exposure dose that is sufficient to define features corresponding to the pattern in the first resist layer and the third resist layer, but insufficient to define features corresponding to the pattern in the second resist layer. As a result, one or more openings in the first resist layer and the third resist layer (e.g., opening 216 in first resist layer 210 and opening 220 in third resist layer 214) are defined during the second patterning step.

[0124] The first patterning step and the second patterning step define respective openings in the first resist layer, the second resist layer, and the third resist layer, such that the first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned above the first opening and extending through the thickness of the second resist layer, and the third resist layer includes a third opening aligned above the second opening and extending through the thickness of the third resist layer.

[0125] The first resist layer, the second resist layer, and the third resist layer are developed (514) in one or more development processes. The development process may include one or more developers to remove exposed or unexposed resist material, depending in part on whether a positive resist material or a negative resist material is used. The developers may include MIBK:IPA (e.g., in a ratio of 1:3, 1:2, 1:1), MIBK, and AZ300MIF, depending in part on the different resist materials used in the multilayer resist mask. The development time for AZ300MIF ranges from 40 to 90 seconds. In one example, for openings in the submicron to micron range, the development time using AZ300MIF is 70 seconds.

[0126] Although the multi-layer resist mask described herein includes a two-layer resist mask and a three-layer resist mask, more than three resist layers may be used.

[0127] The multi-layer resist mask can then be used to form at least a portion of a quantum computing system (e.g., a Josephson junction including a bottom contact and a top contact), as described with reference to Figures 1A-1C 、 Figures 2A-2C and Figures 4A-4C described. Figure 6 The present invention is a flow chart of an exemplary process 600 for forming at least a portion of a quantum computing system (e.g., a Josephson junction) using a multilayer resist mask. The multilayer resist mask includes three resist layers, each of which has an opening in the resist layer extending from a top surface of the resist layer through the thickness of the resist layer. Each corresponding opening in the resist layer is aligned above each other, thereby establishing an opening area that extends from the top surface of the top resist layer of the three resist layers through the corresponding thickness of the three resist layers to the main surface of the substrate. A first material layer (602) is deposited from a first deposition flow direction (e.g., flow direction 251) through first, second, and third openings (e.g., openings 216, 218, 220, respectively) and at a first deposition angle (e.g., angle 250) relative to a z-axis perpendicular to the main surface of the substrate (e.g., substrate 208) and including a component along an x-axis relative to the main surface of the substrate.

[0128] The orientation between the substrate and the deposition material source is changed (604). In some embodiments, the orientation of the deposition material source relative to the substrate is changed, or the orientation of the deposition material source and the substrate relative to each other is changed. For example, the substrate is rotated 90 degrees relative to the deposition material source so that the direction of the material flux for the first deposition (e.g., first deposition flow direction 251) and the direction of the material flux for the second deposition (e.g., second deposition flow direction 271) are orthogonal to each other. In another example, the substrate is tilted relative to the direction of the material flux so that the angle between a plane defined parallel to the surface of the substrate and the direction of the material flux for the first deposition (e.g., first deposition flow direction 251) and the angle between a plane defined parallel to the surface of the substrate and the direction of the material flux for the second deposition (e.g., second deposition flow direction 271) are orthogonal to each other.

[0129] In some embodiments, before the second deposition step, as described with reference to Figure 1B As described, the substrate is transferred to air, transferred to a separate chamber, or left in the deposition chamber for in-situ oxidation, wherein surface oxidation of the deposited material is promoted.

[0130] A second material layer (606) is deposited through the first, second, and third openings from a second deposition flow direction (eg, second deposition flow direction 271) and at a second deposition angle (eg, angle 270) relative to a z-axis perpendicular to the substrate.

[0131] In some embodiments, after depositing the second material layer, the multi-layer resist mask and any unwanted deposited material are removed in a stripping step to remove the unwanted material and complete the fabrication of the Josephson junction.

[0132] In some embodiments, some or all of the above-described processes and characterization techniques occur in a controlled environment, which may include a high-purity vacuum chamber, a temperature below the superconducting temperature of the superconducting material, or a combination thereof.

[0133] An example of a superconducting material that can be used to form quantum circuit elements is aluminum. Aluminum can be used in combination with dielectrics to create Josephson junctions, which are common components of quantum circuit elements. Examples of quantum circuit elements that can be formed from aluminum include circuit elements such as superconducting coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, among others.

[0134] Aluminum can also be used to form superconducting classical circuit elements, which can interoperate with superconducting quantum circuit elements and other classical circuit elements based on complementary metal oxide semiconductor (CMOS) circuits. Examples of classical circuit elements that can be formed with aluminum include fast single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQ that do not use bias resistors. Other classical circuit elements can also be formed from aluminum. Classical circuit elements can be configured to collectively execute the instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form.

[0135] The processes described herein may require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. The processes described herein may also require the removal of one or more materials from the device during fabrication. Depending on the material to be removed, the removal process may include, for example, a wet etching technique, a dry etching technique, or a stripping process.

[0136] The embodiments of the quantum subject matter and quantum operations described in this specification can be implemented in appropriate quantum circuits or more generally in quantum computing systems (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more thereof. The term "quantum computing system" can include, but is not limited to, a quantum computer, a quantum information processing system, a quantum information processing device, a quantum cryptography system, or a quantum simulator.

[0137] The terms quantum information and quantum data refer to information or data carried by, held in, or stored in a quantum system, where the smallest non-trivial system is a qubit, e.g., a system defining a unit of quantum information. It will be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the respective context. Such quantum systems may include, for example, multi-level systems having two or more levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many embodiments, the computational basis states are identified as the ground state and the first excited state, but it will be understood that other arrangements are possible in which computational states are identified by higher-level excited states. It will be understood that a quantum memory is a device capable of storing quantum data for a long time with high fidelity and efficiency, such as a light-matter interface, where light is used for transmission and matter is used for storage and preservation of quantum characteristics of quantum data, such as superposition or quantum coherence.

[0138] Quantum information processing devices can be used to perform quantum processing operations. That is, quantum information processing devices can be configured to utilize quantum mechanical phenomena such as superposition and entanglement to perform operations on data in an uncertain manner. Certain quantum information processing devices, such as qubits, can be configured to represent information and operate on information in more than one state simultaneously. Examples of superconducting quantum information processing devices that can be formed using the processes disclosed herein include circuit elements such as coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), among others.

[0139] In contrast, classical circuit elements typically process data in a deterministic manner. Classical circuit elements can be configured to collectively execute the instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form. In some embodiments, classical circuit elements can be used to send data to and / or receive data from quantum circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements that can be formed using the processes disclosed herein include fast single-flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQ that do not use bias resistors. Other classical circuit elements can also be formed using the processes disclosed herein.

[0140] During the operation of a quantum computing system using a superconducting quantum information processing device and / or a superconducting classical circuit element (such as the circuit element described herein), the superconducting circuit element is cooled in a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties. Superconductor (or, superconducting) material can be understood as a material that exhibits superconducting properties at or below the superconducting critical temperature. The example of a superconducting material includes aluminum (superconducting critical temperature is about 1.2 Kelvin), indium (superconducting critical temperature is about 3.4 Kelvin), NbTi (superconducting critical temperature is about 10 Kelvin) and niobium (superconducting critical temperature is about 9.3 Kelvin). Therefore, superconducting structures such as superconducting traces and superconducting ground planes are formed by materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0141] Although this specification includes many specific implementation details, these details should not be interpreted as limiting the scope of the claimed scope, but should be interpreted as descriptions of features that may be peculiar to a particular embodiment. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described as working in certain combinations and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0142] A number of embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the invention. Other embodiments are within the scope of the following claims.

Claims

1. A method comprising: providing a dielectric substrate and a multilayer resist structure on a surface of the dielectric substrate, wherein the multilayer resist structure comprises a first photoresist layer, a second photoresist layer, and a third photoresist layer, the first photoresist layer comprising a first opening extending through a thickness of the first photoresist layer, the second photoresist layer comprising a second opening aligned above the first opening and extending through the thickness of the second photoresist layer, and the third photoresist layer comprising a third opening aligned above the second opening and extending through the thickness of the third photoresist layer, wherein a thickness of each of the first opening, the second opening, and the third opening extends along a first direction perpendicular to the surface of the dielectric substrate, Each of the first opening, the second opening, and the third opening has a corresponding width extending along a second direction orthogonal to the first direction, The width of the second opening is smaller than the width of the first opening and smaller than the width of the third opening, and Providing the multilayer resist structure comprises: forming the second photoresist layer on the first photoresist layer to be in direct contact with the first photoresist layer, forming the third photoresist layer on the second photoresist layer to be in direct contact with the second photoresist layer, defining features corresponding to the second openings in the first, second, and third photoresist layers by a first patterning step including a first exposure dose, and Features corresponding to the first and third openings are defined in the first and third photoresist layers, respectively, by a second patterning step including a second exposure dose that is lower than the first exposure dose.

2. The method according to claim 1, comprising: depositing a first material layer through the first opening, the second opening, and the third opening at a first deposition angle relative to the surface of the dielectric substrate; as well as depositing a second material layer through the first opening, the second opening, and the third opening at a second deposition angle relative to the surface of the dielectric substrate, wherein the orientation between the surface of the dielectric substrate and a material deposition source is changed from a first position for deposition of a first layer to a second position for deposition of a second layer. The method of claim 2 , wherein the first deposition angle and the second deposition angle are different. The method of claim 3 , wherein the first deposition angle is orthogonal to the second deposition angle.

5. The method of claim 2, wherein the first deposition angle is an oblique angle relative to the surface of the dielectric substrate, and Wherein one or more of the first opening, the second opening, and / or the third opening of the multi-layer resist structure blocks at least some of the deposited material from the first deposition.

6. A method according to claim 5, wherein the second deposition angle is such that a portion of the second photoresist layer and / or a previously deposited first material layer near an edge of the first opening, the second opening and / or the third opening blocks at least some of the deposited material from the second deposition within the first opening, the second opening and / or the third opening. 7 . The method of claim 2 , wherein the first position for deposition of the first layer and the second position for deposition of the second layer are orthogonal to each other.

8. The method of claim 2, wherein the first material layer and the second material layer are superconducting materials. 9 . The method according to claim 2 , further comprising, before depositing the second material layer, performing surface oxidation of the first material layer to provide an oxidized region of the first material layer. 10 . The method of claim 9 , wherein a portion of the first material layer, a portion of the oxidized region, and a portion of the second material layer form part of a quantum information processing device. 11 . The method according to claim 2 , further comprising removing the first photoresist layer, the second photoresist layer, and the third photoresist layer. 12 . The method of claim 2 , comprising rotating the substrate after depositing the first material layer and before depositing the second material layer.

13. The method of claim 2, comprising changing a position of the material deposition source relative to the dielectric substrate after depositing the first material layer and before depositing the second material layer.

14. The method of claim 2, wherein the third opening includes a first undercut width defined between a first side of the third opening and a first side of the second photoresist layer, and includes a second undercut width defined between a second side of the third opening and a second side of the second photoresist layer, wherein the first undercut width is greater than the second undercut width. The method of claim 14 , wherein the second undercut width is zero.

16. The method of claim 14, wherein each of the first opening, the second opening, and the third opening has a corresponding additional width extending along a third direction orthogonal to the first direction and the second direction, The additional width of the third opening is the same as the additional width of the second opening.

17. The method of claim 2, wherein the first layer corresponds to a first portion of a Josephson junction, and wherein the second layer corresponds to a second portion of the Josephson junction.

18. A method according to claim 17, wherein the Josephson junction forms part of a qubit.

19. A method comprising: providing a dielectric substrate and a multilayer resist structure on a surface of the dielectric substrate, wherein the multilayer resist structure comprises a first resist layer, a second resist layer, and a third resist layer, the first resist layer comprising a first opening extending through a thickness of the first resist layer, the second resist layer comprising a second opening aligned above the first opening and extending through a thickness of the second resist layer, and the third resist layer comprising a third opening aligned above the second opening and extending through a thickness of the third resist layer, wherein a thickness of each of the first opening, the second opening, and the third opening extends along a first direction perpendicular to the surface of the dielectric substrate, Each of the first opening, the second opening, and the third opening has a corresponding width extending along a second direction orthogonal to the first direction, and The width of the second opening is smaller than the width of the first opening and smaller than the width of the third opening; depositing a first material layer through the first opening, the second opening, and the third opening at a first deposition angle relative to the surface of the dielectric substrate; as well as depositing a second material layer through the first opening, the second opening, and the third opening at a second deposition angle relative to the surface of the dielectric substrate, wherein the relative orientation between the surface of the dielectric substrate and a material deposition source is changed from a first position for deposition of a first layer to a second position for deposition of a second layer, and Wherein in the second position, a component of the relative orientation of the surface of the dielectric substrate with respect to the material deposition source on the surface of the dielectric substrate is rotated 90 degrees from the first position.

20. The method according to claim 19, further comprising, before depositing the second material layer, performing surface oxidation of the first material layer to provide an oxidized region of the first material layer, A portion of the first material layer, a portion of the oxidized region, and a portion of the second material layer form part of a quantum information processing device.

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