A method for achieving timing closure by dividing ultra-large-scale SOC into module groups

Abstract

The present invention discloses a method for realizing timing closure by dividing a super-large-scale SOC into module groups, and the method comprises the following steps: S1, obtaining the timing data of the whole chipset, and dividing the SOC into three module groups; S2, reading lib, lef, netlist and def in each module group, determining the specific module group that needs to be repaired and the prototype module group that does not need to be repaired; reading lib and lef of the specific module group, and reading netlist and def of the prototype module group; S3, creating multiple process corners and obtaining the timing data information of each process corner; reading netlist and def from multiple process corners of the specific module group by reverse marking, determining the part that maintains the attributes and the part that needs to be repaired; setting the part that maintains the attributes and the prototype module group to a state that does not need to be repaired; S4, issuing a timing repair command, and repairing the timing violation of the part that needs to be repaired. The present invention divides the module groups, reduces the processing pressure during timing repair, effectively reduces the cost, and at the same time creates the process corners and reversely reads the data, thereby improving the efficiency and accuracy of timing repair.

Description

Technical Field

[0001] The invention relates to the field of ultra-large-scale SOC timing closure methods, and in particular to a method for realizing timing closure of an ultra-large-scale SOC by dividing it into module groups. Background Art

[0002] SOC timing closure mainly involves the related fields of integrated circuit design and timing analysis. With the continuous improvement of the complexity and integration of chip design, timing convergence has become a crucial link in the design process. The purpose of timing convergence is to ensure that the system circuit can perform specific functions in a predetermined order to meet the timing requirements of the design. This involves precise control of factors such as the processing speed and routing delay of different unit circuits in the system. In SOC design, timing convergence is not only related to the performance and stability of the chip, but also directly affects the final quality and market competitiveness of the product.

[0003] In order to achieve timing closure and perform timing repair on the entire SOC, a series of advanced technologies and methods are needed. Designers need to have a deep understanding of the timing characteristics of the system, including the timing relationship between each module and unit circuit; and then balance and handle timing violations by optimizing circuit structure, adjusting clock frequency, adding buffers, etc.

[0004] With the development of advanced processes, the scale of SOC chips has become larger and larger, and ultra-large-scale SOCs have emerged. At this time, the process corners of timing convergence have become more numerous. However, there are at least the following two problems when performing timing convergence on ultra-large-scale SOCs:

[0005] I) During the timing closure process, the data that needs to be accessed for timing repair becomes larger and larger, and often requires specific high-performance servers to process. Ordinary servers can no longer meet the requirements of timing tools for server storage performance configuration. Servers are an investment cost for chip R&D. Servers with higher configurations usually have higher costs. The introduction of more high-performance servers makes the cost of chips even higher.

[0006] II) Timing repair tools cannot support timing repair of an ultra-large-scale SOC as a whole. During the timing repair process, the data becomes unstable due to excessive size, and the timing repair time is too long, so the repair process is relatively slow. Summary of the invention

[0007] In response to the above-mentioned problems I) and II), the present invention aims to optimize the timing closure process of ultra-large-scale SOCs, thereby reducing costs while ensuring the timing repair effect, while increasing efficiency and reducing the time required for timing repair.

[0008] In view of the above technical problems, a method for achieving timing closure by dividing ultra-large-scale SOC into module groups is proposed; the method is achieved through the following technical solutions:

[0009] A method for achieving timing closure by dividing a super-large-scale SOC into module groups, using a timing repair tool and EDA software to perform timing closure on the super-large-scale SOC, the method comprising the following steps:

[0010] S1, obtaining the timing data of the full chipset in the ultra-large-scale SOC, and dividing the ultra-large-scale SOC into three module groups;

[0011] S2, read each corresponding lib library file, each lef library exchange format file, each netlist netlist and each def design exchange format file in each module group, and determine each specific module group that needs timing repair and each prototype module group that does not need timing repair;

[0012] S3. In the timing repair tool, create multiple process corners corresponding to each specific module group in step S2, and obtain the timing data corresponding to each process corner; use the timing repair tool to read in each corresponding netlist and each def design exchange format file from the multiple process corners corresponding to each specific module group, and determine the part to be maintained and the part to be repaired; set the part to be maintained and each prototype module group in step S2 to a state that does not require repair;

[0013] S4. Use the timing repair tool in step S3 to issue a timing repair command to repair the timing violation of the part that needs to be repaired in step S3; after completing the timing violation repair, use the timing repair tool to send the script data corresponding to the timing violation repair to the EDA software; the EDA software completes physical routing according to the script data and completes a round of timing convergence.

[0014] By dividing the module groups, the large amount of timing data of the ultra-large-scale SOC is grouped, which effectively reduces the processing pressure during timing repair, eliminates the need to use high-performance servers, and effectively reduces costs; at the same time, reverse-label reading of the netlist and def can quickly determine the parts that need timing repair and the parts that do not need to be repaired, which can speed up the timing repair; in addition, timing repair tools and EDA software are used for repair to ensure the accuracy of timing repair.

[0015] Preferably, the ultra-large-scale SOC includes a top only layer, a processor, an artificial intelligence processor, a memory and an interface module; in step S1, the three module groups divided into the ultra-large-scale SOC are module group 1, module group 2 and module group 3; wherein module group 1 includes a top only layer and a processor; module group 2 includes a top only layer and an artificial intelligence processor; module group 3 includes a top only layer, a memory and an interface module. Dividing into three module groups can effectively reduce the pressure of data processing and avoid the situation where the timing repair tool cannot process a large amount of data; and each module group reuses the top only layer, which can realize the connection and interaction between different module groups, and reuse various resources in the top only layer can also reduce costs.

[0016] Preferably, in step S2, when determining each specific module group that needs timing repair, if the number of specific module groups is at least two, at least two specific module groups are processed in parallel. When there are at least two module groups that need to be repaired, performing parallel repair can effectively speed up the processing speed and shorten the time for repair and timing closure.

[0017] Preferably, in step S3, multiple process corners are created based on process parameters, voltage parameters and temperature parameters corresponding to each specific module group. Process parameters, voltage parameters and temperature parameters are important factors affecting the performance of ultra-large-scale SOCs. Setting process corners for these important factors facilitates data control and subsequent repair processes.

[0018] Preferably, in step S4, the method for repairing the timing violation is: analyzing the timing margin on the data path of the part that needs to be repaired, selecting a node with a timing margin on the data path, and changing the routing of the node to perform timing repair. Selecting a node with a timing margin for corresponding repair can quickly determine the location of the repair and ensure the accuracy of the repair.

[0019] Preferably, the method further comprises: setting the number of iteration rounds, and after completing one round of timing convergence in step S4, repeatedly performing steps S1 to S4 according to the number of iteration rounds. Performing multiple rounds of iterations can effectively complete timing convergence and improve the convergence effect.

[0020] Preferably, the method further comprises: after completing the physical routing of step S4, performing timing verification on the script data in the EDA software. Using the EDA software for timing verification can ensure the accuracy of timing repair and timely discover errors when they occur.

[0021] Preferably, when an error is found in the timing verification, the location of the error is confirmed according to the script data, and the timing violation repair of step S4 is re-executed for the location of the error. When a timing error is found, the error location can be repaired specifically to avoid the waste of resources and time caused by the overall re-repair.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The technical solution of the present invention groups a large amount of timing data of a super-large-scale SOC by dividing the module groups, thereby effectively reducing the processing pressure during timing repair, eliminating the need to use high-performance servers, and effectively reducing costs; at the same time, reverse-labeling and reading the netlist and def can quickly determine the parts that need timing repair and the parts that do not need to be repaired, thereby speeding up the timing repair; in addition, multiple rounds of iterations can be performed to efficiently converge the timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The present invention is a flow chart of a method for achieving timing convergence by dividing module groups into ultra-large-scale SOCs. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. Example

[0026] like Figure 1 As shown, it is a flow chart of a method for achieving timing convergence by dividing the ultra-large-scale SOC into module groups. After dividing the entire chipset into three modules, the specific module group that needs to be repaired is quickly determined, and then the process corner and timing repair tools are used to repair it, and timing convergence is successfully achieved.

[0027] A method for achieving timing closure by dividing a super-large-scale SOC into module groups, using a timing repair tool and EDA software to perform timing closure on the super-large-scale SOC, the method specifically comprising the following steps:

[0028] S1. Use the timing repair tool to obtain the timing data of the full chipset in the ultra-large-scale SOC, and divide the ultra-large-scale SOC into three module groups. The server used here is just an ordinary server, and there is no need to use a server with ultra-high performance configuration.

[0029] In this embodiment, the ultra-large-scale SOC includes a top only layer, a processor, an artificial intelligence processor, a memory, and an interface module; in step S1, the three module groups into which the ultra-large-scale SOC is divided are module group 1, module group 2, and module group 3; wherein module group 1 includes a top only layer and a processor; module group 2 includes a top only layer and an artificial intelligence processor; and module group 3 includes a top only layer, a memory, and an interface module. Dividing into three module groups can effectively reduce the pressure of data processing and avoid the situation where the timing repair tool cannot process a large amount of data. The three module groups reuse the top only layer, which ensures the consistency of the design, helps to simplify the overall process and subsequent verification work, and can also realize the connection and interaction between different module groups; and the top only layer contains some shareable resources and functions, such as bus interfaces, clock distribution networks, etc. Reusing these resources and functions can reduce the additional use of other resources, thereby reducing costs and improving efficiency.

[0030] S2, read each corresponding lib library file, each lef library exchange format file, each netlist netlist and each def design exchange format file in each module group, and determine each specific module group that needs timing repair and each prototype module group that does not need timing repair. Read each lib library file and each lef library exchange format file corresponding to each specific module group, and read each netlist netlist and each def design exchange format file corresponding to each prototype module group.

[0031] In this embodiment, in step S2, when each specific module group that needs timing repair is determined, if there are at least two specific module groups, at least two specific module groups are processed in parallel. When there are at least two module groups that need to be repaired, parallel repair can effectively speed up the processing speed and shorten the time for repair and timing closure.

[0032] S3. In the timing repair tool, create multiple corresponding process corners for each specific module group in step S2, and obtain the timing data information corresponding to each process corner; use the timing repair tool to back-label and read each corresponding netlist and each def design exchange format file from the multiple process corners corresponding to each specific module group, and determine the part that maintains the attributes and the part that needs to be repaired; set the part that maintains the attributes and each prototype module group in step S2 to a state that does not require repair.

[0033] It should be noted that each module group in the ultra-large-scale SOX is composed of standard cells and macro cells defined by the process library, which are the most basic components in timing repair. The lib library file contains detailed timing information of each unit, such as delay, power consumption, etc. This information is essential for the timing repair tool, because the timing repair tool needs to understand the delay characteristics of each unit in order to accurately simulate and optimize the timing performance of the circuit during the repair process. The LEF library exchange format file provides information such as the geometry and connection relationship of these units. This information helps the timing repair tool understand the layout and routing of the unit, so as to more accurately analyze the timing problem. The netlist netlist describes the connection relationship between each unit in the circuit design. By reading the netlist netlist, the timing repair tool can identify the module group and each unit in the module group, and then analyze the signal transmission path and timing relationship between them. The def design exchange format file contains the physical layout information of the design, including the specific position, direction and connection relationship of each unit on the ultra-large-scale SOC. By reading the def file, the timing repair tool can accurately locate the position of each unit in the physical layout, so as to more accurately calculate and analyze the timing. Combining this information, the timing repair tool can realize the reverse labeling of the timing information, that is, according to the actual circuit layout and unit characteristics, the timing data is mapped to the corresponding unit and connection relationship. In this way, the timing repair tool can detect and repair timing problems such as delay mismatch and timing violations based on this information, thereby improving the timing performance of the entire circuit.

[0034] In this embodiment, in step S3, the process corner is created based on the process parameters, voltage parameters and temperature parameters corresponding to each specific module group. For different process corners, since the actual unit delay and line delay are different, the timing delay of the timing path under different process corners is different. The method for creating multiple process corners can be the following steps: 1) Determine each key parameter of each specific module group, the key parameters include at least process parameters, voltage parameters and temperature parameters, and formulate the range of each process corner; 2) Model, simulate and verify according to each key parameter and the range of each process corner; 3) Create multiple process corners after successful verification.

[0035] It should be noted that process corners refer to different combinations of process parameters, which are used to describe possible changes and uncertainties in the manufacturing process. These process parameters may include parameters such as the length, width, oxide thickness, and doping concentration of each module or unit. Slight changes in these parameters may affect the performance of the chip. Therefore, process corners are a way to consider process changes during design and verification. The introduction of process corners is to take into account the uncertainties and changes in process manufacturing to ensure that the design works properly under various circumstances. By defining different process corners, the design team can make corresponding optimizations and adjustments.

[0036] S4. Use the timing repair tool in step S3 to issue a timing repair command. The timing repair tool can use the PRIME_TIME tool to repair the timing violations of the part that needs to be repaired in step S3. The timing violations may include setup violations and hold violations, etc. These violations may occur in the interface module, processor, and artificial intelligence processor. The violation values ​​of each violation are combined to form the violation value of the entire chip. After completing the timing violation repair, use the timing repair tool to send the script data corresponding to the timing violation repair to the EDA software. The EDA software performs actual physical routing based on the script data to complete a round of timing convergence.

[0037] In this embodiment, in step S4, the method for repairing the timing violation is: analyzing the timing margin on the data path of the part that needs to be repaired, selecting a node with the timing margin on the data path, changing the routing of the node or inserting a standard cell into the node to repair the timing. Selecting a node with the timing margin for corresponding repair can simply and quickly determine the location that needs to be repaired, and ensure the accuracy of the repair.

[0038] In this embodiment, the method further includes: setting the number of iteration rounds, and after completing one round of timing closure in step S4, repeatedly performing steps S1 to S4 according to the number of iteration rounds. Performing multiple rounds of iterations can effectively complete timing closure and improve the convergence effect.

[0039] It should be noted that repairing timing violations means optimizing the timing path and reducing delays. After a round of timing repair, a round of timing closure is completed. After multiple rounds of effective iterations, the timing path can be better optimized and timing closure can be completed better.

[0040] In this embodiment, the method further includes: after completing the physical routing of step S4, performing timing verification on the script data in the EDA software and writing out the timing repair data. Using the EDA software for timing verification can ensure the accuracy of the timing repair and can timely discover errors when they occur, thereby reminding the designer to handle them.

[0041] In this embodiment, when an error is found during timing verification, the location of the error can be confirmed based on the script data received by the EDA, and then the timing violation repair of step S4 is re-executed for the location of the error, and other locations that have not failed do not need to be corrected or modified. When a timing error is found, the error location can be repaired in a targeted manner to avoid wasting resources and time by re-repairing the entire process.

[0042] Specific application examples

[0043] Two identical ultra-large-scale SOCs are prepared, and the first ultra-large-scale SOC is subjected to module group timing repair, and the second ultra-large-scale SOC is subjected to full chip timing repair.

[0044] For the first ultra-large-scale SOC, the modules that make up the ultra-large-scale SOC are grouped according to their functions and connection relationships, and are divided into three module groups. Module group 1 includes the top only layer and the processor, module group 2 includes the top only layer and the artificial intelligence processor, and module group 3 includes the top only layer, the memory, and the interface module.

[0045] The size of the overall and module-based timing data is shown in Table 1:

[0046] Table 1:

[0047]

[0048] The timing data size of the full chipset of the ultra-large-scale SOC reaches 2.2T, the setup violation level reaches -1205TNS / ns, and the hold violation level reaches -809TNS / ns. The required server storage configuration requires at least 2.8T. For module group 1, module group 2, and module group 3, their timing data sizes are 0.6T, 0.7T, and 0.9T respectively, the setup violation levels are -439TNS / ns, -621TNS / ns, and -384TNS / ns respectively, and the hold violation levels are -321TNS / ns, -399TNS / ns, and -226TNS / ns respectively, and the server storage configuration requirements are all 1.2T. After the module groups are divided, the server storage configuration requirements for each module group are greatly reduced, and timing repair can be performed using a server with an ordinary 1.2T configuration.

[0049] The server reads each lib library file, each lef library exchange format file, each netlist netlist, and each def design exchange format file corresponding to each module group, and determines each specific module group that needs timing repair and each prototype module group that does not need timing repair. It is found that all three module groups need timing repair, and all three module groups are specific module groups. Read each lib library file and each lef library exchange format file corresponding to each specific module group, transfer these files to the timing repair file, determine the units and locations of hold violations or setup violations, and these units are the parts that need to be repaired.

[0050] Then, create multiple process corners corresponding to each specific module.

[0051] The PRIME_TIME timing repair tool obtains the timing data information corresponding to each process corner; using the PRIME_TIME timing repair tool, each corresponding netlist and each def design exchange format file are back-annotated and read from multiple process corners corresponding to each specific module group, and the other parts of each module except the cells that need to be repaired are marked as don't touch as the keep attribute part, and then a timing repair command is issued for the cells that need to be repaired. For the timing violations of the cells that need to be repaired, whether there is a timing margin on the data path is analyzed, and the appropriate point with a timing margin is selected to complete the timing repair by changing the routing or inserting standard cells.

[0052] Next, the timing repair tool writes out the script data corresponding to the timing repair and passes it into the EDA software. The EDA software reads the script data, performs actual standard cell insertion and physical routing, and completes the actual repair.

[0053] After completing the physical routing, the existing timing data is extracted for analysis. The analysis results are shown in the first round of Table 2 below:

[0054] Table 2:

[0055]

[0056] After completing the first round of timing repair, the interface module violation values, processor violation values ​​and artificial intelligence processor violation values ​​were effectively reduced, and the timing repair tool took only 6 hours to output script data.

[0057] Secondly, the second round of timing repair is continued according to the above process, and it is repeated until the end of the fifth round, when all violation values ​​of the AI ​​processor are repaired. In the sixth round of timing repair, the module group 2 corresponding to the AI ​​processor will be used as the property retention part, and only the interface module of module group 3 and the processor of module group 1 will be repaired. Continue until the end of the seventh round of timing repair, at which time the violation values ​​of each module group are almost 0.

[0058] Similarly, the full chip timing repair data for the second ultra-large-scale SOC is shown in Table 3 below:

[0059] Table 3:

[0060]

[0061] As shown in Table 3, full-chip timing repair not only requires a 2.8T high-performance server, but also requires more rounds of timing repair. In addition, it takes 14 hours for the timing repair tool to generate script data for each round, which is much lower than the timing repair of the module group. Even in the same round, taking the 7th round as an example, the timing repair of the module group has almost completed the repair work, while the full-chip timing repair still has a violation value of -44.7ns that cannot be ignored. It can be seen that the timing repair of the module group is more advanced and effective.

[0062] In summary, the present invention divides the large amount of timing data of the ultra-large-scale SOC into groups by dividing the module groups, effectively reducing the processing pressure during timing repair, eliminating the need to use high-performance servers, and effectively reducing costs; at the same time, the reverse reading of netlist and def quickly determines the parts that need timing repair and the parts that do not need to be repaired, which can speed up the timing repair; in addition, multiple rounds of iterations can be performed to efficiently converge the timing

[0063] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for achieving timing closure of a super-large-scale SOC by dividing it into module groups, using a timing repair tool and EDA software to perform timing closure on the super-large-scale SOC, characterized in that: The method comprises the following steps: S1, obtaining the timing data of the full chipset in the ultra-large-scale SOC, and dividing the ultra-large-scale SOC into three module groups; S2, the server reads each corresponding lib library file, each lef library exchange format file, each netlist netlist and each def design exchange format file in each module group, and determines each specific module group that needs timing repair and each prototype module group that does not need timing repair; S3. In the timing repair tool, create multiple process corners corresponding to each specific module group in step S2, and obtain the timing data corresponding to each process corner; use the timing repair tool to read in each corresponding netlist and each def design exchange format file from the multiple process corners corresponding to each specific module group, and determine the part to be maintained and the part to be repaired; set the part to be maintained and each prototype module group in step S2 to a state that does not require repair; S4, using the timing repair tool in step S3 to issue a timing repair command to repair the timing violation of the part that needs to be repaired in step S3; After the timing violation repair is completed, the script data corresponding to the timing violation repair is sent to the EDA software using the timing repair tool; The EDA software completes physical routing based on the script data and completes a round of timing convergence.

2. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: The ultra-large-scale SOC includes a top only layer, a processor, an artificial intelligence processor, a memory, and an interface module; in step S1, the ultra-large-scale SOC is divided into three module groups, namely, module group 1, module group 2, and module group 3; Among them, module group 1 includes a top only layer and a processor; module group 2 includes a top only layer and an artificial intelligence processor; module group 3 includes a top only layer, a memory and an interface module.

3. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: In step S2, when each specific module group that needs timing repair is determined, if the number of the specific module groups is at least two, at least two specific module groups are processed in parallel.

4. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: In step S3, multiple process corners are created based on process parameters, voltage parameters and temperature parameters corresponding to each specific module group.

5. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: In step S4, the method for repairing the timing violation is: analyzing the timing margin on the data path of the part that needs to be repaired, selecting a node with the timing margin on the data path, and changing the routing of the node to perform timing repair.

6. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: The method further includes: setting the number of iteration rounds, and after completing a round of timing convergence in step S4, repeatedly executing steps S1 to S4 according to the number of iteration rounds.

7. The method for achieving timing closure by sub-module grouping of ultra-large-scale SOC according to claim 1, characterized in that: The method further includes: after completing the physical routing of step S4, performing timing verification on the script data in the EDA software.

8. The method for achieving timing closure by using ultra-large-scale SOC module groups according to claim 7, characterized in that: When an error is found during the timing verification, the location of the error is confirmed based on the script data, and the timing violation repair of step S4 is re-executed for the location of the error.

Images