Display panel and its shutdown discharge method

Abstract

The application discloses a display panel and a power-off discharging method thereof. The display panel comprises a signal output circuit, a first discharging circuit and a second discharging circuit. The signal output circuit is used for outputting a discharging voltage during a discharging period. The first discharging circuit is connected with the signal output circuit and an odd-numbered group of gate lines, and is used for transmitting the discharging voltage to the odd-numbered group of gate lines during a first discharging period and transmitting the discharging voltage converted into a negative discharging voltage to the odd-numbered group of gate lines during a second discharging period. The second discharging circuit is connected with the signal output circuit and an even-numbered group of gate lines, and is used for transmitting the discharging voltage converted into a negative discharging voltage to the even-numbered group of gate lines during the first discharging period and transmitting the discharging voltage to the even-numbered group of gate lines during the second discharging period. The number of gate lines of the odd-numbered group of gate lines is the same as that of the even-numbered group of gate lines. The above method can improve the switching-on and switching-off screen flashing and image difference.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panels, in particular to a display panel and a power-off discharging method thereof. BACKGROUND

[0002] Currently, people have higher and higher requirements for display. In order to achieve better display effect, large-size high-refresh-rate electronic screens are developed. Correspondingly, for large size and high refresh rate, when the large-size electronic screen is powered off, there is often residual charge, which causes the subsequent on-off screen to appear flashing. Therefore, discharge is performed when the electronic screen is powered off, so as to empty the in-plane charge and reduce the residual charge.

[0003] When discharge is performed when the electronic screen is powered off, the gate voltage of all pixels in the plane is raised. Due to the charge coupling effect between the gate line and the data line, the voltage on the pixel electrode discharged through the data line is correspondingly raised, which causes a large difference between the data signal pulled up and the common voltage during black insertion. At this time, flashing or picture difference is prone to occur. SUMMARY

[0004] In order to reduce the coupling effect of the gate voltage between the data line and the common electrode line and improve the on-off screen flashing and picture difference, the present application provides a display panel and a power-off discharging method thereof.

[0005] To solve the above problems, the first aspect of the present application provides a display panel applied to a display panel, the display panel comprising a plurality of parallel gate lines and data lines perpendicular to the gate lines. The discharge circuit comprises: a signal output circuit for outputting a discharge voltage during a discharge period; a first discharge circuit connected to the signal output circuit and an odd-numbered gate line, for transmitting the discharge voltage to the odd-numbered gate line in a first discharge period and converting the discharge voltage into a negative discharge voltage and transmitting the negative discharge voltage to the odd-numbered gate line in a second discharge period; and a second discharge circuit connected to the signal output circuit and an even-numbered gate line, for converting the discharge voltage into a negative discharge voltage and transmitting the negative discharge voltage to the even-numbered gate line in the first discharge period, and transmitting the discharge voltage to the even-numbered gate line in the second discharge period; wherein the number of the odd-numbered gate lines is the same as the number of the even-numbered gate lines.

[0006] Preferably, the discharge voltage is a gradually decreasing voltage.

[0007] Preferably, the second discharge period is at least not less than the first discharge period.

[0008] The first discharging circuit comprises a first discharging sub-circuit and a second discharging sub-circuit and a first control circuit for controlling the first discharging sub-circuit and the second discharging sub-circuit to switch; the input ends of the first discharging sub-circuit and the second discharging sub-circuit are connected with the signal output circuit, the output ends are connected with the odd-numbered gate lines, and the control ends are connected with the first control circuit; the first control circuit outputs a first level signal in a first discharging period according to a control signal, so as to control the first discharging sub-circuit to transmit the discharging voltage to the odd-numbered gate lines, and outputs a second level signal in a second period, so as to control the second discharging sub-circuit to transmit the discharging voltage switched to a negative discharging voltage to the odd-numbered gate lines; the second discharging sub-circuit comprises an inverting amplifier for converting the discharging voltage to a negative discharging voltage.

[0009] The first discharging sub-circuit comprises a first transistor, and the second discharging sub-circuit comprises a second transistor, and the first transistor and the second transistor are opposite type transistors.

[0010] The control signal is a gradually decreasing control voltage or a gradually increasing control voltage; the first control circuit comprises a comparator, the comparator comprises a reference voltage, and the first level signal or the second level signal is output according to the size of the control voltage and the reference voltage.

[0011] The second discharging circuit comprises a third discharging sub-circuit and a fourth discharging sub-circuit and a second control circuit for controlling the third discharging sub-circuit and the fourth discharging sub-circuit to switch; the input ends of the third discharging sub-circuit and the fourth discharging sub-circuit are connected with the signal output circuit, the output ends are connected with the even-numbered gate lines, and the control ends are connected with the second control circuit; the second control circuit controls the third discharging sub-circuit to work in a first discharging period according to the control signal, so as to transmit the discharging voltage converted to a negative discharging voltage to the even-numbered gate lines, and controls the fourth discharging sub-circuit to work in a second discharging period, so as to transmit the discharging voltage to the even-numbered gate lines; the third discharging sub-circuit comprises an inverting amplifier for converting the discharging voltage to a negative discharging voltage.

[0012] The first control circuit and the second control circuit are connected with the signal output circuit; when the discharging voltage is a gradually decreasing voltage, the control signal is the discharging voltage.

[0013] The first control circuit and the second control circuit both comprise a reference voltage, and the reference voltage is at least not less than an intermediate value between the discharging voltage and a threshold voltage in a pixel unit.

[0014] The second aspect of the application also provides a power-off discharging method, wherein the power-off discharging method is based on the display panel in any of the above embodiments, and the power-off discharging method comprises: transmitting a discharging voltage to odd group gate lines and transmitting a negative discharging voltage to even group gate lines in a first discharging period; and transmitting the discharging voltage to the even group gate lines and transmitting the negative discharging voltage to the odd group gate lines in a second discharging period, so that the coupling effects of the odd group gate lines and the even group gate lines on the data lines are counteracted in the discharging period.

[0015] The application has the following beneficial effects: in the first discharging period, the first discharging circuit transmits the positive discharging voltage to the odd group gate lines, and the second discharging circuit transmits the negative discharging voltage to the even group gate lines, so that the voltage on the data lines remains stable in the first discharging period due to the coupling effect of the gate voltages on the even group gate lines on the data lines when the odd group gate lines are discharged; in the second discharging period, the second discharging circuit transmits the positive discharging voltage to the even group gate lines, and the first discharging circuit transmits the negative discharging voltage to the odd group gate lines, so that the voltage on the data lines also remains stable in the second discharging period due to the coupling effect of the gate voltages on the odd group gate lines on the data lines when the even group gate lines are discharged, so that the data lines are not affected by the coupling effect of the gate voltages on the gate lines in the entire discharging period, and remain stable, thereby improving the screen flicker and image difference during power-on and power-off. The number of the gate lines of the odd group and the even group is the same. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0017] Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of the display panel of the application;

[0018] Figure 2 FIG. 2 is a signal timing diagram of the first embodiment of the display panel of the application;

[0019] Figure 3 FIG. 3 is a signal timing diagram of the second embodiment of the display panel of the application;

[0020] Figure 4 FIG. 4 is a structural schematic diagram of a specific embodiment of the display panel of the application;

[0021] Figure 5 FIG. 5 is a flow schematic diagram of an embodiment of the power-off discharging method of the application.

[0022] LABEL EXPLANATION

[0023] 11 signal output circuit 11; 12 first discharge circuit; 13 second discharge circuit; Vin discharge voltage; 121 first discharge sub-circuit; 122 second discharge sub-circuit; 131 third discharge sub-circuit; 132 fourth discharge sub-circuit; 123 first control circuit; 133 second control circuit. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0025] The terms used in the embodiments of the present application are merely for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0026] It should be understood that the term "and / or" used herein is merely to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0027] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0028] It should be noted that if the application embodiments involve directionality indication (such as up, down, left, right, front, back, etc.), the directionality indication is only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indication also changes accordingly.

[0029] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive or alternative embodiments. It is expressly understood that the embodiments described herein are combinable with each other.

[0030] The application provides a display panel, wherein the display panel comprises a plurality of parallel gate lines and data lines perpendicular to the gate lines. Please refer to Figure 1 , Figure 1 is a structural schematic diagram of an embodiment of the display panel of the application. The display panel comprises a signal output circuit 11, a first discharge circuit 12, and a second discharge circuit 13.

[0031] The signal output circuit 11 is configured to output a discharge voltage Vin during a discharge period. In an embodiment, the discharge voltage Vin is a high-level voltage VGH. In another embodiment, the discharge voltage Vin is a gradually decreasing voltage, and when the discharge voltage decreases to be less than a threshold voltage of a pixel transistor in the display panel, the pixel transistor is turned off, and the discharge is ended. In another embodiment, the discharge voltage Vin is a low-level voltage VGL, and the pixel transistor in the display panel is a P-type transistor that is turned on at a low level. In this embodiment, the discharge voltage is a gradually increasing voltage, and when the discharge voltage reaches a cutoff voltage of the pixel transistor, the pixel transistor is turned off, and the discharge is ended. The signal output circuit 11 can be a timing driver in the display panel, that is, a gate signal output circuit of the display panel, configured to output the discharge voltage Vin to the gate lines. In another embodiment, the discharge voltage Vin is a constant high-level voltage during the discharge period, and after the discharge is ended, the output of the discharge voltage Vin is stopped. The discharge period comprises a first discharge period and a second discharge period.

[0032] The first discharge circuit 12 is connected to the signal output circuit 11 and the odd-numbered gate lines, and is configured to transmit the discharge voltage Vin to the odd-numbered gate lines during the first discharge period, and switch the discharge voltage Vin to a negative discharge voltage -Vin and transmit the negative discharge voltage -Vin to the odd-numbered gate lines during the second discharge period.

[0033] The second discharging circuit 13 is connected with the signal output circuit 11 and the even-numbered gate line, and is used for converting the discharging voltage Vin into a negative discharging voltage -Vin in the first discharging period and transmitting the discharging voltage Vin to the even-numbered gate line in the second discharging period.

[0034] It should be noted that the odd-numbered gate line includes the odd-numbered row gate line or the odd-numbered gate line, and the even-numbered gate line includes the even-numbered row gate line or the even-numbered gate line. Specifically, the gate lines in the display panel include 2N gate lines (G1, G2,..., G2N-1, G2N), and in a specific embodiment, the odd-numbered gate line includes (G1, G3, G5,..., G2N-1), and the even-numbered gate line includes (G2, G4,..., G2N). In another specific embodiment, a plurality of adjacent gate lines (at least 2 or more) are grouped, and specifically, three adjacent gate lines are grouped, so that the odd-numbered gate line includes the first group of gate lines (G1, G2, G3), the third group of gate lines (G7, G8, G9), the fifth group of gate lines (G13, G14, G15), and so on. The even-numbered gate line includes the second group of gate lines (G4, G5, G6), the fourth group of gate lines (G10, G11, G12), the sixth group of gate lines (G16, G17, G18), and so on. In a preferred embodiment, the gate lines in the display panel are divided into two groups, the first group of gate lines (G1-GN) is the odd-numbered gate line, and the second group of gate lines (GN+1-G2N) is the even-numbered gate line. In this embodiment, the odd-numbered gate line can include a plurality of groups, and each group of odd-numbered gate lines can include a plurality of gate lines; the even-numbered gate line can also include a plurality of groups, and each group of even-numbered gate lines includes a plurality of gate lines; wherein the number of all gate lines in the odd-numbered gate line and the number of all gate lines in the even-numbered gate line should be the same. Specifically, the number of gate lines in each group of odd-numbered gate lines is the same as the number of gate lines in each group of even-numbered gate lines, and the number of groups (grouping number) of the odd-numbered gate line and the even-numbered gate line is also the same.

[0035] In a preferred embodiment, the discharging voltage Vin is a gradually decreasing voltage, and the voltage of the discharging voltage Vin in the first discharging period is greater than the voltage in the second period. Specifically, please refer to Figure 2 , Figure 2 The signal timing diagram of the first embodiment of the display panel of the present application is shown in FIG. 1. As shown in FIG. 1, the signal timing diagram of the first embodiment of the display panel of the present application includes a signal output circuit 11, a first discharging circuit 12, a second discharging circuit 13, a first group of gate lines (G1-GN) and a second group of gate lines (GN+1-G2N). Figure 2As shown, the discharge voltage Vin is a gradually decreasing voltage. In the first discharge period, the voltage transmitted to the odd group gate lines is the positive discharge voltage Vin, so as to discharge the corresponding pixel units on the odd group gate lines; meanwhile, the voltage transmitted to the even group gate lines by the second discharge circuit 13 is the negative discharge voltage -Vin. At this time, the data lines are coupled upward by the odd group gate lines and coupled downward by the even group gate lines in the first discharge period, so as to cancel each other, thereby keeping the voltage on the data lines stable, and the voltage of the common electrode line is also kept stable. In the second discharge period, the voltage transmitted to the even group gate lines is the positive discharge voltage Vin, so as to discharge the corresponding pixel units on the even group gate lines; meanwhile, the voltage transmitted to the odd group gate lines by the first discharge circuit 12 is the negative discharge voltage -Vin. At this time, the voltage on the data lines and the common electrode line is also kept stable under the coupling effect of the odd group gate lines and the even group gate lines. Thus, the data lines are kept stable in the entire discharge period, thereby improving the on / off screen flicker and the image difference phenomenon. More specifically, the discharge voltage in the first discharge period is a first discharge voltage, the discharge voltage in the second discharge period is a second discharge voltage, the first discharge voltage is transmitted to the odd group gate lines and the negative first discharge voltage is transmitted to the even group gate lines in the first discharge period; the negative second discharge voltage is transmitted to the odd group gate lines and the positive second discharge voltage is transmitted to the even group gate lines in the second discharge period, wherein the first discharge voltage and the second discharge voltage can be the same as the discharge voltage or can be in a certain proportion, which is not limited herein. In this embodiment, the first discharge voltage and the second discharge voltage are on the same slope line.

[0036] In another embodiment, the discharge voltage Vin is a constant high-level voltage, and the voltages on the odd group gate lines and the even group gate lines will be further described with reference to Figure 3 , Figure 3 the signal timing diagram of the second embodiment of the display panel of the present application. As shown in Figure 3 , the discharge voltage Vin is transmitted to the odd group gate lines in the first discharge period, and the negative discharge voltage -Vin is transmitted to the even group gate lines, the discharge voltage Vin is transmitted to the even group gate lines in the second discharge period, and the negative discharge voltage -Vin is transmitted to the odd group gate lines. In this embodiment, the time width of the first discharge period and the second discharge period can be the same.

[0037] In the first embodiment, when the discharge voltage Vin is a gradually decreasing voltage, preferably, the second discharge period is longer than the first discharge period to ensure that the discharge voltage during the second discharge period has not decreased too much and is at least greater than the threshold voltage of the pixel transistor, so that the pixel transistor can be turned on for a period of time to discharge the pixel unit corresponding to the even array of gate lines. Preferably, for example, if the threshold voltage of the pixel transistor is 10V and the initial voltage of the discharge voltage Vin is 30V, then the discharge is switched to the even array of gate lines at least before the discharge voltage Vin drops to 20V (e.g., 22V). This is because the closer the discharge voltage Vin is to the threshold voltage, the slower the discharge speed.

[0038] This application also provides specific structures for the first and second discharge circuits; please refer to them for further details. Figure 4 , Figure 4 This is a schematic diagram of the structure of a specific embodiment of the display panel of this application. Figure 4 As shown, the first discharge circuit 12 includes a first discharge circuit 121, a second discharge circuit 122, and a first control circuit 123 for controlling the switching between the first discharge circuit 121 and the second discharge circuit 122. Specifically, both the first discharge circuit 121 and the second discharge circuit 122 include an input terminal, an output terminal, and a control terminal. The input terminals are both connected to the signal output circuit 11, the output terminals are both connected to the odd-numbered gate lines, and the control terminals are both connected to the first control circuit 123.

[0039] The first control circuit 123 outputs a first level signal according to the control signal XON during the first discharge period to control the first discharge circuit 121 to transmit the discharge voltage Vin to the odd array gate lines, and outputs a second level signal during the second period to control the second discharge circuit 122 to switch the discharge voltage Vin to a negative discharge voltage -Vin and transmit it to the odd array gate lines.

[0040] In a preferred embodiment, the second discharge circuit 122 includes a reverse discharger, which comprises a first resistor R1 and a second resistor R2. According to Vin / R1 = -Vout / R2, the ratio of the output voltage to the input voltage, Vout / Vin = -R2 / R1. When R2 = R1, Vout = -Vin. Thus, the discharge voltage Vin is converted to a negative discharge voltage -Vin by the reverse amplifier in the second discharge circuit 122. In other embodiments, voltage switching can also be performed using other circuits, which are not limited here.

[0041] In the embodiment, the first discharge sub-circuit 121 comprises a first transistor T, and the second discharge sub-circuit 122 comprises a second transistor Q, the gates of the first transistor T and the second transistor Q are connected to the first control circuit 123, and the first transistor T and the second transistor Q are opposite type transistors. The first level signal and the second level signal are one high level signal and the other low level signal. Specifically, the first transistor T is an N-type transistor which is high level on, the first level signal is a high level signal, and the second level signal is a low level signal. The first transistor T is on under the first level signal and off under the second level signal, and the second transistor Q is off under the first level signal and on under the second level signal, which is not limited herein.

[0042] In a preferred embodiment, the control signal XON is a gradually decreasing control voltage or a gradually increasing control voltage. The first control circuit 123 is a comparator comprising a reference voltage Vref, and the first level signal or the second level signal is output according to the size of the control signal XON and the reference voltage Vref. Specifically, the control signal XON is a gradually decreasing control voltage, when the control signal XON is greater than the reference voltage Vref, the first level signal is output to control the first discharge sub-circuit 121 to work, and when the control signal XON is less than or equal to the reference voltage Vref, the second level signal is output to control the second discharge sub-circuit 122 to work. In other embodiments, the first control circuit 123 can also be other automatic switching devices, which are not limited herein.

[0043] In an embodiment, the control signal XON can be a separate shutdown signal. In a preferred embodiment, the first control circuit 123 is connected to the signal output circuit 11, and the control signal XON is the same as the gradually decreasing discharge voltage Vin, that is, the control signal XON is the discharge voltage Vin, so that the discharge circuit of the display panel can be controlled by one signal. In the embodiment, more preferably, the reference voltage is at least not less than the intermediate value between the discharge voltage and the threshold voltage of the pixel transistor, so as to ensure the discharge in the second discharge period and avoid that the discharge voltage Vin is too low in the second discharge period, resulting in that the pixel units corresponding to the odd number of gate lines are not completely discharged.

[0044] Further, the second discharging circuit 13 comprises a third discharging sub-circuit 131, a fourth discharging sub-circuit 132 and a second control circuit 133 for controlling the third discharging sub-circuit 131 and the fourth discharging sub-circuit 132. Specifically, the input terminals of the third discharging sub-circuit 131 and the fourth discharging sub-circuit 132 are connected to the signal output circuit 11, the output terminals are connected to the even group gate line, and the control terminals are connected to the second control circuit 133. The second control circuit 133 controls the third discharging sub-circuit 131 to convert the discharging voltage into a negative discharging voltage and transmit the negative discharging voltage to the even group gate line in the first discharging period according to the control signal XON, and controls the fourth discharging sub-circuit 132 to transmit the discharging voltage to the even group gate line in the second discharging period. The third discharging sub-circuit 131 comprises an inverting amplifier for converting the discharging voltage Vin into a negative discharging voltage.

[0045] Preferably, the third discharging sub-circuit 131 has the same circuit structure as the second discharging sub-circuit 122, the fourth discharging sub-circuit 132 has the same circuit structure as the first discharging sub-circuit 121, and the first control circuit 123 and the second control circuit 133 have the same circuit structure. In other embodiments, the first control circuit 123 and the second control circuit 133 can be different, which is not limited herein. In the embodiment, the first control circuit 123 and the second control circuit 133 are preferably one control circuit. In another embodiment, the third discharging sub-circuit 131 can be the same as the first discharging sub-circuit 121, and the fourth discharging sub-circuit 132 can be the same as the second discharging sub-circuit 122. In this case, the first control circuit 123 and the second control circuit 133 have opposite judgment conditions, so that the first control circuit 123 and the second control circuit 133 output opposite level voltages in the first discharging period and the second discharging period. The working process is not described herein.

[0046] Preferably, the first control circuit 123 and the second control circuit 133 are connected to the signal output circuit 11. The signal output circuit 11 can be a driving chip, which can output multiple driving signals at the same time. More preferably, the control signal of the first control circuit 123 and the control signal of the second control circuit 133 are the same, and can be the same as the discharging voltage Vin. In other embodiments, the control signal of the first control circuit 123 and the control signal of the second control circuit 133 can be different, and the reference voltage of the first control circuit 123 and the reference voltage of the second control circuit 133 can be different, which is not limited herein, as long as the voltage switching is performed at the same time.

[0047] The application also provides a power-off discharging method, which is described in detail in the following Figure 5 , Figure 5 The flowchart of an embodiment of the power-off discharging method is shown in FIG. 1. As shown in FIG. 1, the method comprises the following steps. Figure 5

[0048] ​Step S51: transmitting a discharging voltage to the odd group of gate lines and transmitting a negative discharging voltage to the even group of gate lines in a first discharging period.

[0049] Step S52: transmitting a discharging voltage to the even group of gate lines and transmitting a negative discharging voltage to the odd group of gate lines in a second discharging period.

[0050] Thus, the coupling effects of the odd group of gate lines and the even group of gate lines to the data lines in the whole discharging period are counteracted. The discharging period includes the first discharging period and the second discharging period.

[0051] Specifically, when the pixel transistor in the pixel unit is a high-level conductive transistor, the pixel unit corresponding to the odd group of gate lines is discharged in the first discharging period, and the pixel unit corresponding to the even group of gate lines is discharged in the second discharging period. When the pixel transistor in the pixel unit is a low-level conductive transistor, the pixel unit corresponding to the even group of gate lines is discharged in the first discharging period, and the pixel unit corresponding to the odd group of gate lines is discharged in the second discharging period, which is not limited herein. Preferably, the pixel unit corresponding to the odd group of gate lines is discharged in the first discharging period, and the pixel unit corresponding to the even group of gate lines is discharged in the second discharging period.

[0052] Preferably, the odd group of gate lines includes all the gate lines of odd rows, and the even group of gate lines includes all the gate lines of even rows.

[0053] In a preferred embodiment, before step S51, the gate lines in the display panel are divided into the odd group and the even group according to the number of clock signals or the number of gate lines. The odd group of gate lines is the gate line of the odd group, and the even group of gate lines is the gate line of the even group. The clock signal (CLK) is a signal transmitted to the plurality of gate lines in the display panel. For example, when the clock signal is 2, the first row and the third row (2n+1) gate lines share one clock signal, and when the clock signal is 6, the first row and the seventh row (6n+1) gate lines share one clock signal. Therefore, the gate lines can be divided into the odd group and the even group according to the number of clock signals, for example, when the clock signal is 6, CLK1-3 are the odd group, CLK4-6 are the even group, and the gate lines 1-3 in the display panel are the odd group, the gate lines 4-6 are the even group, the gate lines 7-9 are the odd group, and so on. This is not limited herein. It should be noted that in the shutdown discharging period, the high-level signals of all clock signals should be the same to achieve the shutdown of the whole panel.

[0054] It should be noted that the number of the odd group of gate lines and the even group of gate lines (including the number of gate lines and the number of groups) is the same. Preferably, the odd group of gate lines and the even group of gate lines are arranged in the display panel in an interlaced manner.

[0055] The first discharge circuit and the second discharge circuit in the display panel can be one or can include multiple. The multiple first discharge circuits are respectively connected with the odd gate lines of each group, and the multiple second discharge circuits are respectively connected with the even gate lines of each group, which are not limited herein. The first control circuit in the first discharge circuit and the second control circuit in the second discharge circuit can be shared, that is, one, or can not be shared, that is, two, which are not limited herein.

[0056] The application has the following beneficial effects: the first discharge circuit transmits a positive discharge voltage to the odd gate lines in the first discharge period, and the second discharge circuit transmits a negative discharge voltage to the even gate lines, so that the voltage on the data line remains stable in the first discharge period due to the coupling effect of the gate voltage on the even gate lines when the odd gate lines are discharged; the second discharge circuit transmits a positive discharge voltage to the even gate lines in the second discharge period, and the first discharge circuit transmits a negative discharge voltage to the odd gate lines, so that the voltage on the data line also remains stable in the second discharge period due to the coupling effect of the gate voltage on the odd gate lines when the even gate lines are discharged, so that the data line is not affected by the coupling effect of the gate voltage on the gate line in the whole discharge period, and is maintained stable, thereby improving the switching screen and image difference. The number of the odd gate lines and the even gate lines is the same.

[0057] The above is only an embodiment of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.

Claims

1. A display panel comprising a plurality of parallel gate lines and data lines perpendicular to the gate lines, characterized in that, The display panel further comprises: a signal output circuit, configured to output a discharging voltage during a discharging period; a first discharging circuit connected to the signal output circuit and an odd-numbered gate line, configured to transmit the discharging voltage to the odd-numbered gate line during a first discharging period and transmit the discharging voltage converted into a negative discharging voltage to the odd-numbered gate line during a second discharging period; a second discharging circuit connected to the signal output circuit and an even-numbered gate line, configured to transmit the discharging voltage converted into a negative discharging voltage to the even-numbered gate line during the first discharging period and transmit the discharging voltage to the even-numbered gate line during the second discharging period; wherein the odd-numbered gate line and the even-numbered gate line have the same number of gate lines.

2. The display panel of claim 1, wherein, The discharging voltage is a gradually decreasing voltage.

3. The display panel of claim 2, wherein, The second discharging period is at least not less than the first discharging period.

4. The display panel of claim 1, wherein, The first discharging circuit comprises a first discharging sub-circuit and a second discharging sub-circuit and a first control circuit for controlling switching of the first discharging sub-circuit and the second discharging sub-circuit; the input ends of the first discharging sub-circuit and the second discharging sub-circuit are connected to the signal output circuit, the output ends thereof are connected to the odd-numbered gate line, and the control ends thereof are connected to the first control circuit; The first control circuit outputs a first level signal during the first discharging period according to a control signal to control the first discharging sub-circuit to transmit the discharging voltage to the odd-numbered gate line, and outputs a second level signal during the second period to control the second discharging sub-circuit to transmit the discharging voltage converted into a negative discharging voltage to the odd-numbered gate line; wherein the second discharging sub-circuit comprises an inverting amplifier for converting the discharging voltage into a negative discharging voltage.

5. The display panel of claim 4, wherein, The first discharging sub-circuit comprises a first transistor, and the second discharging sub-circuit comprises a second transistor, and the first transistor and the second transistor are opposite type transistors.

6. The display panel of claim 4, wherein, The control signal is a gradually decreasing control voltage or a gradually increasing control voltage; the first control circuit comprises a comparator, the comparator comprises a reference voltage, and the first level signal or the second level signal is output according to the magnitude of the control voltage and the reference voltage.

7. The display panel of claim 4, wherein, The second discharging circuit comprises a third discharging sub-circuit and a fourth discharging sub-circuit and a second control circuit for controlling switching of the third discharging sub-circuit and the fourth discharging sub-circuit; the input ends of the third discharging sub-circuit and the fourth discharging sub-circuit are connected to the signal output circuit, the output ends thereof are connected to the even-numbered gate line, and the control ends thereof are connected to the second control circuit; wherein the second control circuit controls the third discharging sub-circuit to work to transmit the discharging voltage converted into a negative discharging voltage to the even-numbered gate line during the first discharging period and controls the fourth discharging sub-circuit to work to transmit the discharging voltage to the even-numbered gate line during the second discharging period according to the control signal; wherein the third discharging sub-circuit comprises an inverting amplifier for converting the discharging voltage into a negative discharging voltage.

8. The display panel of claim 7, wherein, The first control circuit and the second control circuit are connected with the signal output circuit; when the discharge voltage is gradually decreasing voltage, the control signal is the discharge voltage.

9. The display panel of claim 8, wherein, The first control circuit and the second control circuit each include a reference voltage, which is at least not less than the intermediate value between the discharge voltage and the threshold voltage in the pixel unit.

10. A power-off discharge method for a display panel, characterized in that, The display panel includes the display panel of any one of the above claims 1-9, and the display panel shutdown discharge method includes: In the first discharge period, the discharge voltage is transmitted to the odd group gate lines, and the negative discharge voltage is transmitted to the even group gate lines; In the second discharge period, the discharge voltage is transmitted to the even group gate lines, and the negative discharge voltage is transmitted to the odd group gate lines, so that the coupling effects of the odd group gate lines and the even group gate lines on the data lines are offset to each other in the discharge period.

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