Multi-stage impedance optimization method, memory module and device

Abstract

This invention discloses a multi-stage impedance optimization method, memory module, and device, belonging to the field of impedance optimization technology. The method includes the following steps: when the gold finger impedance value is lower than the target value, the signal line width is narrowed at the closest position to bring it back to the target value, and impedance fluctuations are reduced through multi-stage impedance optimization; when the gold finger impedance value is higher than the target value, the signal line width is widened at the closest position to bring it back to the target value, and impedance fluctuations are reduced through multi-stage impedance optimization. This invention reduces the impact of impedance fluctuations and improves signal integrity.

Description

Technical Field

[0001] The present invention relates to the technical field of impedance optimization, and more specifically, to a multi-stage impedance optimization method, memory module, and device. Background Art

[0002] Memory modules are operating at increasingly higher speeds, with DDR5 modules reaching speeds of up to 6400MHz. This rapid signal rise speed creates impedance fluctuations when signals pass through discontinuities (e.g., from the gold finger to the signal line), causing signal reflections and compromising signal integrity. This is a technical issue that researchers in this field urgently need to address. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a multi-stage impedance optimization method, memory module and device, which reduce the impact of impedance fluctuations and improve signal integrity.

[0004] The object of the present invention is achieved through the following solutions:

[0005] A multi-stage impedance optimization method comprises the following steps:

[0006] Where impedance is discontinuous, impedance fluctuations can be reduced by adjusting the line width.

[0007] Furthermore, the location where the impedance is discontinuous includes any location where the impedance is discontinuous.

[0008] Furthermore, the locations of the impedance discontinuity include locations of the gold fingers and the signal lines.

[0009] Furthermore, the line width adjustment is achieved through single-stage optimization adjustment.

[0010] Furthermore, the line width adjustment is achieved through multi-stage optimization adjustment.

[0011] Furthermore, the method of reducing impedance fluctuation by adjusting line width includes the following sub-steps:

[0012] When the gold finger impedance value is lower than the target value, the signal line width is narrowed at the closest position to bring it back to the target value, and impedance fluctuations are reduced through multi-stage impedance optimization;

[0013] When the gold finger impedance value is higher than the target value, the signal line width is widened at the closest position to bring it back to the target value, and impedance fluctuations are reduced through multi-stage impedance optimization.

[0014] A memory module involves the positions of gold fingers and signal lines, and utilizes the multi-stage impedance optimization method to reduce impedance fluctuations at the positions of gold fingers and signal lines, thereby improving signal integrity.

[0015] Furthermore, the memory module includes a DDR5 memory module.

[0016] An electronic device includes the memory module described above.

[0017] The beneficial effects of the present invention include:

[0018] The present invention reduces the influence of impedance fluctuation and improves signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 The following is a schematic diagram of the impedance fluctuation problem. In the figure, the horizontal axis is time (s) and the vertical axis is impedance value (Ω);

[0021] Figure 2 Schematic diagram of the present invention, in which the horizontal axis is time (s), the vertical axis is impedance value (Ω), t1 is the equivalent time of L1 segment (s), t1' is the equivalent time of C1 segment (s), t2 is time (s), t2' is the equivalent time of L2 segment (s), t2' is the equivalent time of C2 segment (s), L1 is the inductance value (H), C1 is the capacitance value (F), L2 is the inductance value (H), and C2 is the capacitance value (F);

[0022] Figure 3 It is a schematic diagram of the present invention; in the figure, Z c1 is the equivalent impedance value (Ω), Z L1 is the equivalent impedance value (Ω), Z c2 is the equivalent impedance value (Ω), Z L2 is the equivalent impedance value (Ω), Z0 is the characteristic impedance value (Ω);

[0023] Figure 4 Schematic diagram for comparing the effects of the invention; in the figure, the horizontal axis is time (s) and the vertical axis is impedance value (Ω);

[0024] illustrate: Figures 1 to 3 For the purpose of retaining the color drawings, if they are black and white drawings, the effect is not as good as that with color, which is more conducive to understanding the scheme of the present invention. Therefore, retaining the color as a mark is conducive to understanding by people in this field. DETAILED DESCRIPTION

[0025] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0026] Terminology

[0027] Gold finger: A common term in this field, referring to the metal contact point of the PCB board.

[0028] The impedance fluctuation problem between the gold finger position and the signal line is as follows Figure 1 As shown, at position 1 (red), the impedance drops below the target value of 40Ω. This is because the memory chip's gold fingers are much wider than the signal lines. At position 2 (red), the impedance rises to approximately the target value of 40Ω for the signal line, then exhibits some impedance fluctuations (red positions 3 and 4).

[0029] In order to solve the above-mentioned problem of impedance fluctuation, in the technical concept of the present invention, as Figure 2 and Figure 3 As shown, including the following:

[0030] The gold finger impedance value is lower than the target value. At the closest position, the signal line width is narrowed to quickly return to the target value, and the impedance fluctuation is reduced through multi-stage impedance optimization technology.

[0031] On the contrary, if the impedance value is higher than the target value, the signal line width is widened at the closest position to quickly return to the target value, and the impedance fluctuation is reduced through multi-stage impedance optimization technology.

[0032] For example, when the gold finger impedance value is lower than the target value, the multi-stage impedance optimization method of the present invention is used to reduce the impedance fluctuation and make the impedance approach the target impedance Zo, that is:

[0033] [L1(t1)+C1(t1')]+[L2(t2)+C2(t2')]+…+[L n (t n )+C n (t n ')]=>Zo

[0034] like Figure 4 As shown, after optimization of the present invention ( Figure 4 The impedance value is close to the target value.

[0035] The parts not involved in the present invention are the same as the existing technology or can be implemented by using the existing technology.

[0036] The above technical solution is only one embodiment of the present invention. For those skilled in the art, it is easy to make various types of improvements or modifications based on the application methods and principles disclosed in the present invention, and it is not limited to the method described in the above specific embodiment of the present invention. Therefore, the method described above is only preferred and does not have a restrictive meaning.

[0037] In addition to the above examples, those skilled in the art may obtain other embodiments based on the above disclosure or by utilizing knowledge or technology in related fields to make modifications. The features of each embodiment may be interchangeable or replaced. The modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A multi-stage impedance optimization method for reducing impedance fluctuations at the locations of gold fingers and signal lines, characterized in that: The method comprises the following steps: reducing impedance fluctuation by adjusting line width at locations where impedance is discontinuous; The method of reducing impedance fluctuation by adjusting line width includes the following sub-steps: when the gold finger impedance value is lower than the target value, narrowing the signal line width at the closest position to bring it back to the target value, and reducing impedance fluctuation by multi-stage impedance optimization; when the gold finger impedance value is higher than the target value, widening the signal line width at the closest position to bring it back to the target value, and reducing impedance fluctuation by multi-stage impedance optimization; The multi-segment impedance optimization method for reducing impedance fluctuation specifically includes: segmenting the impedance fluctuation graph into four segments, namely, segment L1, segment C1, segment L2, and segment C2; the equivalent times (s) corresponding to the four segments are t1, t1', t2, and t2', respectively, wherein the L1 and L2 segments correspond to fluctuation windows where the impedance is lower than the target value; and the C1 and C2 segments correspond to fluctuation windows where the impedance is higher than the target value; Z L1 , Z L2 , Z c1 , Z c2 are the equivalent impedances (Ω) of L1, C1, L2, and C2 segments respectively; The inductance corresponding to the L1 and L2 segments is L eq The capacitance corresponding to the C1 and C2 segments is C eq Wherein, n is 1 or 2.

2. The multi-stage impedance optimization method according to claim 1, characterized in that: The location of impedance discontinuity includes any location where impedance discontinuity exists.

3. The multi-stage impedance optimization method according to claim 1, characterized in that: The locations of the impedance discontinuity include locations of the gold fingers and the signal lines.

4. A memory module, involving the positions of gold fingers and signal lines, characterized in that: The multi-stage impedance optimization method described in claim 3 is used to reduce the impedance fluctuation at the position of the gold finger and the signal line, thereby improving the signal integrity.

5. The memory module according to claim 4, wherein: The memory module includes a DDR5 memory module.

6. An electronic device, characterized in that: Comprising the memory module as claimed in claim 4.

7. An electronic device, characterized in that: Comprising the memory module as claimed in claim 5.

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