Double-Sided Epitaxial Silicon Carbide Metal-Oxide Field Effect Transistor Power Device

Abstract

The present invention discloses a double-sided epitaxial layer silicon carbide metal-oxide field effect transistor power device, comprising: a first N-type silicon carbide metal-oxide field effect transistor is located on the first surface of an N-type silicon carbide substrate; the first N-type silicon carbide metal-oxide field effect transistor includes a first gate structure, a first source structure and a first drain structure; a second N-type silicon carbide metal-oxide field effect transistor is located on the second surface of the N-type silicon carbide substrate; the second N-type silicon carbide metal-oxide field effect transistor includes a second gate structure, a second source structure and a second drain structure; the first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are connected in parallel and are arranged mirror-symmetrically with respect to the N-type silicon carbide substrate. The technical solution provided by the embodiment of the present invention reduces the on-resistance of the power device, effectively reduces the area of ​​the power device and reduces the cost of the power device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a double-sided epitaxial layer silicon carbide metal-oxide field effect transistor power device. Background Art

[0002] Although silicon is the most widely used semiconductor in electronics, recent studies have shown that it has certain limitations, especially in high-power applications. Bandgap is a relevant factor for semiconductor-based circuits because a high bandgap offers advantages in operation at high temperatures, voltages, and frequencies. The bandgap of silicon is 1.12eV, while the bandgap value of silicon carbide is 3.2eV, which is about 3 times higher than that of silicon, so silicon carbide power devices have higher performance and efficiency, higher switching frequencies, and a smaller overall footprint. SiC MOSFETs have excellent characteristics and a unipolar conduction mechanism, which leads to their reduced size and improved switching performance. In addition, when having the same current and voltage ratings, the size of SiC MOSFETs can be much smaller than their Si counterparts, and due to the smaller size, the overall parasitic capacitance is smaller, which enables SiC metal-oxide-semiconductor field-effect transistors to achieve high switching speeds and low on-resistance. Therefore, SiC-based converters have great application potential in hybrid / electric vehicles, solar inverters, and uninterruptible power supplies.

[0003] At present, how to effectively reduce the on-resistance of silicon carbide metal-oxide field-effect transistors, effectively reduce the area of ​​power devices, and effectively reduce the cost of power devices are still the main issues that power device engineers need to consider during the design stage. Summary of the invention

[0004] The present invention provides a double-sided epitaxial layer silicon carbide metal-oxide field effect transistor power device to reduce the on-resistance of the power device, effectively reduce the area of ​​the power device and reduce the cost of the power device.

[0005] According to one aspect of the present invention, there is provided a double-sided epitaxial layer silicon carbide metal-oxide field effect transistor power device, comprising:

[0006] An N-type silicon carbide substrate, the N-type silicon carbide substrate comprising a first surface and a second surface arranged opposite to the first surface;

[0007] A first N-type silicon carbide metal-oxide field effect transistor, wherein the first N-type silicon carbide metal-oxide field effect transistor is located on a first surface of the N-type silicon carbide substrate;

[0008] The first N-type silicon carbide metal-oxide field effect transistor includes a first gate structure, a first source structure and a first drain structure;

[0009] A second N-type silicon carbide metal-oxide field effect transistor, wherein the second N-type silicon carbide metal-oxide field effect transistor is located on a second surface of the N-type silicon carbide substrate;

[0010] The second N-type silicon carbide metal-oxide field effect transistor includes a second gate structure, a second source structure and a second drain structure;

[0011] The first gate structure and the second gate structure are connected to the same gate power signal, the first source structure and the second source structure are connected to the same source power signal, and the first drain structure and the second drain structure are connected to the same drain power signal, so that the first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are connected in parallel;

[0012] The first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are arranged in mirror symmetry with respect to the N-type silicon carbide substrate.

[0013] Optionally, the first N-type silicon carbide metal-oxide field effect transistor includes at least one of a planar structure, a single trench structure, and a double trench structure;

[0014] The second N-type silicon carbide metal-oxide field effect transistor includes at least one of a planar structure, a single trench structure, and a double trench structure.

[0015] Optionally, the first N-type silicon carbide metal-oxide field effect transistor includes:

[0016] A first N-type silicon carbide epitaxial drift region, wherein the first N-type silicon carbide epitaxial drift region is located on a first surface of the N-type silicon carbide substrate;

[0017] A first P-type body region, wherein the first P-type body region is located on a side of the first N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate;

[0018] A first active region, the first active region comprising a first N-type active region and a first P-type active region, the first P-type active region surrounding the first N-type active region;

[0019] A first gate structure, the first gate structure is located on a side of the first N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate, the first gate structure comprises a first gate dielectric layer and a first gate, the first gate dielectric layer is in contact with the first N-type silicon carbide epitaxial drift region;

[0020] a first source structure, wherein the first source structure covers a portion of the first active area;

[0021] A first drain structure, wherein the first drain structure is located on a first surface of the N-type silicon carbide substrate.

[0022] Optionally, the second N-type silicon carbide metal-oxide field effect transistor includes:

[0023] A second N-type silicon carbide epitaxial drift region, wherein the second N-type silicon carbide epitaxial drift region is located on a second surface of the N-type silicon carbide substrate;

[0024] A second P-type body region, wherein the second P-type body region is located on a side of the second N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate;

[0025] a second active region, the second active region comprising a second N-type active region and a second P-type active region, the second P-type active region surrounding the second N-type active region;

[0026] A second gate structure, the second gate structure is located on a side of the second N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate, the second gate structure comprises a second gate dielectric layer and a second gate, and the second gate dielectric layer is in contact with the second N-type silicon carbide epitaxial drift region;

[0027] a second source structure, wherein the second source structure covers a portion of the second active area;

[0028] A second drain structure is provided on a second surface of the N-type silicon carbide substrate.

[0029] Optionally, the first gate structure is a trench gate structure, the first gate structure is located in the first N-type active region, penetrates the first N-type active region, and extends from the first N-type active region via the first P-type body region to a partial area of ​​the first N-type silicon carbide epitaxial drift region, the first gate dielectric layer is in contact with the first N-type active region, the first P-type body region and the first N-type silicon carbide epitaxial drift region, and the first gate is located in the first gate dielectric layer.

[0030] Optionally, the second gate structure is a trench gate structure, the second gate structure is located in the second N-type active region, penetrates the second N-type active region, and extends from the second N-type active region via the second P-type body region to a partial area of ​​the second N-type silicon carbide epitaxial drift region, the second gate dielectric layer is in contact with the second N-type active region, the second P-type body region and the second N-type silicon carbide epitaxial drift region, and the second gate is located in the second gate dielectric layer.

[0031] Optionally, the first gate structure is a trench gate structure, the first gate structure is located in the first N-type active region, penetrates the first N-type active region, and extends from the first N-type active region via the first P-type body region to a partial region of the first N-type silicon carbide epitaxial drift region, the first gate dielectric layer is in contact with the first N-type active region, the first P-type body region, and the first N-type silicon carbide epitaxial drift region, and the first gate is located in the first gate dielectric layer;

[0032] The first source structure is a trench source structure. The first source structure is located in the first active region. The first source structure penetrates the first N-type active region and extends to a partial region of the first P-type body region.

[0033] Optionally, the second gate structure is a trench gate structure, the second gate structure is located in the second N-type active region, penetrates the second N-type active region, and extends from the second N-type active region via the second P-type body region to a partial region of the second N-type silicon carbide epitaxial drift region, the second gate dielectric layer is in contact with the second N-type active region, the second P-type body region and the second N-type silicon carbide epitaxial drift region, and the second gate is located in the second gate dielectric layer;

[0034] The second source structure is a trench source structure. The second source structure is located in the second active region. The second source structure penetrates the second N-type active region and extends to a partial region of the second P-type body region.

[0035] The technical solution provided by the embodiment of the present invention is that the first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are mirror-symmetrical about the N-type silicon carbide substrate. The above technical solution stacks the two N-type silicon carbide metal-oxide field effect transistors in the vertical direction, which greatly reduces the horizontal area of ​​the power device, effectively reduces the area of ​​the power device, and reduces the production cost. And the first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are connected in parallel, which can greatly reduce the on-resistance of the power device. In summary, the technical solution provided by the embodiment of the present invention can effectively reduce the area of ​​the power device, reduce the on-resistance of the power device, and reduce the production cost of the power device under the same voltage and current levels.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a schematic structural diagram of a double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided according to an embodiment of the present invention;

[0039] Figure 2 It is a schematic structural diagram of another double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided in an embodiment of the present invention;

[0040] Figure 3 It is a schematic structural diagram of another double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or devices that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] In order to reduce the on-resistance of power devices, effectively reduce the area of ​​power devices and reduce the cost of power devices, the embodiments of the present invention provide the following technical solutions:

[0044] Figure 11 is a schematic structural diagram of a double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided according to an embodiment of the present invention. Figure 2 is a schematic structural diagram of another double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided according to an embodiment of the present invention, Figure 3 is a schematic structural diagram of another double-sided epitaxial silicon carbide metal-oxide field effect transistor power device provided according to an embodiment of the present invention, such as Figure 1-Figure 3 As shown, the double-sided epitaxial layer silicon carbide metal-oxide field effect transistor power device includes: an N-type silicon carbide substrate 100, the N-type silicon carbide substrate 100 includes a first surface and a second surface arranged opposite to the first surface; a first N-type silicon carbide metal-oxide field effect transistor 200, the first N-type silicon carbide metal-oxide field effect transistor 200 is located on the first surface of the N-type silicon carbide substrate 100; the first N-type silicon carbide metal-oxide field effect transistor 200 includes a first gate structure 201, a first source structure 202 and a first drain structure 203; a second N-type silicon carbide metal-oxide field effect transistor 300, the second N-type silicon carbide metal-oxide field effect transistor 300 is located on the second surface of the N-type silicon carbide substrate 100; the second The N-type silicon carbide metal-oxide field effect transistor 300 includes a second gate structure 301, a second source structure 302, and a second drain structure 303; the first gate structure 201 and the second gate structure 301 are connected to the same gate power signal, the first source structure 202 and the second source structure 302 are connected to the same source power signal, and the first drain structure 203 and the second drain structure 303 are connected to the same drain power signal, so that the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are connected in parallel; the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are arranged in mirror symmetry with respect to the N-type silicon carbide substrate 100.

[0045] In this embodiment, epitaxial layers of the same thickness are grown on the first surface and the second surface of the N-type silicon carbide substrate 100 that are arranged opposite to each other, and then N-type silicon carbide metal-oxide field effect transistors (MOSFETs) are fabricated on both epitaxial layers. The epitaxial layers and drain structures of the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 share the N-type silicon carbide substrate 100, that is, the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are formed to be mirror-symmetrical with respect to the N-type silicon carbide substrate 100. Since the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are arranged to be mirror-symmetrical with respect to the N-type silicon carbide substrate 100, the thickness and shape of the epitaxial layers of the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 with respect to the N-type silicon carbide substrate 100 are completely the same.

[0046] The technical solution provided by the embodiment of the present invention is that the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are mirror-symmetrical about the N-type silicon carbide substrate 100. The above technical solution stacks the two N-type silicon carbide metal-oxide field effect transistors in the vertical direction, which greatly reduces the horizontal area of ​​the power device, effectively reduces the area of ​​the power device, and reduces the production cost. And the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are connected in parallel, which can greatly reduce the on-resistance of the power device. In summary, the technical solution provided by the embodiment of the present invention can effectively reduce the area of ​​the power device, reduce the on-resistance of the power device, and reduce the production cost of the power device at the same voltage and current level.

[0047] Compared with Si devices, SiC power devices can effectively achieve high efficiency, miniaturization and lightweight of power electronic systems. It is understood that the energy loss of SiC power devices is only 50% of that of Si devices, the heat generation is only 50% of that of Si devices, and they have higher current density. At the same power level, the volume of SiC power modules is significantly smaller than that of Si power modules. Taking the intelligent power module (IPM) as an example, using SiC power devices, the module volume can be reduced to 1 / 3 to 2 / 3 of that of Si power modules.

[0048] Optionally, based on the above technical solution, the first N-type silicon carbide metal-oxide field effect transistor 200 includes at least one of a planar structure, a single trench structure and a double trench structure; the second N-type silicon carbide metal-oxide field effect transistor 300 includes at least one of a planar structure, a single trench structure and a double trench structure.

[0049] Specifically, Figure 1 As shown, the first N-type silicon carbide metal-oxide field effect transistor 200 includes a planar structure, and the second N-type silicon carbide metal-oxide field effect transistor 300 includes a planar structure. The first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are mirror-symmetrical with respect to the N-type silicon carbide substrate 100.

[0050] like Figure 2 As shown, the first N-type silicon carbide metal-oxide field effect transistor 200 includes a single trench structure, the second N-type silicon carbide metal-oxide field effect transistor 300 includes a single trench structure, and the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are mirror-symmetrical with respect to the N-type silicon carbide substrate 100.

[0051] like Figure 3 As shown, the first N-type silicon carbide metal-oxide field effect transistor 200 includes a double trench structure, the second N-type silicon carbide metal-oxide field effect transistor 300 includes a double trench structure, and the first N-type silicon carbide metal-oxide field effect transistor 200 and the second N-type silicon carbide metal-oxide field effect transistor 300 are mirror-symmetrical with respect to the N-type silicon carbide substrate 100.

[0052] Optionally, based on the above technical solution, Figure 1 As shown, the first N-type silicon carbide metal-oxide field effect transistor 200 includes: a first N-type silicon carbide epitaxial drift region 204, the first N-type silicon carbide epitaxial drift region 204 is located on the first surface of the N-type silicon carbide substrate 100; a first P-type body region 205, the first P-type body region 205 is located on a side of the first N-type silicon carbide epitaxial drift region 204 away from the N-type silicon carbide substrate 100; a first active region 206, the first active region 206 includes a first N-type active region 207 and a first P-type active region 208, the first P-type active region 208 surrounds A first N-type active region 207; a first gate structure 201, the first gate structure 201 is located on a side of the first N-type silicon carbide epitaxial drift region 204 away from the N-type silicon carbide substrate 100, the first gate structure 201 includes a first gate dielectric layer 209 and a first gate 2010, the first gate dielectric layer 209 is in contact with the first N-type silicon carbide epitaxial drift region 204; a first source structure 202, the first source structure 202 covers a portion of the first active region 206; a first drain structure 203 is located on the first surface of the N-type silicon carbide substrate 100.

[0053] Specifically, the first N-type silicon carbide epitaxial drift region 204, the first P-type body region 205, and the first active region 206 including the first N-type active region 207 and the first P-type active region 208 are made of an epitaxial layer made on the first surface of the N-type silicon carbide substrate 100. Among them, the first N-type silicon carbide epitaxial drift region 204 is a lightly doped N-type silicon carbide epitaxial drift region (N-Drift). The first P-type body region 205 is a lightly doped P-type body region (P-Well). The first N-type active region 207 is a heavily doped (N++) N-type active region. The first P-type active region 208 is a heavily doped (P+) P-type active region. The first gate is prepared by a heavily doped polysilicon process. The first drain is prepared by a metal deposition process. The above technical solution enables a first N-type silicon carbide metal-oxide field effect transistor 200 with a planar structure to be provided on the first surface of the N-type silicon carbide substrate 100.

[0054] Optionally, based on the above technical solution, Figure 1 As shown, the second N-type silicon carbide metal-oxide field effect transistor 300 includes: a second N-type silicon carbide epitaxial drift region 304, the second N-type silicon carbide epitaxial drift region 304 is located on the second surface of the N-type silicon carbide substrate 100; a second P-type body region 305, the second P-type body region 305 is located on a side of the second N-type silicon carbide epitaxial drift region 304 away from the N-type silicon carbide substrate 100; a second active region 306, the second active region 306 includes a second N-type active region 307 and a second P-type active region 308, the second P-type active region 308 surrounds the second N-type active region A source region 307; a second gate structure 301, the second gate structure 301 is located on a side of the second N-type silicon carbide epitaxial drift region 304 away from the N-type silicon carbide substrate 100, the second gate structure 301 includes a second gate dielectric layer 309 and a second gate 3010, the second gate dielectric layer 309 is in contact with the second N-type silicon carbide epitaxial drift region 304; a second source structure 302, the second source structure 302 covers a portion of the second active region 306; a second drain structure 303, the second drain structure 303 is located on the second surface of the N-type silicon carbide substrate 100.

[0055] Specifically, the second N-type silicon carbide epitaxial drift region 304, the second P-type body region 305, and the second active region 306 including the second N-type active region 307 and the second P-type active region 308 are made of an epitaxial layer made on the second surface of the N-type silicon carbide substrate 100. Among them, the second N-type silicon carbide epitaxial drift region 304 is a lightly doped N-type silicon carbide epitaxial drift region (N-Drift). The second P-type body region 305 is a lightly doped P-type body region (P-Well). The second N-type active region 307 is a heavily doped (N++) N-type active region. The second P-type active region 308 is a heavily doped (P+) P-type active region. The second gate is prepared by a heavily doped polysilicon process. The second drain is prepared by a metal deposition process. The above technical solution enables a second N-type silicon carbide metal-oxide field effect transistor 300 with a planar structure to be provided on the second surface of the N-type silicon carbide substrate 100.

[0056] Optionally, based on the above technical solution, Figure 2 As shown, the first gate structure 201 is a trench gate structure, the first gate structure 201 is located in the first N-type active region 207, penetrates the first N-type active region 207, and extends from the first N-type active region 207 via the first P-type body region 205 to a partial area of ​​the first N-type silicon carbide epitaxial drift region 204, the first gate dielectric layer 209 is in contact with the first N-type active region 207, the first P-type body region 205 and the first N-type silicon carbide epitaxial drift region 204, and the first gate 2010 is located in the first gate dielectric layer 209.

[0057] Specifically, the above technical solution provides a first N-type silicon carbide metal-oxide field effect transistor 200 with a single trench structure on the first surface of the N-type silicon carbide substrate 100. The trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance.

[0058] Optionally, based on the above technical solution, Figure 2 As shown, the second gate structure 301 is a trench gate structure, the second gate structure 301 is located in the second N-type active region 307, penetrates the second N-type active region 307, and extends from the second N-type active region 307 via the second P-type body region 305 to a partial area of ​​the second N-type silicon carbide epitaxial drift region 304, the second gate dielectric layer 309 is in contact with the second N-type active region 307, the second P-type body region 305 and the second N-type silicon carbide epitaxial drift region 304, and the second gate 3010 is located in the second gate dielectric layer 309.

[0059] Specifically, the above technical solution enables a second N-type silicon carbide metal-oxide field effect transistor 300 with a single trench structure to be provided on the second surface of the N-type silicon carbide substrate 100. The trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance.

[0060] Optionally, based on the above technical solution, Figure 3 As shown, the first gate structure 201 is a trench gate structure, the first gate structure 201 is located in the first N-type active region 207, penetrates the first N-type active region 207, and extends from the first N-type active region 207 to a partial area of ​​the first N-type silicon carbide epitaxial drift region 204 via the first P-type body region 205, the first gate dielectric layer 209 is in contact with the first N-type active region 207, the first P-type body region 205 and the first N-type silicon carbide epitaxial drift region 204, and the first gate 2010 is located in the first gate dielectric layer 209; the first source structure 202 is a trench source structure, the first source structure 202 is located in the first active region 206, the first source structure 202 penetrates the first N-type active region 207, and extends to a partial area of ​​the first P-type body region 205.

[0061] Specifically, the above technical solution enables a first N-type silicon carbide metal-oxide field effect transistor 200 with a double trench structure to be provided on the first surface of the N-type silicon carbide substrate 100. The trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance. The trench source structure can effectively alleviate the electric field distribution under the trench gate dielectric layer.

[0062] Optionally, based on the above technical solution, Figure 3 As shown, the second gate structure 301 is located in the second N-type active region 307, penetrates the second N-type active region 307, and extends from the second N-type active region 307 to a partial area of ​​the second N-type silicon carbide epitaxial drift region 304 via the second P-type body region 305. The second gate dielectric layer 309 is in contact with the second N-type active region 307, the second P-type body region 305 and the second N-type silicon carbide epitaxial drift region 304, and the second gate is located in the second gate dielectric layer 309; the second source structure 302 is a trench source structure, the second source structure 302 is located in the second active region 306, the second source structure 302 penetrates the second N-type active region 307, and extends to a partial area of ​​the second P-type body region 305.

[0063] Specifically, the above technical solution enables a second N-type silicon carbide metal-oxide field effect transistor 300 with a double trench structure to be provided on the second surface of the N-type silicon carbide substrate 100. The trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance. The trench source structure can effectively alleviate the electric field distribution under the trench gate dielectric layer.

[0064] Optionally, based on the above technical solution, the first N-type silicon carbide epitaxial drift region 204 and the second N-type silicon carbide epitaxial drift region 304 of the N-type silicon carbide substrate 100 can also be N-type gallium nitride materials, that is, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide substrate, and then a gallium nitride device is prepared on the gallium nitride epitaxial layer.

[0065] Since GaN materials have good heat dissipation performance, high breakdown electric field, high saturation velocity and higher electron mobility, GaN power devices have great application prospects in high-power high-frequency energy conversion and high-frequency microwave communications. Compared with its equivalent silicon field-effect transistor, GaN field-effect transistor has the advantages of lower gate capacitance, lower gate drive voltage and higher rated voltage capability.

[0066] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0067] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A double-sided epitaxial silicon carbide metal-oxide field effect transistor power device, characterized in that: include: An N-type silicon carbide substrate, the N-type silicon carbide substrate comprising a first surface and a second surface arranged opposite to the first surface; A first N-type silicon carbide metal-oxide field effect transistor, wherein the first N-type silicon carbide metal-oxide field effect transistor is located on a first surface of the N-type silicon carbide substrate; The first N-type silicon carbide metal-oxide field effect transistor includes a first gate structure, a first source structure and a first drain structure; A second N-type silicon carbide metal-oxide field effect transistor, wherein the second N-type silicon carbide metal-oxide field effect transistor is located on a second surface of the N-type silicon carbide substrate; The second N-type silicon carbide metal-oxide field effect transistor includes a second gate structure, a second source structure and a second drain structure; The first gate structure and the second gate structure are connected to the same gate power signal, the first source structure and the second source structure are connected to the same source power signal, and the first drain structure and the second drain structure are connected to the same drain power signal, so that the first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are connected in parallel; The first N-type silicon carbide metal-oxide field effect transistor and the second N-type silicon carbide metal-oxide field effect transistor are arranged mirror-symmetrically with respect to the N-type silicon carbide substrate; The first N-type silicon carbide metal-oxide field effect transistor includes at least one of a planar structure, a single trench structure, and a double trench structure; The second N-type silicon carbide metal-oxide field effect transistor includes at least one of a planar structure, a single trench structure, and a double trench structure; The first drain structure is located on the first surface of the N-type silicon carbide substrate; The second drain structure is located on the second surface of the N-type silicon carbide substrate.

2. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 1, characterized in that: The first N-type silicon carbide metal-oxide field effect transistor comprises: A first N-type silicon carbide epitaxial drift region, wherein the first N-type silicon carbide epitaxial drift region is located on a first surface of the N-type silicon carbide substrate; A first P-type body region, wherein the first P-type body region is located on a side of the first N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate; A first active region, the first active region comprising a first N-type active region and a first P-type active region, the first P-type active region surrounding the first N-type active region; A first gate structure, the first gate structure is located on a side of the first N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate, the first gate structure comprises a first gate dielectric layer and a first gate, the first gate dielectric layer is in contact with the first N-type silicon carbide epitaxial drift region; A first source structure, wherein the first source structure covers a portion of the first active area.

3. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 1, characterized in that: The second N-type silicon carbide metal-oxide field effect transistor comprises: A second N-type silicon carbide epitaxial drift region, wherein the second N-type silicon carbide epitaxial drift region is located on a second surface of the N-type silicon carbide substrate; A second P-type body region, wherein the second P-type body region is located on a side of the second N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate; a second active region, the second active region comprising a second N-type active region and a second P-type active region, the second P-type active region surrounding the second N-type active region; A second gate structure, the second gate structure is located on a side of the second N-type silicon carbide epitaxial drift region away from the N-type silicon carbide substrate, the second gate structure comprises a second gate dielectric layer and a second gate, and the second gate dielectric layer is in contact with the second N-type silicon carbide epitaxial drift region; A second source structure, wherein the second source structure covers a portion of the second active area.

4. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 2, characterized in that: The first gate structure is a trench gate structure, which is located in the first N-type active region, penetrates the first N-type active region, and extends from the first N-type active region via the first P-type body region to a partial area of ​​the first N-type silicon carbide epitaxial drift region, the first gate dielectric layer is in contact with the first N-type active region, the first P-type body region and the first N-type silicon carbide epitaxial drift region, and the first gate is located in the first gate dielectric layer.

5. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 3, characterized in that: The second gate structure is a trench gate structure, the second gate structure is located in the second N-type active region, penetrates the second N-type active region, and extends from the second N-type active region via the second P-type body region to a partial area of ​​the second N-type silicon carbide epitaxial drift region, the second gate dielectric layer is in contact with the second N-type active region, the second P-type body region and the second N-type silicon carbide epitaxial drift region, and the second gate is located in the second gate dielectric layer.

6. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 2, characterized in that: The first gate structure is a trench gate structure, the first gate structure is located in the first N-type active region, penetrates the first N-type active region, and extends from the first N-type active region to a partial region of the first N-type silicon carbide epitaxial drift region via the first P-type body region, the first gate dielectric layer is in contact with the first N-type active region, the first P-type body region, and the first N-type silicon carbide epitaxial drift region, and the first gate is located in the first gate dielectric layer; The first source structure is a trench source structure. The first source structure is located in the first active region. The first source structure penetrates the first N-type active region and extends to a partial region of the first P-type body region.

7. The double-sided epitaxial silicon carbide metal-oxide field effect transistor power device according to claim 3, characterized in that: The second gate structure is a trench gate structure, the second gate structure is located in the second N-type active region, penetrates the second N-type active region, and extends from the second N-type active region to a partial region of the second N-type silicon carbide epitaxial drift region via the second P-type body region, the second gate dielectric layer is in contact with the second N-type active region, the second P-type body region and the second N-type silicon carbide epitaxial drift region, and the second gate is located in the second gate dielectric layer; The second source structure is a trench source structure. The second source structure is located in the second active region. The second source structure penetrates the second N-type active region and extends to a partial region of the second P-type body region.

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