An epitaxial structure of a semiconductor device and a method for manufacturing the same, and a semiconductor device

Abstract

Embodiments of the present application provide an epitaxial structure of a semiconductor device, a preparation method thereof and the semiconductor device. The epitaxial structure comprises a substrate, a buffer structure and an insertion structure. The buffer structure comprises at least two buffer layers, and the insertion structure comprises at least one insertion layer. The buffer layers and the insertion layers are arranged in an alternating stack, and any insertion layer is located between two adjacent buffer layers. At least one insertion layer comprises a plurality of island structures, and the buffer layer located on the side of the island structure away from the substrate covers the island structure. By using the above technical solution, the compressive stress generated during the epitaxial layer growth process can be controlled by setting the insertion structure. In this way, the warping of the substrate during the growth process can be reduced, the uniformity of the buffer layer thickness can be improved, and thus the quality of the epitaxial structure and the quality of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an epitaxial structure of a semiconductor device and its fabrication method, and a semiconductor device. Background Technology

[0002] Due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity, GaN semiconductor material is more suitable than Si and GaAs for fabricating high-temperature, high-frequency, high-voltage, and high-power devices.

[0003] Since the epitaxial structure lacks a GaN substrate, GaN epitaxial technology is used to grow GaN on heterogeneous substrates. There is a lattice mismatch between GaN and heterogeneous substrates, which leads to a large number of through dislocations in GaN material. At the same time, the heterogeneous substrate will generate stress on GaN, and the substrate will deform during the growth process, which will affect the uniformity of the substrate surface temperature and lead to a deterioration in the uniformity of GaN growth. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an epitaxial structure of a semiconductor device and a method for fabricating the same, as well as a semiconductor device. By setting an insertion structure, the compressive stress generated during the growth of the epitaxial layer can be controlled, thereby reducing substrate warpage during growth, improving the uniformity of buffer layer thickness, and thus improving the quality of the epitaxial structure and the semiconductor device.

[0005] In a first aspect, embodiments of the present invention provide an epitaxial structure for a semiconductor device, comprising:

[0006] Substrate, buffer structure, and insertion structure;

[0007] The buffer structure includes at least two buffer layers, and the insertion structure includes at least one insertion layer. The buffer layers and the insertion layers are stacked alternately, and any one of the insertion layers is located between two adjacent buffer layers.

[0008] At least one of the insertion layers includes a plurality of island structures, and the buffer layer located on the side of the island structure away from the substrate covers the island structure.

[0009] Optionally, the insertion structure includes multiple insertion layers;

[0010] Each of the inserted layers includes a plurality of the island-like structures.

[0011] Optionally, the multilayer insertion layer includes a first insertion layer and a second insertion layer, wherein the first insertion layer includes a plurality of first island structures and the second insertion layer includes a plurality of second island structures;

[0012] Along the thickness direction of the epitaxial structure, there is at least one first island structure overlapping with the gaps of two adjacent second island structures.

[0013] Optionally, the insertion layer includes In atoms.

[0014] Optionally, the proportion 'a' of the In atoms in the insertion layer satisfies 0. <a≤50%。

[0015] Optionally, the thickness d1 of the insertion layer satisfies 5nm≤d1≤50nm.

[0016] Optionally, the thickness of the buffer structure is d2, and the thickness of the insertion structure is d3;

[0017] Where 40≤d3 / d2≤400.

[0018] Optionally, the epitaxial structure further includes:

[0019] A nucleation layer is located between the substrate and the buffer structure;

[0020] The channel layer is located on the side of the buffer structure away from the substrate;

[0021] A barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure;

[0022] The cap layer is located on the side of the barrier layer away from the substrate.

[0023] Secondly, embodiments of the present invention also provide a method for fabricating an epitaxial structure of a semiconductor device, comprising:

[0024] Provide substrate;

[0025] A buffer structure and an insertion structure are fabricated on one side of the substrate; the buffer structure includes at least two buffer layers, the insertion structure includes at least one insertion layer, the buffer layers and the insertion layers are alternately stacked, and any one of the insertion layers is located between two adjacent buffer layers; the at least one insertion layer includes a plurality of island structures, and the buffer layer located on the side of the island structure away from the substrate covers the island structure.

[0026] Optionally, the insertion layer includes In atoms;

[0027] A buffer structure and an insertion structure are fabricated on one side of the substrate, including:

[0028] At the first preparation temperature, the IN source is turned on to prepare the insertion layer;

[0029] After turning off the IN source, the buffer layer is prepared at the second preparation temperature for a preset time; the second preparation temperature is higher than the first preparation temperature.

[0030] Optionally, the buffer structure includes multiple buffer layers, and the insertion structure includes multiple insertion layers;

[0031] A buffer structure and an insertion structure are fabricated on one side of the substrate, including:

[0032] The buffer layer and the insertion layer are sequentially and alternately fabricated on one side of the substrate.

[0033] Optionally, before preparing the buffer structure, the following steps are also included:

[0034] A nucleation layer is prepared, wherein the nucleation layer is located between the substrate and the buffer structure;

[0035] After preparing the buffer structure, the following steps are also included:

[0036] A channel layer is prepared, wherein the channel layer is located on the side of the buffer structure away from the substrate;

[0037] A barrier layer is prepared, wherein the barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure;

[0038] A cap layer is prepared, the cap layer being located on the side of the barrier layer away from the substrate.

[0039] Thirdly, embodiments of the present invention also provide a semiconductor device, including the epitaxial structure of the semiconductor device described in any embodiment of the first aspect;

[0040] The epitaxial structure further includes a nucleation layer located between the substrate and the buffer structure; a channel layer located on the side of the buffer structure away from the substrate; a barrier layer located on the side of the channel layer away from the substrate, the barrier layer and the channel layer forming a heterojunction structure; and a cap layer located on the side of the barrier layer away from the substrate.

[0041] The semiconductor device further includes:

[0042] The source and drain are located on the side of the barrier layer away from the substrate, and the gate is located on the side of the cap layer away from the substrate, the gate being located between the source and the drain.

[0043] The epitaxial structure of the semiconductor device provided in this embodiment of the invention includes a substrate, a buffer structure, and an insertion structure. By adding at least one insertion layer between two adjacent buffer layers, and by alternately stacking the buffer layers and the insertion layers, as the thickness of the buffer layer increases, multiple island-like structures in the insertion layer will gradually merge into a complete buffer layer. The tensile stress generated during the merging process can offset the compressive stress generated during the epitaxial layer growth process, thereby neutralizing the warping of the substrate during growth, improving the uniformity of the buffer layer thickness, and thus improving the quality of the epitaxial structure and the semiconductor device. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram illustrating the warping changes during the epitaxial structure growth process of a semiconductor device in related technologies.

[0046] Figure 3 This is a schematic diagram illustrating the warping changes during the epitaxial growth process of a semiconductor device, provided by an embodiment of the present invention.

[0047] Figure 4 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic flowchart of a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention;

[0049] Figure 6 This is a schematic flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0053] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0054] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the epitaxial structure of a semiconductor device provided in this embodiment of the invention includes: a substrate 110, a buffer structure 120, and an insertion structure 130; the buffer structure 120 includes at least two buffer layers 121, the insertion structure 130 includes at least one insertion layer 131, the buffer layers 121 and the insertion layers 131 are alternately stacked, and any insertion layer 131 is located between two adjacent buffer layers 121; the at least one insertion layer 131 includes a plurality of island structures 200, and the buffer layer 121 located on the side of the island structure 200 away from the substrate 110 covers the island structure 200.

[0055] For example, continue to refer to Figure 1 The substrate 110 can be made of Si, SiC, Sapphire, AlN, or any other material suitable for growing nitrides. The substrate 110 can be a high-resistivity substrate to reduce the radio frequency coupling between the substrate 110 and the epitaxial layer, thereby improving the radio frequency performance of the epitaxial structure and the semiconductor device.

[0056] Continue to refer to Figure 1 As shown, the epitaxial structure provided in this embodiment of the invention further includes a buffer structure 120 and an insertion structure 130, wherein the buffer structure 120 includes at least two buffer layers 121. Figure 1 The following description uses at least two buffer layers 121, including a first buffer layer 1211 and a second buffer layer 1212, as an example. The buffer layer 121 can be a high-resistivity buffer layer 121 containing doped impurities, and the material used to prepare the high-resistivity buffer layer 121 can include nitrides. For example, the buffer layer 121 can include a combination of GaN and AlGaN or at least one of these materials, and the doping element can be one or more of C, Fe, and Mg.

[0057] Continue to refer to Figure 1As shown, the insertion structure 130 includes at least one insertion layer 131. For example, the insertion layer 131 may include one or more materials that are easily decomposed at high temperatures, thus further decomposing into multiple independent island structures 200 after the entire insertion layer 131 is fabricated; that is, the insertion layer 131 includes multiple island structures 200. Based on this, a buffer layer 121 is grown on the side of the insertion layer 131 away from the substrate 110. For example, when growing a second buffer layer 1212, the second buffer layer 1212 first fills the gaps between the island structures 200. As the thickness of the second buffer layer 1212 increases, the second buffer layer 1212 gradually merges into a complete buffer layer 121 on the side of the island structures 200 away from the substrate 110. During the merging process of the second buffer layer 1212, tensile stress is generated, which counteracts the compressive stress generated during the epitaxial layer growth process, neutralizes the warping phenomenon of the substrate during growth, ensures the normal growth of other epitaxial layers, and improves the quality of the epitaxial structure and the semiconductor device.

[0058] Specifically, Figure 2 This is a schematic diagram illustrating the warping changes during the epitaxial growth process of a semiconductor device in related technologies. Figure 3 This is a schematic diagram illustrating the warping changes during the epitaxial structure growth process of a semiconductor device, as provided in an embodiment of the present invention. Figure 2 and Figure 3 The horizontal axis represents the growth time of the epitaxial structure, and the vertical axis represents the warpage of the substrate (convex or concave). Taking a buffer structure consisting of two buffer layers as an example... Figure 2 The first buffer layer can be grown during the growth time t2'-t3', and the second buffer layer can be grown during the growth time t3'-t4'. Compressive stress will gradually accumulate during the growth of the buffer layer. If no intercalation layer is added between the two buffer layers, the substrate will be very convex after the buffer layer growth is completed. Figure 3 During the growth period t2-t3, the first buffer layer can grow; during the growth period t3-t4, the insertion layer can grow; and during the growth period t4-t5, the second buffer layer can grow. During the growth of the second buffer layer, the initial growth preferentially fills the gaps in the insertion layer. As the second buffer layer continues to grow, the island-like structures gradually merge. Tensile stress is generated during this merging process to counteract compressive stress. Figure 2 and Figure 3 It is evident that reducing substrate warpage ensures the normal growth of other epitaxial layers, thereby improving the quality of epitaxial structures and semiconductor devices.

[0059] Furthermore, since there are many dislocations during the epitaxial structure generation process, by setting multiple independently set island structures in the insertion layer, it is possible to prevent dislocations from extending further to the surface of the epitaxial structure, which means that dislocations can be filtered out, thereby improving the quality of the epitaxial structure and the quality of the semiconductor device.

[0060] In summary, the epitaxial structure of the semiconductor device provided in this embodiment of the invention, by adding at least one insertion layer between two adjacent buffer layers and by alternately stacking the buffer layers and the insertion layers, allows multiple island-like structures in the insertion layer to gradually merge into a complete buffer layer as the thickness of the buffer layer increases. The tensile stress generated during the merging process can offset the compressive stress generated during the growth of the epitaxial layer, thereby neutralizing the warping of the substrate during the growth process, improving the uniformity of the buffer layer thickness, and thus improving the quality of the epitaxial structure and the quality of the semiconductor device.

[0061] Optional, Figure 4 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention. Figure 4 As shown, the insertion structure 130 includes multiple insertion layers 131; each insertion layer 131 includes multiple island structures 200.

[0062] For example, refer to Figure 4 When the insertion layer 131 has two or more layers, a "sandwich" structure of buffer layer 121, insertion layer 131, and buffer layer 121 can be repeatedly grown sequentially on the substrate 110. This embodiment of the invention does not specifically limit the number of insertion layers 131; for ease of description, it is taken as two layers of insertion layer 131 as an example. (Continue referring to...) Figure 4When the insertion structure 130 in the epitaxial structure of the semiconductor device consists of two insertion layers 131, specifically, a first buffer layer 1211, a first insertion layer 1311, a second buffer layer 1212, a second insertion layer 1312, and a third buffer layer 1213 can be sequentially grown on the substrate 110. Each insertion layer 131 includes multiple island structures 200. Based on this, a buffer layer 121 is further grown on the side of the insertion layer 131 away from the substrate 110. For example, when growing the second buffer layer 1212, the second buffer layer 1212 first fills the gaps between the island structures 200. When growing the third buffer layer 1213, the third buffer layer 1213 first fills the gaps between the island structures 200. Furthermore, when the total thickness of the buffer layer 121 is approximately greater than 1000 nm (exemplarily, the total thickness of the buffer layer 121 can also be 990 nm-1010 nm), as the growth thickness of the second buffer layer 1212 and the third buffer layer 1213 increases, the second buffer layer 1212 and the third buffer layer 1213 will gradually merge into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. Tensile stress is generated during the merging process of the second buffer layer 1212 and the third buffer layer 1213, which can repeatedly offset the compressive stress generated during the epitaxial layer growth process. This allows for repeated adjustment and neutralization of substrate warpage during growth. Optionally, when the total thickness of the buffer layer 121 is approximately greater than 2000 nm, by alternately stacking the buffer layer 121 and the insertion layer 131, substrate warpage during growth can be neutralized. Therefore, the uniformity of the buffer layer 121 thickness can be improved, ensuring the normal growth of other epitaxial layers, and improving the quality of the epitaxial structure and the semiconductor device.

[0063] Optional, continue to refer to Figure 4 The multilayer insertion layer 131 includes a first insertion layer 1311 and a second insertion layer 1312. The first insertion layer 1311 includes a plurality of first island structures 201, and the second insertion layer 1312 includes a plurality of second island structures 202. Along the thickness direction of the epitaxial structure (X direction as shown in the figure), there is at least one first island structure 201 with a gap overlap with two adjacent second island structures 202.

[0064] For example, continue to refer to Figure 4In the first insertion layer 1311, at least one first island structure 201 overlaps with the gaps of two adjacent second island structures 202. Specifically, the existence of at least one overlapping gap between the first island structure 201 and two adjacent second island structures 202 can be understood as the arrangement of the multiple first island structures 201 in the first insertion layer 1311 and the multiple second island structures 202 in the second insertion layer 1312 is not entirely the same; that is, not all second island structures 202 are located directly above the first island structure 201. By ensuring that at least one first island structure 201 overlaps with the gaps of two adjacent second island structures 202, this embodiment of the invention ensures, on the one hand, the normal growth of the buffer layer 121, and on the other hand, a large overall coverage area of ​​the island structures 200. This provides good shielding and filtering effects on dislocation locations exposed on the surface of the buffer layer 121, thereby preventing dislocations from further extending to the surface of the epitaxial structure. In other words, it filters dislocations, improving the quality of the epitaxial structure and the semiconductor device.

[0065] Optional, continue to refer to Figure 1 The insertion layer 131 includes In atoms.

[0066] Specifically, the insertion layer 131 can be a nitride containing In atoms. For example, the material of the insertion layer 131 can be InGaN, InAlN, or InAlGaN. Since In atoms are easily decomposed at temperatures above 800°C, but Ga atoms remain in the epitaxial layer, the decomposition of In atoms will create voids. After annealing, the bottom layers of the insertion layers 131 are connected to each other, while the top layers are separated from each other, thus forming an island-like structure 200. Based on this, a buffer layer 121 is grown on the side of the insertion layer 131 away from the substrate 110. For example, when growing the second buffer layer 1212, the second buffer layer 1212 first fills the gaps between the island structures 200. As the thickness of the second buffer layer 1212 increases, the second buffer layer 1212 will gradually merge into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. Tensile stress will be generated during the merging process of the second buffer layer 1212, which will then offset the compressive stress generated during the epitaxial layer growth process, neutralize the warping phenomenon of the substrate during the growth process, ensure the normal growth of other epitaxial layers, and improve the quality of the epitaxial structure and the quality of the semiconductor device.

[0067] Optional, continue to refer to Figure 1 The percentage of In atoms 'a' in insertion layer 131 satisfies 0. <a≤50%。

[0068] Specifically, the proportion of In atoms in the insertion layer 131 does not exceed 50%. If the atomic number ratio a of In atoms is too large, it is not easy to form the island structure 200 after annealing. By setting the atomic number ratio a of In atoms in the insertion layer 131 to satisfy 0 < a ≤ 50%, it is possible to avoid the continuous film formation of the insertion layer 131 grown on the upper surface of the buffer layer 121, which affects the continued growth of the buffer layer 121 on the insertion layer 131. In this way, it is possible to ensure that the insertion layer 131 with multiple independent island structures 200 is formed on the upper surface of the buffer layer 121, thereby ensuring the normal growth and preparation of the epitaxial structure of the semiconductor device.

[0069] Optionally, continue to refer to Figure 1 , the thickness d1 of the insertion layer 131 satisfies 5 nm ≤ d1 ≤ 50 nm.

[0070] Specifically, continue to refer to Figure 1 , when the thickness d1 of the insertion layer 131 < 5 nm, due to the too thin thickness d1 of the insertion layer 131, the distance between adjacent island structures 200 after annealing will be too far. That is to say, when the thickness of the buffer layer 121 increases, due to the relatively far distance between adjacent island structures 200, when preparing the buffer layer 121 on the side of the insertion layer 131 away from the substrate 110, the merging effect is not obvious, and no large tensile stress will be generated during the merging process of the buffer layer 121, that is, it cannot offset the compressive stress generated during the growth of the epitaxial layer too much, and the warping of the substrate 110 during the growth process will still be caused, which is not conducive to the subsequent growth of the epitaxial layer. When the thickness d1 of the insertion layer 131 > 50 nm, due to the too thick thickness d1 of the insertion layer 131, it is not easy to form the island structure 200 after annealing. For example, a continuously arranged insertion layer 131 is formed as a whole layer. In this case, there is no merging of the buffer layer 121, and no tensile stress will be generated during the merging process of the buffer layer 121, that is, it cannot offset the compressive stress generated during the growth of the epitaxial layer, and the warping of the substrate 110 during the growth process will still be caused, which is not conducive to the subsequent growth of the epitaxial layer. It can be understood that when the thickness d1 of the insertion layer 131 satisfies 5 nm ≤ d1 ≤ 50 nm, it can ensure that multiple independent island structures 200 can be formed in the insertion layer 131 after annealing, and the distance between adjacent island structures 200 is appropriate, which can ensure that the second buffer layer 1212 gradually merges into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. The tensile stress generated during the merging process of the second buffer layer 1212 can offset the compressive stress generated during the growth of the epitaxial layer, neutralize the warping phenomenon of the substrate during the growth process, ensure the normal growth of other epitaxial layers, and improve the quality of the epitaxial structure and the quality of the semiconductor device. Moreover, when the thickness d1 of the insertion layer 131 is set to satisfy 5 nm ≤ d1 ≤ 50 nm, that is, the thickness of the insertion layer 131 is appropriate, it can also ensure that the preparation process of the insertion layer 131 is simple.

[0071] Optional, continue to refer to Figure 1 The thickness of the buffer structure 120 is d2, and the thickness of the insertion structure 130 is d3; where 40≤d2 / d3≤400.

[0072] For example, when the buffer structure 120 includes two buffer layers, continue to refer to Figure 1 The thickness d2 of the buffer structure 120 is the sum of the thickness d21 of the first buffer layer 1211 and the thickness d22 of the second buffer layer 1212; when the buffer structure 120 includes three or more buffer layers 121, the thickness d2 of the buffer structure 120 refers to the sum of the thicknesses of the three or more buffer layers.

[0073] For details, please refer to [link / reference]. Figure 1 When d2 / d3 > 400, it indicates that the thickness of the buffer structure 120 is much greater than the thickness of the insertion structure 130. This will cause the tensile stress generated by the island structure 200 in the insertion layer 131 during the merging process to be insufficient to offset the compressive stress generated during the epitaxial layer growth process. Consequently, it cannot neutralize the warpage of the substrate 110 during the growth process, and the warpage cannot be effectively controlled. When d2 / d3 < 40, the thickness d1 of the insertion layer 131 is too thick, making it difficult to form the island structure 200 after annealing. For example, it is difficult to form a continuous insertion layer 131. In this case, there is no merging of the buffer layer 121, and the tensile stress generated during the merging process of the buffer layer 121 will not be offset. This means that the compressive stress generated during the epitaxial layer growth process cannot be offset, and the warpage cannot be effectively controlled, thus affecting the growth quality of the epitaxial layer. In this embodiment of the invention, by setting 40≤d2 / d3≤400, it can ensure that the island structures 200 in the insertion layer 131 are normally merged as the buffer layer 121 is added. On the other hand, it can also ensure that the tensile stress generated during the merging of the island structures 200 can offset the compressive stress generated during the epitaxial layer growth process. In this way, the warping of the substrate 110 during the growth process can be neutralized, and the uniformity of the thickness of the buffer layer 121 can be improved.

[0074] Optional, continue to refer to Figure 1 The epitaxial structure further includes: a nucleation layer 140 located between the substrate 110 and the buffer structure 120; a channel layer located on the side of the buffer structure 120 away from the substrate 110; a barrier layer 150 located on the side of the channel layer away from the substrate 110, wherein the barrier layer 150 and the channel layer form a heterojunction structure; and a cap layer 160 located on the side of the barrier layer 150 away from the substrate 110.

[0075] For example, continue to refer to Figure 1The nucleation layer 140 is located between the substrate 110 and the buffer structure 120, serving to bond the semiconductor material layer to be grown next. The material of the nucleation layer 140 can be a combination of AlN and AlGaN or at least one of them, and the thickness of the nucleation layer 140 can be 50-200 nm.

[0076] For example, the channel layer (not shown in the figure) is located on the side of the buffer structure 120 away from the substrate 110, and the material of the channel layer can be GaN. It should be noted that the buffer layer 121 can be reused as a channel layer; that is, the buffer layer 121 and the barrier layer 150 form a heterojunction structure, i.e., a region for forming a two-dimensional electron gas (2DEG), such as... Figure 1 As shown by the dashed line.

[0077] For example, the barrier layer 150 is located on the side of the channel layer away from the substrate 110. The material used to fabricate the barrier layer 150 includes ternary nitrides, which may include at least one of InAlN, AlGaN, InAlGaN or other semiconductor materials. The thickness of the barrier layer 150 may be 5-50 nm.

[0078] For example, the cap layer 160 is located on the side of the barrier layer 150 away from the substrate 110. The cap layer 160 can be used to passivate the surface of the barrier layer 150, reduce gate leakage current, and facilitate metal / semiconductor ohmic contact. The cap layer 160 can reduce surface leakage current of subsequent semiconductor devices and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and semiconductor devices. Optionally, the material of the cap layer 160 can be a group III nitride, such as p-type doped gallium nitride (P-GaN). The P-GaN structure can effectively reduce the barrier height of the barrier layer 150. Optionally, the cap layer 160 can be a GaN layer with a thickness between 1 nm and 10 nm.

[0079] It should be understood that the embodiments of the present invention are based on the design of the epitaxial structure of semiconductor devices. By adding at least one insertion layer between two adjacent buffer layers and stacking the buffer layer and the insertion layer alternately, as the thickness of the buffer layer increases, multiple island-like structures in the insertion layer will gradually merge into a complete buffer layer. The tensile stress generated during the merging process can offset the compressive stress generated during the growth of the epitaxial layer, thereby neutralizing the warping of the substrate during the growth process, improving the uniformity of the buffer layer thickness, and thus improving the quality of the epitaxial structure and the quality of the semiconductor device. The semiconductor devices include, but are not limited to: high-power HEMTs operating in high-voltage, high-current environments; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors.

[0080] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating the epitaxial structure of a semiconductor device. Figure 5 This is a schematic flowchart illustrating a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention may include:

[0081] S101, Provide substrate.

[0082] For example, the substrate can be a high-resistivity substrate to reduce radio frequency coupling between the substrate and the epitaxial layer, thereby improving the radio frequency performance of the epitaxial structure and semiconductor devices. The substrate can be made of Si, SiC, Sapphire, AlN, or any other material suitable for growing nitrides. The substrate can be prepared by methods such as atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal-organic compound vapor deposition, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0083] S102. A buffer structure and an insertion structure are prepared on one side of the substrate. The buffer structure includes at least two buffer layers, and the insertion structure includes at least one insertion layer. The buffer layers and the insertion layers are stacked alternately, and any insertion layer is located between two adjacent buffer layers. The at least one insertion layer includes multiple island structures, and the buffer layer on the side of the island structure away from the substrate covers the island structure.

[0084] For example, the buffer structure and the insertion structure can be fabricated in a metal-organic chemical vapor deposition (MOCVD) chamber, and the buffer structure and the insertion structure are fabricated on one side of the substrate. The buffer structure includes at least two buffer layers, which can be high-resistivity buffer layers containing doped impurities. The buffer layers can include a combination of GaN and AlGaN or at least one of these materials. The doping element can be one or more of C, Fe, and Mg, ensuring that vertical leakage current is blocked and the pinch-off performance of the semiconductor device is improved. The insertion structure includes at least one insertion layer, which can include one or more materials that are easily decomposed at high temperatures.

[0085] For details, please refer to Figure 1The insertion layer 131 includes multiple island structures 200, and a buffer layer 121 covers the island structures 200 on the side of the island structures 200 away from the substrate 110. By setting the insertion layer 131 between the two buffer layers 121 and then annealing in situ, since the insertion layer 131 may include one or more materials that are easily decomposed at high temperatures, these materials are easily decomposed during the annealing process. Thus, after the entire insertion layer 131 is prepared, it will further decompose into multiple independent island structures 200, that is, the insertion layer 131 includes multiple island structures 200. This can prevent dislocations from extending further to the surface of the epitaxial structure, that is, it can filter dislocations and improve the quality of the epitaxial structure and the quality of the semiconductor device. Based on this, a buffer layer 121 is grown on the side of the insertion layer 131 away from the substrate 110. For example, when growing the second buffer layer 1212, the second buffer layer 1212 first fills the gaps between the island structures 200. As the thickness of the second buffer layer 1212 increases, the second buffer layer 1212 will gradually merge into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. Tensile stress will be generated during the merging process of the second buffer layer 1212, which will then offset the compressive stress generated during the epitaxial layer growth process, neutralize the warping phenomenon of the substrate during the growth process, ensure the normal growth of other epitaxial layers, and improve the quality of the epitaxial structure and the quality of the semiconductor device.

[0086] Optional, continue to refer to Figure 1 The thickness d1 of the insertion layer 131 satisfies 5nm≤d1≤50nm, which ensures that multiple island structures 200 can be formed in the insertion layer after annealing, and the distance between adjacent island structures 200 is moderate. As the thickness of the buffer layer 121 increases, the island structures 200 will merge to generate tensile stress, which will offset the compressive stress generated during the epitaxial layer growth process. This will neutralize the warping of the substrate 110 during the growth process and improve the uniformity of the thickness of the buffer layer 121.

[0087] Optional, continue to refer to Figure 1 The thickness of the buffer structure 120 is d2, and the thickness of the insertion structure 130 is d3; where 40≤d2 / d3≤400. On the one hand, this ensures that the island structures 200 in the insertion layer 131 can merge normally as the buffer layer 121 is added. On the other hand, it also ensures that the tensile stress generated during the merging of the island structures 200 can offset the stress generated during the epitaxial layer growth process. This can neutralize the warping of the substrate 110 during the growth process and improve the thickness uniformity of the buffer layer 121.

[0088] The epitaxial structure fabrication method provided in this invention involves adding at least one insertion layer between two adjacent buffer layers, with the buffer layers and insertion layers stacked alternately. As the thickness of the buffer layer increases, multiple island-like structures in the insertion layer gradually merge into a complete buffer layer. The tensile stress generated during the merging process can offset the stress generated during the epitaxial layer growth, thereby neutralizing the warping of the substrate during growth, improving the uniformity of the buffer layer thickness, and thus improving the quality of the epitaxial structure and the semiconductor device.

[0089] Based on the above embodiments, this invention also provides another method for fabricating the epitaxial structure of a semiconductor device. Figure 6 This is a schematic flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention. Figure 6 As shown, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention may include:

[0090] S201, Provide a substrate.

[0091] S202. At the first preparation temperature, turn on the IN source to prepare the insertion layer, which includes In atoms.

[0092] For example, the intercalation layer can be prepared in a metal-organic chemical vapor deposition (MOCVD) reaction chamber. The initial preparation temperature can be 700°C-800°C, the growth pressure can be 400 mbar-600 mbar, and the growth atmosphere can be N2. Specifically, by turning on the IN source at the initial preparation temperature within the reaction chamber, the intercalation layer can include In atoms.

[0093] For details, please refer to Figure 1 The insertion layer 131 can be a nitride containing In atoms. For example, the material of the insertion layer 131 can be InGaN, InAlN, or InAlGaN. Since In atoms are easily decomposed at temperatures above 800°C, but Ga atoms remain in the epitaxial layer, the decomposition of In atoms creates voids. After annealing, the bottom layers of the insertion layers 131 are connected to each other, while the top layers are separated, forming an island structure 200. As the thickness of the second buffer layer 1212 increases, the second buffer layer 1212 gradually merges into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. The tensile stress generated during the merging process will offset the compressive stress generated during the epitaxial layer growth process, thereby neutralizing the warping of the substrate 110 during growth and improving the thickness uniformity of the buffer layer 121.

[0094] Optional, continue to refer to Figure 1, when the IN source is opened to prepare the insertion layer 131, the atomic number ratio a of In atoms in the insertion layer 131 satisfies 0 < a ≤ 50%, which can prevent the insertion layer 131 grown on the upper surface of the buffer layer 121 from forming a continuous film and affecting the continued growth of the buffer layer 121 on the insertion layer 131. In this way, it can ensure that the insertion layer 131 with multiple island structures 200 is formed on the upper surface of the buffer layer 121, thus ensuring the normal growth and preparation of the epitaxial structure of the semiconductor device.

[0095] S203. Close the IN source. At the second preparation temperature, after maintaining for a preset time, prepare the buffer layer; the second preparation temperature is higher than the first preparation temperature; the buffer structure includes at least two buffer layers, the insertion structure includes at least one insertion layer, the buffer layers and the insertion layers are alternately stacked, and any insertion layer is located between two adjacent buffer layers; at least one insertion layer includes multiple island structures, and the buffer layer on the side of the island structure away from the substrate covers the island structure.

[0096] Exemplarily, the second preparation temperature can be 1050°C. The preset time can be understood as the time for the In atoms in the insertion layer to be fully decomposed. Exemplarily, the preset time can be 30 s.

[0097] Specifically, after the substrate is prepared, a first buffer layer with a thickness of 1 μm can be grown in an environment with a temperature of 1050°C, and the flow rates of the Ga source and the N source can be 1400 μmol / min and 1.6 mol / min respectively. Then, an insertion layer is grown on the upper surface of the buffer layer. After the insertion layer is prepared, the IN source and the Ga source are closed, the growth atmosphere is switched to H2, the growth temperature is raised to 1050°C within 150 s, and maintained for 30 s. Then the Ga source is opened, and a second buffer layer with a thickness of 1 μm can be grown on the insertion layer.

[0098] It should be noted that continue to refer to Figure 1 , because In atoms are prone to decomposition in an environment with a temperature higher than 800°C. Thus, the second preparation temperature is higher than the first preparation temperature, which can cause the insertion layer 131 to form multiple independent island structures 200 due to the temperature increase in the environment of the second preparation temperature, and can prevent the insertion layer 131 grown on the upper surface of the buffer layer 121 from forming a continuous film and affecting the continued growth of the buffer layer 121 on the insertion layer 131, thereby ensuring the normal growth and preparation of the epitaxial structure of the semiconductor device. In addition, as the thickness of the second buffer layer 1212 increases, the second buffer layer 1212 will gradually merge into a complete buffer layer 121 on the side of the island structure 200 away from the substrate 110. The tensile stress generated during the merging process will offset the stress generated during the growth of the epitaxial layer, and thus can neutralize the warping of the substrate 110 during the growth process and improve the thickness uniformity of the buffer layer 121.

[0099] The epitaxial structure fabrication method provided in this invention involves fabricating an insertion layer at a first fabrication temperature, the insertion layer including In atoms, and a buffer layer at a second fabrication temperature, wherein the second fabrication temperature is higher than the first fabrication temperature. This ensures that during the fabrication of the buffer layer, the In atoms decompose due to the increased temperature, thus the insertion layer can form an island-like structure. Furthermore, the tensile stress generated during the merging of the island-like structure can offset the compressive stress generated during the growth of the epitaxial layer, thereby neutralizing the warpage of the substrate during growth and improving the uniformity of the buffer layer thickness.

[0100] Based on the above embodiments, this invention also provides another method for fabricating the epitaxial structure of a semiconductor device. Figure 7 This is a schematic flowchart illustrating another method for fabricating the epitaxial structure of a semiconductor device according to an embodiment of the present invention. Figure 7 As shown, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention may include:

[0101] S301, Provide substrate.

[0102] S302. Buffer layer and insertion layer are alternately prepared on one side of the substrate.

[0103] For example, refer to Figure 4 Each insertion layer 131 is located between two adjacent buffer layers 121; each insertion layer 131 includes a plurality of island structures 200, and the buffer layer 121 located on the side of the island structure 200 away from the substrate 110 covers the island structure 200.

[0104] Specifically, an insertion layer is prepared at a first preparation temperature, and a buffer layer is prepared at a second preparation temperature. The buffer layer and insertion layer are prepared alternately in sequence. That is, the insertion structure includes multiple insertion layers, with the buffer layer and insertion layer overlapping sequentially to form a repeating sandwich structure of buffer layer, insertion layer, and buffer layer. As the thickness of the buffer layer increases, the island-like structures in the insertion layer gradually merge into a complete buffer layer. Therefore, the tensile stress generated during the merging process can be repeatedly offset, adjusting and neutralizing the warping phenomenon that occurs during growth.

[0105] Furthermore, for ease of description, the embodiments of the present invention take an insertion structure comprising two insertion layers as an example, referring to... Figure 4 The multilayer insertion layer 131 includes a first insertion layer 1311 and a second insertion layer 1312. The first insertion layer 1311 includes a plurality of first island structures 201, and the second insertion layer 1312 includes a plurality of second island structures 202. Along the thickness direction of the epitaxial structure, there is at least one first island structure 201 with an overlap between the gaps of two adjacent second island structures 202.

[0106] For details, please refer to [link / reference]. Figure 4 There is at least one first island structure 201 with an overlap between the gaps of two adjacent second island structures 202. This ensures the normal growth of the buffer layer 121 and also ensures that the overall coverage area of ​​the island structure 200 is large, providing good shielding and filtering effects on the dislocation positions exposed on the surface of the buffer layer 121. This prevents dislocations from extending further to the surface of the epitaxial structure, thus filtering out dislocations and improving the quality of the epitaxial structure and the semiconductor device.

[0107] The epitaxial structure fabrication method provided in this invention alternately fabricates a buffer layer and an insertion layer. The tensile stress generated by the island structures in the insertion layer during the merging process can offset the compressive stress generated during the growth of the epitaxial layer, thereby repeatedly adjusting and neutralizing the warping phenomenon that occurs during growth. Furthermore, the presence of at least one first island structure overlapping with the gaps of two adjacent second island structures can prevent dislocations from further extending to the surface of the epitaxial structure, thus filtering dislocations and improving the quality of the epitaxial structure and the semiconductor device.

[0108] Based on the above embodiments, this invention also provides another method for fabricating the epitaxial structure of a semiconductor device. Figure 8 This is a schematic flowchart illustrating another method for fabricating the epitaxial structure of a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, the method for fabricating the epitaxial structure of a semiconductor device provided in this embodiment of the invention may include:

[0109] S401, Provide substrate.

[0110] S402. Prepare a nucleation layer, which is located between the substrate and the buffer structure.

[0111] For example, the substrate was heat-treated to 1100°C for 10 min in an H2 environment. Then, at 1100°C and 100 mbar, with Al and N source flow rates of 144.5 μmol / L and 45 mmol / min respectively, a 50 nm thick AlN nucleation layer was grown on one side of the substrate. The nucleation layer serves to bond the semiconductor material layers that will be grown next.

[0112] S403. A buffer structure and an insertion structure are prepared on one side of the substrate. The buffer structure includes at least two buffer layers, and the insertion structure includes at least one insertion layer. The buffer layers and the insertion layers are stacked alternately, and any insertion layer is located between two adjacent buffer layers. The at least one insertion layer includes multiple island structures, and the buffer layer on the side of the island structure away from the substrate covers the island structure.

[0113] S404. Prepare the channel layer, which is located on the side of the buffer structure away from the substrate.

[0114] Specifically, the channel layer is located on the side of the buffer structure away from the substrate, and the material of the channel layer can be GaN. It should be noted that the buffer layer can be reused as the channel layer, that is, the buffer layer and the barrier layer form a heterojunction structure.

[0115] S405. Prepare a barrier layer. The barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

[0116] Specifically, after the channel layer is fabricated, the Ga source is turned on to grow a barrier layer with a thickness of 25 nm and an Al composition of 25%. The fluxes of the Ga, Al, and N sources can be 258 μmol / min, 62.5 μmol / min, and 890 mmol / min, respectively. A heterojunction structure is formed between the channel layer and the barrier layer, creating a two-dimensional electron gas channel.

[0117] S406. Prepare the cap layer, which is located on the side of the barrier layer away from the substrate.

[0118] Specifically, after the barrier layer is fabricated, the Al source is turned off while the Ga and N sources are kept flowing, and a 5nm thick cap layer is grown under the same conditions. After the cap layer growth is complete, the Ga source is turned off while NH3 is kept flowing, and the temperature is lowered in an NH3 atmosphere. The main function of the cap layer is to reduce surface states, reduce surface leakage current in subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure and the semiconductor device.

[0119] The epitaxial structure fabrication method provided in this invention can improve the performance and reliability of the epitaxial structure and semiconductor device by preparing a nucleation layer to bond the semiconductor material layer to be grown next and reduce surface states, and by preparing a capping layer to reduce surface leakage current of the subsequent semiconductor device and suppress current collapse.

[0120] Based on the same inventive concept, this invention also provides a semiconductor device, including the epitaxial structure of the semiconductor device described in this invention embodiment. Specifically, Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 9 As shown, the epitaxial structure also includes a nucleation layer 140 located between the substrate 110 and the buffer structure 120; a channel layer located on the side of the buffer structure 120 away from the substrate 110; a barrier layer 150 located on the side of the channel layer away from the substrate 110, the barrier layer 150 and the channel layer forming a heterojunction structure; and a cap layer located on the side of the barrier layer 150 away from the substrate 110. The semiconductor device also includes:

[0121] The source 210 and drain 230 are located on the side of the barrier layer 150 away from the substrate 110, and the gate 220 is located on the side of the cap layer 160 away from the substrate 110, with the gate 220 located between the source 210 and the drain 230.

[0122] For example, the source 210 and drain 230 form ohmic contacts with the barrier layer 150, respectively; the gate 220 is located between the source 210 and drain 230, and is located on the side of the cap layer 160 away from the substrate 110, and the gate 220 forms a Schottky contact with the cap layer 160.

[0123] The semiconductor device provided in the embodiments of the present invention includes the epitaxial structure in the above embodiments. Therefore, the semiconductor device provided in the embodiments of the present invention also has the beneficial effects described in the above embodiments, which will not be repeated here.

[0124] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An epitaxial structure for a semiconductor device, characterized in that, Includes substrate, buffer structure, and insertion structure; The buffer structure includes at least two buffer layers, and the insertion structure includes at least one insertion layer. The buffer layers and the insertion layers are stacked alternately, and any one of the insertion layers is located between two adjacent buffer layers. At least one of the insertion layers includes a plurality of island structures, and the buffer layer located on the side of the island structure away from the substrate covers the island structure; The buffer layer is made of nitride, and the island structure is formed by the decomposition of the material of the insertion layer at an environment above 800°C; the insertion layer is a nitride comprising at least one of Al atoms, Ga atoms, and In atoms.

2. The epitaxial structure according to claim 1, characterized in that, The insertion structure includes multiple insertion layers; Each of the inserted layers includes a plurality of the island-like structures.

3. The epitaxial structure according to claim 2, characterized in that, The multilayer insertion layer includes a first insertion layer and a second insertion layer, wherein the first insertion layer includes a plurality of first island structures and the second insertion layer includes a plurality of second island structures; Along the thickness direction of the epitaxial structure, there is at least one first island structure overlapping with the gaps of two adjacent second island structures.

4. The epitaxial structure according to claim 1, characterized in that, The atomic ratio 'a' of the In atoms in the insertion layer satisfies 0. <a≤50%。 5. The epitaxial structure according to claim 1, characterized in that, The thickness d1 of the insertion layer satisfies 5nm≤d1≤50nm.

6. The epitaxial structure according to claim 1, characterized in that, The thickness of the buffer structure is d2, and the thickness of the insertion structure is d3; Where 40≤d2 / d3≤400.

7. The epitaxial structure according to claim 1, characterized in that, The epitaxial structure further includes: A nucleation layer is located between the substrate and the buffer structure; The channel layer is located on the side of the buffer structure away from the substrate; A barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure; The cap layer is located on the side of the barrier layer away from the substrate.

8. A method for fabricating an epitaxial structure of a semiconductor device, characterized in that, include: Provide substrate; A buffer structure and an insertion structure are fabricated on one side of the substrate; the buffer structure includes at least two buffer layers, the insertion structure includes at least one insertion layer, the buffer layers and the insertion layers are alternately stacked, and any one of the insertion layers is located between two adjacent buffer layers; the at least one insertion layer includes multiple island-shaped structures, and the buffer layer located on the side of the island-shaped structure away from the substrate covers the island-shaped structure; The buffer layer is made of nitride, and the island structure is formed by the decomposition of the material of the insertion layer at an environment above 800°C; the insertion layer is a nitride comprising at least one of Al atoms, Ga atoms, and In atoms.

9. The preparation method according to claim 8, characterized in that, A buffer structure and an insertion structure are fabricated on one side of the substrate, including: At the first preparation temperature, the IN source is turned on to prepare the insertion layer; After turning off the IN source, the buffer layer is prepared at the second preparation temperature for a preset time; the second preparation temperature is higher than the first preparation temperature.

10. The preparation method according to claim 8, characterized in that, The buffer structure includes multiple buffer layers, and the insertion structure includes multiple insertion layers; A buffer structure and an insertion structure are fabricated on one side of the substrate, including: The buffer layer and the insertion layer are sequentially and alternately fabricated on one side of the substrate.

11. The preparation method according to claim 8, characterized in that, Before preparing the buffer structure, the following steps are also included: A nucleation layer is prepared, wherein the nucleation layer is located between the substrate and the buffer structure; After preparing the buffer structure, the following steps are also included: A channel layer is prepared, wherein the channel layer is located on the side of the buffer structure away from the substrate; A barrier layer is prepared, wherein the barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure; A cap layer is prepared, the cap layer being located on the side of the barrier layer away from the substrate.

12. A semiconductor device, characterized in that, Includes the epitaxial structure as described in any one of claims 1-7; The epitaxial structure further includes a nucleation layer located between the substrate and the buffer structure; a channel layer located on the side of the buffer structure away from the substrate; and a barrier layer located on the side of the channel layer away from the substrate, wherein the barrier layer and the channel layer form a heterojunction structure. A cap layer located on the side of the barrier layer away from the substrate; The semiconductor device further includes: The source and drain are located on the side of the barrier layer away from the substrate, and the gate is located on the side of the cap layer away from the substrate, the gate being located between the source and the drain.

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