Integrated temperature Hall sensor and preparation method thereof

Abstract

The present application proposes an integrated temperature Hall sensor and a preparation method thereof, wherein the integrated temperature Hall sensor comprises: a substrate; a buffer layer and a semiconductor layer sequentially arranged on one side of the substrate; a barrier layer, wherein the barrier layer is arranged on the side of the semiconductor layer away from the buffer layer; an ohmic contact layer, wherein the ohmic contact layer is arranged on the side of the barrier layer away from the semiconductor layer; a first passivation layer, wherein the first passivation layer is arranged on the side of the semiconductor layer away from the buffer layer, wherein the first passivation layer covers the semiconductor layer exposed by the barrier layer, wherein a first via hole is arranged on the first passivation layer, wherein the first via hole exposes a part of the surface of the barrier layer; and a Schottky contact layer, wherein the Schottky contact layer is arranged on the side of the first passivation layer away from the semiconductor layer, wherein the orthographic projection of the first via hole on the substrate is within the range of the orthographic projection of the Schottky contact layer on the substrate. Thus, when the integrated temperature Hall sensor is working, a reverse-biased Schottky diode is formed between the semiconductor layer and the barrier layer, and the microampere-level current generated by the reverse bias can drive the integrated temperature Hall sensor, thereby reducing the power consumption of the integrated temperature Hall sensor. In addition, the ambient temperature can be further monitored by detecting the change of the dark current of the Schottky diode.

Description

Technical Field

[0001] The present application relates to the field of sensors, and in particular, to an integrated temperature Hall sensor and a method for preparing the same. Background Art

[0002] At present, the current sensors used in power grids mainly include current transformers, Hall current sensors, Rogowski coils, magnetoresistive current sensors, etc. Hall current sensors have broad application prospects in power grids, automobiles and other fields due to their advantages of non-contact measurement, wide range, high accuracy, good stability, fast response speed, adaptability to high-frequency currents, and strong anti-interference ability. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] In one aspect of the present invention, an integrated temperature Hall sensor is proposed, comprising: a substrate; a buffer layer and a semiconductor layer sequentially arranged on one side of the substrate; a barrier layer, the barrier layer being arranged on the side of the semiconductor layer away from the buffer layer; an ohmic contact layer, the ohmic contact layer being arranged on the side of the barrier layer away from the semiconductor layer; a first passivation layer, the first passivation layer being arranged on the side of the semiconductor layer away from the buffer layer, the first passivation layer covering the semiconductor layer exposed by the barrier layer, a first via being arranged on the first passivation layer, the first via exposing a portion of the surface of the barrier layer; a Schottky contact layer, the Schottky contact layer being arranged on the side of the barrier layer away from the semiconductor layer, the orthographic projection of the first via on the substrate being within the range of the orthographic projection of the Schottky contact layer on the substrate. Thus, when the integrated temperature Hall sensor is working, a reverse-biased Schottky diode is formed between the semiconductor layer and the barrier layer, and the microampere-level current generated by the reverse bias can drive the integrated temperature Hall sensor, thereby reducing the power consumption of the integrated temperature Hall sensor. In addition, the ambient temperature can be further monitored by detecting the change in the dark current of the Schottky diode.

[0005] According to some embodiments of the present invention, the ohmic contact layer includes a first ohmic contact layer, a second ohmic contact layer and a third ohmic contact layer, the first ohmic contact layer and the second ohmic contact layer are arranged at both ends of the barrier layer along a first direction, the third ohmic contact layer and the Schottky contact layer are arranged at both ends of the barrier layer along a second direction, and the first direction and the second direction intersect.

[0006] According to some embodiments of the present invention, a second via is further provided on the first passivation layer, the second via exposing a portion of the surface of the ohmic contact layer, and the integrated temperature Hall sensor further includes: a metal routing layer, the metal routing layer is provided on a side of the first passivation layer away from the semiconductor layer, and the orthographic projection of the second via on the substrate is within the orthographic projection range of the metal routing layer on the substrate.

[0007] According to some embodiments of the present invention, the integrated temperature Hall sensor also includes: a second passivation layer, the second passivation layer is arranged on a side of the first passivation layer away from the semiconductor layer, a third via and a fourth via are arranged on the second passivation layer, the third via exposes a portion of the surface of the metal routing layer, and the fourth via exposes a portion of the surface of the Schottky contact layer.

[0008] According to some embodiments of the present invention, the barrier layer includes a central region and an extension region, the extension region includes a first region, a second region, a third region and a fourth region, the first ohmic contact layer and the second ohmic contact layer are respectively arranged in the first region and the second region, the third ohmic contact layer is arranged in the third region, and the orthographic projection of the Schottky contact layer on the substrate is located within the orthographic projection range of the fourth region on the substrate.

[0009] According to some embodiments of the present invention, the first area and the second area are symmetrically arranged at two ends of the central area along the first direction, and the third area and the fourth area are symmetrically arranged at two ends of the central area along the second direction.

[0010] According to some embodiments of the present invention, the thickness of the Schottky contact layer is 30 nm-1000 nm.

[0011] According to some embodiments of the present invention, the integrated temperature Hall sensor satisfies at least one of the following conditions: the material forming the buffer layer, the semiconductor layer and the barrier layer includes at least one of gallium nitride, gallium arsenide, silicon carbide, and silicon; the material forming the first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer each independently includes at least one of Ti, Ni, Al, Pt, W, TiN, and Au; the material forming the metal routing layer and the Schottky contact layer each independently includes at least one of Ti, Ni, Pt, Cr, Al, and Au; the material forming the first passivation layer and the second passivation layer each independently includes at least one of silicon dioxide, silicon nitride, or aluminum oxide.

[0012] In another aspect of the present invention, a method for preparing the aforementioned integrated temperature Hall sensor is proposed, comprising: forming a buffer layer and a semiconductor layer in sequence on one side of a substrate; forming a barrier layer on the side of the semiconductor layer away from the buffer layer; forming an ohmic contact layer on the side of the barrier layer away from the semiconductor layer; forming a first passivation layer on the side of the barrier layer away from the buffer layer, the first passivation layer covers the semiconductor layer exposed by the barrier layer, a first via is provided on the first passivation layer, the first via exposes part of the surface of the barrier layer; forming a Schottky contact layer on the side of the barrier layer away from the semiconductor layer, the orthographic projection of the first via on the substrate is within the range of the orthographic projection of the Schottky contact layer on the substrate. Thus, the integrated temperature Hall sensor prepared by the method can be directly driven by the microampere level current generated by the reverse bias of the Schottky diode to read the Hall voltage, thereby reducing the power consumption of the integrated temperature Hall sensor.

[0013] According to some embodiments of the present invention, the method of forming the ohmic contact layer includes: forming a first metal layer on a side of the barrier layer away from the semiconductor layer and performing a first patterning and annealing to form the ohmic contact layer.

[0014] According to some embodiments of the present invention, the method of forming the Schottky contact layer includes: forming a second metal layer on a side of the barrier layer away from the semiconductor layer, and performing a second patterning to form the Schottky contact layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0016] Figure 1 A schematic diagram of the structure of an integrated temperature Hall sensor according to an embodiment of the present invention is shown.

[0017] Figure 2 A schematic structural diagram of an ohmic contact layer and a Schottky contact layer according to an embodiment of the present invention is shown.

[0018] Figure 3 A schematic structural diagram of an ohmic contact layer and a Schottky contact layer according to another embodiment of the present invention is shown.

[0019] Figure 4 A schematic structural diagram of an ohmic contact layer and a Schottky contact layer according to another embodiment of the present invention is shown.

[0020] Figure 5 A schematic structural diagram of an ohmic contact layer and a Schottky contact layer according to another embodiment of the present invention is shown.

[0021] Figure 6 A schematic structural diagram of an ohmic contact layer and a Schottky contact layer according to another embodiment of the present invention is shown.

[0022] Figure 7 A schematic diagram of a process for preparing an integrated temperature Hall sensor according to an embodiment of the present invention is shown.

[0023] Reference numerals:

[0024] 1: integrated temperature Hall sensor; 11: substrate; 12: buffer layer; 13: semiconductor layer; 14': barrier layer pre-treatment layer; 14: barrier layer; 140: central area; 141: first area; 142: second area; 143: third area; 144: fourth area; 15: ohmic contact layer; 151: first ohmic contact layer; 152: second ohmic contact layer; 153: third ohmic contact layer; 16: first passivation layer; 161: first via; 162: second via; 171: Schottky contact layer; 172: metal routing layer; 18: second passivation layer; 181: third via; 182: fourth via; F1: first direction; F2: second direction. DETAILED DESCRIPTION

[0025] The embodiments of the present invention are described in detail below. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. If no specific techniques or conditions are specified in the embodiments, the techniques or conditions described in the literature in this area or the product specifications are used. The reagents or instruments used that do not specify the manufacturer are all conventional products that can be obtained commercially.

[0026] In one aspect of the present invention, an integrated temperature Hall sensor 1 is provided, referring to Figure 1 The integrated temperature Hall sensor 1 includes: a substrate 11; a buffer layer 12 and a semiconductor layer 13 sequentially arranged on one side of the substrate 11; a barrier layer 14, wherein the barrier layer 14 is arranged on a side of the semiconductor layer 13 away from the buffer layer 12; an ohmic contact layer 15, wherein the ohmic contact layer 15 is arranged on a side of the barrier layer 14 away from the semiconductor layer 13; a first passivation layer 16, wherein the first passivation layer 16 is arranged on a side of the semiconductor layer 13 away from the buffer layer 12, wherein the first passivation layer 16 covers the semiconductor layer 13 exposed by the barrier layer 14, wherein a first via hole is arranged on the first passivation layer 16, wherein the first via hole exposes a portion of the surface of the barrier layer 14; and a Schottky contact layer 171, wherein the Schottky contact layer 171 is arranged on a side of the barrier layer 14 away from the semiconductor layer 13, wherein the orthographic projection of the first via hole on the substrate 11 is within the range of the orthographic projection of the Schottky contact layer 171 on the substrate 11.

[0027] Specifically, refer to Figure 1 The integrated temperature Hall sensor 1 comprises: a substrate 11; a buffer layer 12, the buffer layer 12 being arranged on one surface of the substrate 11; a semiconductor layer 13, the semiconductor layer 13 being arranged on a surface of the buffer layer 12 away from the substrate 11; a barrier layer 14, the barrier layer 14 being arranged on a surface of the semiconductor layer 13 away from the buffer layer 12; an ohmic contact layer 15, the ohmic contact layer 15 being arranged on a surface of the barrier layer 14 away from the semiconductor layer 13; a first passivation layer 16, the first passivation layer 16 being arranged On the side of the semiconductor layer 13 away from the buffer layer 12, the first passivation layer 16 covers the semiconductor layer 13 exposed by the barrier layer 14, and a first via is arranged on the first passivation layer 16, and the first via exposes a portion of the surface of the barrier layer 14; the Schottky contact layer 171 is arranged on the surface of the barrier layer 14 away from the semiconductor layer 13, and the orthographic projection of the first via on the substrate 11 is located within the range of the orthographic projection of the Schottky contact layer 171 on the substrate 11.

[0028] The integrated temperature Hall sensor 1 proposed by the present invention, when the semiconductor is in the on state and is subjected to an external magnetic field, the electrons will be subjected to the Lorentz force and move to the side of the semiconductor channel perpendicular to the current direction, thereby generating a potential difference between the two ends perpendicular to the current direction. The magnitude of the magnetic field can be inferred by collecting this potential difference. When the integrated temperature Hall sensor 1 is working, a reverse-biased Schottky diode is formed between the semiconductor layer 13 and the barrier layer 14. The micro-ampere level current generated by the reverse bias can drive the integrated temperature Hall sensor 1, thereby reducing the power consumption of the integrated temperature Hall sensor 1. In addition, when the temperature rises, the concentration of the two-dimensional electron gas in the Schottky diode increases, and the threshold voltage of the Schottky diode decreases. Therefore, the dark current of the Schottky diode increases. By detecting the change of the dark current, the ambient temperature can be further monitored.

[0029] According to some embodiments of the present invention, the material forming the buffer layer 12 , the semiconductor layer 13 , and the barrier layer 14 includes at least one of gallium nitride, gallium arsenide, silicon carbide, and silicon.

[0030] According to some embodiments of the present invention, the material forming the buffer layer 12 , the semiconductor layer 13 and the barrier layer 14 includes gallium nitride.

[0031] According to some embodiments of the present invention, the ohmic contact layer 15 includes a first ohmic contact layer 151, a second ohmic contact layer 152 and a third ohmic contact layer 153, the first ohmic contact layer 151 and the second ohmic contact layer 152 are arranged at both ends of the barrier layer 14 along the first direction F1, the third ohmic contact layer 153 and the Schottky contact layer 171 are arranged at both ends of the barrier layer 14 along the second direction F2, and the first direction F1 and the second direction F2 intersect.

[0032] Specifically, the shape of the barrier layer 14 is not particularly limited, and those skilled in the art can design it as needed. Figure 2 Taking the barrier layer 14 as a square as an example, the first direction F1 and the second direction F2 can be the extension directions of the side length of the square respectively, the first direction F1 and the second direction F2 are perpendicular, the first ohmic contact layer 151 and the second ohmic contact layer 152 are arranged at both ends of the barrier layer 14 along the first direction F1, the third ohmic contact layer 153 and the Schottky contact layer 171 are arranged at both ends of the barrier layer 14 along the second direction F2, wherein the first ohmic contact layer 151, the second ohmic contact layer 152 and the third ohmic contact layer 153 are all directly arranged on the surface of the barrier layer 14, a first passivation layer 16 is arranged between the Schottky contact layer 171 and the barrier layer 14, and the Schottky contact layer 171 is in contact with the barrier layer 14 through the first via hole.

[0033] refer to Figure 3 Taking the barrier layer 14 as a square as an example, the first direction F1 and the second direction F2 can be the extension directions of the two diagonals of the square respectively, the first direction F1 and the second direction F2 are perpendicular, the first ohmic contact layer 151 and the second ohmic contact layer 152 are arranged at the two ends of the barrier layer 14 along the first direction F1, the third ohmic contact layer 153 and the Schottky contact layer 171 are arranged at the two ends of the barrier layer 14 along the second direction F2, wherein the first ohmic contact layer 151, the second ohmic contact layer 152 and the third ohmic contact layer 153 are all directly arranged on the surface of the barrier layer 14, a first passivation layer 16 is arranged between the Schottky contact layer 171 and the barrier layer 14, and the Schottky contact layer 171 is in contact with the barrier layer 14 through the first via hole.

[0034] According to some embodiments of the present invention, reference Figure 1, a second via is also provided on the first passivation layer 16, and the second via exposes a portion of the surface of the ohmic contact layer 15; the integrated temperature Hall sensor 1 also includes: a metal wiring layer 172, and the metal wiring layer 172 is arranged on a side of the first passivation layer 16 away from the semiconductor layer 13, and the orthographic projection of the second via on the substrate 11 is located within the orthographic projection range of the metal wiring layer 172 on the substrate 11.

[0035] Specifically, the ohmic contact layer 15 includes the first ohmic contact layer 151, the second ohmic contact layer 152 and the third ohmic contact layer 153. A plurality of second vias are arranged on the first passivation layer 16. The plurality of second vias correspond to the first ohmic contact layer 151, the second ohmic contact layer 152 and the third ohmic contact layer 153 one by one, respectively. The second vias arranged corresponding to the first ohmic contact layer 151 expose a portion of the surface of the first ohmic contact layer 151, the second vias arranged corresponding to the second ohmic contact layer 152 expose a portion of the surface of the second ohmic contact layer 152, and the second vias arranged corresponding to the third ohmic contact layer 153 expose a portion of the surface of the third ohmic contact layer 153. The metal routing layer 172 includes a first metal routing layer, a second metal routing layer and a third metal routing layer. The first metal routing layer is arranged on the surface of the first passivation layer 16 away from the semiconductor layer 13 and contacts the first ohmic contact layer 151 through a second via. The second metal routing layer is arranged on the surface of the first passivation layer 16 away from the semiconductor layer 13 and contacts the second ohmic contact layer 152 through a second via. The third metal routing layer is arranged on the surface of the first passivation layer 16 away from the semiconductor layer 13 and contacts the third ohmic contact layer 153 through a second via.

[0036] According to some embodiments of the present invention, reference Figure 1 The integrated temperature Hall sensor 1 may further include: a second passivation layer 18, the second passivation layer 18 is arranged on a side of the first passivation layer 16 away from the semiconductor layer 13, and a third via 181 and a fourth via 182 are arranged on the second passivation layer 18, the third via 181 exposes a portion of the surface of the metal wiring layer 172, and the fourth via 182 exposes a portion of the surface of the Schottky contact layer 171.

[0037] Specifically, a plurality of third vias 181 are arranged on the second passivation layer 18, and the plurality of third vias 181 correspond to the first metal routing layer, the second metal routing layer and the third metal routing layer one by one, respectively. The third vias 181 arranged corresponding to the first metal routing layer expose a portion of the surface of the first metal routing layer, the third vias 181 arranged corresponding to the second metal routing layer expose a portion of the surface of the second metal routing layer, and the third vias 181 arranged corresponding to the third metal routing layer expose a portion of the surface of the third metal routing layer.

[0038] According to some embodiments of the present invention, reference Figure 2-Figure 4 , the barrier layer 14 may be square.

[0039] According to other embodiments of the present invention, Figure 4 and Figure 5 The barrier layer 14 may be square, and a first groove and a second groove are formed at two ends of the barrier layer 14 along the first direction F1, respectively. The first ohmic contact layer 151 is arranged corresponding to the first groove, and the second ohmic contact layer 152 is arranged corresponding to the second groove.

[0040] According to some embodiments of the present invention, reference Figure 6 The barrier layer 14 includes a central area 140 and an extension area, the extension area includes a first area 141, a second area 142, a third area 143 and a fourth area 144, the first ohmic contact layer 151 and the second ohmic contact layer 152 are respectively arranged in the first area 141 and the second area 142, the third ohmic contact layer 153 is arranged in the third area 143, and the orthographic projection of the Schottky contact layer 171 on the substrate 11 is located within the orthographic projection range of the fourth area 144 on the substrate 11.

[0041] Specifically, refer to Figure 6, with the central area 140 as the center, the first area 141 and the second area 142 are arranged at the two ends of the barrier layer 14 along the first direction F1, the third area 143 and the fourth area 144 are arranged at the two ends of the barrier layer 14 along the second direction F2, the first ohmic contact layer 151 is arranged in the first area 141, the second ohmic contact layer 152 is arranged in the second area 142, the third ohmic contact layer 153 is arranged in the third area 143, and the Schottky contact layer 171 is arranged in the fourth area 144, wherein the first ohmic contact layer 151, the second ohmic contact layer 152 and the third ohmic contact layer 153 are directly arranged on the surface of the barrier layer 14, and the Schottky contact layer 171 is arranged on the side of the first passivation layer 16 away from the semiconductor layer 13 and contacts the barrier layer 14 through the first via hole.

[0042] According to some embodiments of the present invention, reference Figure 6 , the first region 141 and the second region 142 are symmetrically arranged at both ends of the central region 140 along the first direction F1, and the third region 143 and the fourth region 144 are symmetrically arranged at both ends of the central region 140 along the second direction F2. Specifically, the first ohmic contact layer 151 is arranged in the first region 141, the second ohmic contact layer 152 is arranged in the second region 142, and the first ohmic contact layer 151 and the second ohmic contact layer 152 are symmetrically arranged; the third ohmic contact layer 153 is arranged in the third region 143, the Schottky contact layer 171 is arranged in the fourth region 144, and the third ohmic contact layer 153 and the Schottky contact layer 171 are symmetrically arranged.

[0043] According to some embodiments of the present invention, the thickness of the Schottky contact layer 171 is 30nm-1000nm. For example, it can be 30nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm or 1000nm, or it can be a range composed of any of the above values. According to some embodiments of the present invention, the thickness of the Schottky contact layer 171 can be 150nm-300nm.

[0044] According to some embodiments of the present invention, the materials forming the first ohmic contact layer 151 , the second ohmic contact layer 152 , and the third ohmic contact layer 153 respectively and independently include at least one of Ti, Ni, Al, Pt, W, TiN, and Au.

[0045] According to some embodiments of the present invention, the materials forming the metal wiring layer and the Schottky contact layer 171 independently include at least one of Ti, Ni, Pt, Cr, Al, and Au.

[0046] According to some embodiments of the present invention, the materials forming the first passivation layer 16 and the second passivation layer 18 respectively and independently include at least one of silicon dioxide, silicon nitride or aluminum oxide.

[0047] In another aspect of the present invention, reference Figure 7 , a method for preparing the above-mentioned integrated temperature Hall sensor 1 is proposed, comprising: forming a buffer layer 12 and a semiconductor layer 13 in sequence on one side of a substrate 11; forming a barrier layer 14 on a side of the semiconductor layer 13 away from the buffer layer 12; forming an ohmic contact layer 15 on a side of the barrier layer 14 away from the semiconductor layer 13; forming a first passivation layer 16 on a side of the semiconductor layer 13 away from the buffer layer 12, the first passivation layer 16 covers the semiconductor layer 13 exposed by the barrier layer 14, and a first via 161 is provided on the first passivation layer 16, and the first via 161 exposes a part of the surface of the barrier layer 14; forming a Schottky contact layer 171 on a side of the barrier layer 14 away from the semiconductor layer 13, and the orthographic projection of the first via 161 on the substrate 11 is located within the range of the orthographic projection of the Schottky contact layer 171 on the substrate 11. Therefore, the integrated temperature Hall sensor 1 prepared by the method can be directly driven by the microampere level current generated by the reverse bias of the Schottky diode to read the Hall voltage, thereby reducing the power consumption of the integrated temperature Hall sensor 1.

[0048] According to some embodiments of the present invention, reference Figure 7 The method for preparing the integrated temperature Hall sensor 1 may include:

[0049] A buffer layer 12 is formed on one surface of the substrate 11. Specifically, the method for forming the buffer layer 12 may refer to conventional processes in the art and is not particularly limited herein.

[0050] A semiconductor layer 13 is formed on a surface of the buffer layer 12 away from the substrate 11. Specifically, the method for forming the semiconductor layer 13 may refer to conventional processes in the art and is not particularly limited herein.

[0051] A barrier layer pre-treatment layer 14 ′ is formed on a surface of the semiconductor layer 13 away from the buffer layer 12 , and the barrier layer pre-treatment layer 14 ′ is etched to form a patterned barrier layer 14 .

[0052] An ohmic contact layer is formed on the surface of the barrier layer 14 away from the semiconductor layer 13. According to some embodiments of the present invention, the method of forming the ohmic contact layer 15 includes: forming a first metal layer on a side of the barrier layer 14 away from the semiconductor layer 13 and performing a first patterning and annealing to form the ohmic contact layer 15. Specifically, after the first metal layer is formed, a first patterning and annealing can be performed by an etching process or a metal lift-off process to form a first ohmic contact layer 151, a second ohmic contact layer 152 and a third ohmic contact layer 153.

[0053] A first passivation layer 16 having a first via hole 161 and a second via hole is formed on a side of the semiconductor layer away from the buffer layer. It should be noted that the method for forming the first passivation layer 16 may refer to conventional methods in the art and is not limited here.

[0054] A Schottky contact layer 171 is formed on a side of the first passivation layer 16 away from the semiconductor layer 13. According to some embodiments of the present invention, a method for forming the Schottky contact layer 171 includes: forming a second metal layer on a side of the barrier layer 14 away from the semiconductor layer 13, and performing a second patterning to form the Schottky contact layer 171. Specifically, after the second metal layer is formed, a second patterning may be performed by an etching process or a metal lift-off process to form the Schottky contact layer 171. When the Schottky contact layer 171 and the metal wiring layer 172 are formed by a single process, the method for forming the Schottky contact layer 171 and the metal wiring layer 172 includes: forming a second metal layer on a side of the barrier layer 14 away from the semiconductor layer 13, and performing a second patterning to simultaneously form the Schottky contact layer 171 and the metal wiring layer 172. Specifically, after the second metal layer is formed, a second patterning may be performed by an etching process or a metal lift-off process to form the Schottky contact layer 171 and the metal wiring layer 172.

[0055] A second passivation layer 18 having a third via hole 181 and a fourth via hole 182 is formed on a side of the first passivation layer 16 away from the semiconductor layer 13. Specifically, the specific method for forming the second passivation layer 18 can refer to conventional processes in the art and is not limited here.

[0056] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0058] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0061] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An integrated temperature Hall sensor, characterized in that: include: substrate; A buffer layer and a semiconductor layer are sequentially arranged on one side of the substrate; A barrier layer, wherein the barrier layer is arranged on a side of the semiconductor layer away from the buffer layer; an ohmic contact layer, wherein the ohmic contact layer is arranged on a side of the barrier layer away from the semiconductor layer, a first passivation layer, the first passivation layer being arranged on a side of the semiconductor layer away from the buffer layer, the first passivation layer covering the semiconductor layer exposed by the barrier layer, the first via hole being arranged on the first passivation layer, the first via hole exposing a portion of the surface of the barrier layer; A Schottky contact layer, wherein the Schottky contact layer is arranged on a side of the first passivation layer away from the semiconductor layer, and an orthographic projection of the first via hole on the substrate is located within a range of an orthographic projection of the Schottky contact layer on the substrate; Among them, the ohmic contact layer includes a first ohmic contact layer, a second ohmic contact layer and a third ohmic contact layer, the first ohmic contact layer and the second ohmic contact layer are arranged at both ends of the barrier layer along a first direction, the third ohmic contact layer and the Schottky contact layer are arranged at both ends of the barrier layer along a second direction, and the first direction and the second direction intersect.

2. The integrated temperature Hall sensor according to claim 1, characterized in that: A second via hole is also provided on the first passivation layer, and the second via hole exposes a portion of the surface of the ohmic contact layer; The integrated temperature Hall sensor further includes: a metal wiring layer, which is arranged on a side of the first passivation layer away from the semiconductor layer, and the orthographic projection of the second via on the substrate is located within the orthographic projection range of the metal wiring layer on the substrate.

3. The integrated temperature Hall sensor according to claim 2, characterized in that: Also includes: A second passivation layer, wherein the second passivation layer is arranged on a side of the first passivation layer away from the semiconductor layer, and a third via and a fourth via are arranged on the second passivation layer, wherein the third via exposes a portion of the surface of the metal wiring layer, and the fourth via exposes a portion of the surface of the Schottky contact layer.

4. The integrated temperature Hall sensor according to any one of claims 1 to 3, characterized in that: The barrier layer includes a central area and an extended area, the extended area includes a first area, a second area, a third area and a fourth area, the first ohmic contact layer and the second ohmic contact layer are respectively arranged in the first area and the second area, the third ohmic contact layer is arranged in the third area, and the orthographic projection of the Schottky contact layer on the substrate is located within the orthographic projection range of the fourth area on the substrate.

5. The integrated temperature Hall sensor according to claim 4, characterized in that: The first area and the second area are symmetrically arranged at two ends of the central area along the first direction, and the third area and the fourth area are symmetrically arranged at two ends of the central area along the second direction.

6. The integrated temperature Hall sensor according to claim 1, characterized in that: The thickness of the Schottky contact layer is 30nm-1000nm.

7. The integrated temperature Hall sensor according to claim 3, characterized in that: Satisfy at least one of the following conditions: The material forming the buffer layer, the semiconductor layer and the barrier layer includes at least one of gallium nitride, gallium arsenide, silicon carbide and silicon; The materials forming the first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer independently include at least one of Ti, Ni, Al, Pt, W, TiN and Au; The materials forming the metal wiring layer and the Schottky contact layer independently include at least one of Ti, Ni, Pt, Cr, Al, and Au; The materials forming the first passivation layer and the second passivation layer independently include at least one of silicon dioxide, silicon nitride, or aluminum oxide.

8. A method for preparing the integrated temperature Hall sensor according to any one of claims 1 to 7, characterized in that: include: forming a buffer layer and a semiconductor layer in sequence on one side of the substrate; forming a barrier layer on a side of the semiconductor layer away from the buffer layer; An ohmic contact layer is formed on a side of the barrier layer away from the semiconductor layer, the ohmic contact layer includes a first ohmic contact layer, a second ohmic contact layer and a third ohmic contact layer, the first ohmic contact layer and the second ohmic contact layer are arranged at two ends of the barrier layer along a first direction, the third ohmic contact layer and the Schottky contact layer are arranged at two ends of the barrier layer along a second direction, and the first direction and the second direction intersect; forming a first passivation layer on a side of the semiconductor layer away from the buffer layer, the first passivation layer covering the semiconductor layer exposed by the barrier layer, and a first via hole being provided on the first passivation layer, the first via hole exposing a portion of the surface of the barrier layer; A Schottky contact layer is formed on a side of the barrier layer away from the semiconductor layer, and an orthographic projection of the first via hole on the substrate is located within the range of an orthographic projection of the Schottky contact layer on the substrate.

9. The method according to claim 8, characterized in that The method of forming the ohmic contact layer includes: A first metal layer is formed on a side of the barrier layer away from the semiconductor layer, and is patterned for the first time and annealed to form the ohmic contact layer.

10. The method according to claim 9, characterized in that The method of forming the Schottky contact layer includes: A second metal layer is formed on a side of the barrier layer away from the semiconductor layer, and a second patterning is performed to form the Schottky contact layer.

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