Image sensor with data converter including low-noise comparator

Abstract

This disclosure relates to an image sensor having a data converter including a low-noise comparator. The invention provides an image sensor that may include an array of imaging pixels arranged in rows and columns. Each column of pixels may be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC may include a first low-noise single-ended comparator stage, a second low-noise single-ended comparator stage, latching circuitry, and a counter. The first low-noise single-ended comparator stage may include one or more current source transistors, a voltage ramp generator, a common-source amplifier transistor, one or more auto-zeroing components, one or more capacitors (e.g., noise filter capacitors), and voltage clamping circuitry. The voltage ramp generator may output a rising ramp voltage or a falling ramp voltage.

Description

Technical Field

[0001] The present invention relates generally to imaging systems, and more specifically, to image sensors having analog-to-digital converters. Background Technology

[0002] An image sensor includes active image sensor pixels that generate an image signal in response to incident light and readout circuitry for reading the image signal from the active image sensor pixels. This readout circuitry typically includes an analog-to-digital converter to convert the analog signal output from the image sensor pixels into corresponding digital data.

[0003] Sometimes, a ramp analog-to-digital converter (ADC) can be used to implement the readout circuit. Designing a ramp ADC for an image sensor can be challenging. Image sensors employing a ramp ADC architecture can achieve high bit resolution but require a high-speed clock. Conventional ramp ADCs include differential comparators, which result in high noise levels and increased power consumption. The implementation described in this paper arises in this context. Attached Figure Description

[0004] Figure 1 This is a schematic diagram of an exemplary system with an image sensor according to some implementation schemes.

[0005] Figure 2 This is a schematic diagram of an exemplary pixel array and associated row and column control circuitry for reading signals from a pixel array, according to some implementation schemes.

[0006] Figure 3 This is a schematic diagram of a column of image sensor pixels coupled to an exemplary column analog-to-digital converter (ADC) circuit according to some implementation schemes.

[0007] Figure 4 This is a circuit diagram of an exemplary low-noise single-ended comparator stage based on some implementation schemes.

[0008] Figure 5 This illustrates the use of a voltage ramp according to some implementation schemes. Figures 2 to 4 The timing diagram shows the operation of the analog-to-digital converter of the type shown.

[0009] Figure 6 This illustrates the use of a rising voltage ramp according to some implementation schemes. Figures 2 to 4 The timing diagram shows the operation of the analog-to-digital converter of the type shown. Detailed Implementation

[0010] Embodiments of the present invention relate to image sensors. Those skilled in the art will understand that exemplary embodiments of the invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0011] Electronic devices such as digital cameras, computers, cellular phones, and other electronic devices may include image sensors that collect incoming light to capture images. The image sensor may include an array of pixels, sometimes referred to as image sensor pixels or imaging pixels. The image sensor includes photosensitive elements, such as photodiodes, that convert incoming light into image signals. An image sensor may include hundreds, thousands, or millions of imaging pixels. The image sensor may include control circuitry (e.g., driver circuitry for selectively accessing pixels) and readout circuitry for reading out image signals corresponding to the charges generated by the photosensitive elements.

[0012] Figure 1 This is a diagram of an exemplary imaging and response system, which includes an imaging system that captures images using an image sensor. Figure 1 The system 100 may be an electronic device, such as a camera, cellular phone, video camera or other electronic device that captures digital image data, may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or may be a surveillance system.

[0013] like Figure 1 As shown, system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include a camera, such as camera module 12. Camera module 12 may include one or more image sensors 14, such as those in an image sensor array integrated circuit, and one or more lenses. During image capture operation, each lens may focus light onto the associated image sensor 14. Image sensor 14 is sometimes referred to as an optical sensor. Image sensor 14 may include photosensitive elements (e.g., image sensor pixels) that convert incoming light into digital data. Image sensor 14 may include hundreds of pixels, thousands of pixels, millions of pixels, or any desired number of pixels.

[0014] Each image sensor in camera module 12 may be identical, or different types of image sensors may exist in a given image sensor array integrated circuit. In some examples, image sensor 14 may also include bias circuitry, sample-and-hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory, buffer circuitry, and / or addressing circuitry.

[0015] Still and video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, or face detection. Image processing and data formatting circuitry 16 can additionally or alternatively be used to compress raw camera image files when needed (e.g., compressing to Joint Photographic Experts Group or JPEG format).

[0016] In one exemplary arrangement, such as a system-on-a-chip (SoC) arrangement, sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, sensor 14 and image processing circuitry 16 may be formed on separate semiconductor substrates. For example, sensor 14 and image processing circuitry 16 may be formed on separate substrates stacked perpendicularly to each other.

[0017] Imaging system 10 can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include input-output device 22 and storage and processing circuitry 24. Host subsystem 20 may include processing software for detecting objects in the image, detecting motion of objects between image frames, determining distances to objects in the image, or filtering or otherwise processing the image provided by imaging system 10. For example, image processing and data formatting circuitry 16 of imaging system 10 can transmit acquired image data to storage and processing circuitry 24 of host subsystem 20.

[0018] If needed, system 100 can provide users with many advanced functions. For example, in a computer or mobile phone, it can provide users with the ability to run user applications. For these functions, the input-output devices 22 of the host subsystem 20 may include a keyboard, input-output ports, buttons, a display, and storage and processing circuitry 24. The storage and processing circuitry 24 of the host subsystem 20 may include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, etc.). The storage and processing circuitry 24 may additionally or alternatively include a microprocessor, microcontroller, digital signal processor, and / or application-specific integrated circuit.

[0019] Figure 2 It shows Figure 1 An example of the arrangement of the image sensor 14. For example... Figure 2 As shown, the image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44 (sometimes referred to as control and processing logic) may be... Figure 1The image processing and data formatting circuitry 16 may be part of, or separate from, the image sensor 14. The image sensor 14 may include a pixel array, such as an array 32 of pixels 34. Pixels 34 are sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels. The control and processing circuitry 44 may be coupled to the row control circuitry 40 via control path 27 and to the column control and readout circuitry 42 via data path 26.

[0020] The line control circuit 40 can receive a line address from the control and processing circuit 44 and can provide the corresponding line control signal to the image pixel 34 through one or more control paths 36. The line control signal may include a pixel reset control signal, a charge transfer control signal, an overflow control signal, a line selection control signal, a double conversion gain control signal, or any other desired pixel control signal.

[0021] Column control and readout circuitry 42 may be coupled to one or more columns of pixel array 32 via one or more wires (such as column lines 38). A given column line 38 may be coupled to a column of image pixels 34 in image pixel array 32 and may be used to read image signals from image pixels 34 and to provide bias signals (e.g., bias current or bias voltage) to image pixels 34. In some examples, each pixel column may be coupled to a corresponding column line 38.

[0022] For image pixel readout operations, row driver circuit 40 can be used to select pixel rows in image pixel array 32, and image data associated with image pixels 34 of that pixel row can be read out on column line 38 by column readout circuit 42. Column readout circuit 42 may include column circuitry, such as column amplifiers for amplifying signals read from array 32, sample-and-hold circuitry for sampling and storing signals read from array 32, analog-to-digital converter circuitry for converting readout analog signals into corresponding digital signals, and / or column memory for storing readout signals and any other desired data. Column control and readout circuit 42 can output digital pixel readout values ​​to control and processing logic unit 44 via line 26.

[0023] The pixel array 32 may have any number of rows and columns. Generally, the size of the image pixel array 32 and the number of rows and columns in the array 32 will depend on the specific implementation of the image sensor 14. Although rows and columns are generally described herein as horizontal and vertical, respectively, the terms row and column are used interchangeably and can refer to any grid-like structure. Features described herein as "rows" may be arranged vertically, and features described herein as "columns" may be arranged horizontally.

[0024] Pixel array 32 may include a color filter array with multiple color filter elements, which allows a single image sensor to sample different colors of light. For example, image sensor pixels (such as image pixels in array 32) may include a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. As an example, red, green, and blue image sensor pixels may be arranged in a Bayer mosaic pattern. A Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. Alternatively, wideband image pixels with wideband color filter elements (e.g., transparent color filter elements, yellow color filter elements, etc.) may be used instead of green pixels in a Bayer pattern. These examples are merely illustrative, and in general, color filter elements of any desired color and any desired pattern can be formed over any desired number of image pixels 34.

[0025] Figure 3 This is a schematic diagram of a series of image sensor pixels coupled to an exemplary analog-to-digital converter (ADC) circuit 50 according to some implementation schemes. The ADC 50 can represent... Figure 2 A data converter within the column readout circuit 42. For example... Figure 3 As shown, an image sensor pixel, such as pixel 34, may include a photosensitive element such as a photodiode PD and a charge transfer transistor such as a charge transfer transistor T1. The charge transfer transistor has a first source-drain terminal coupled to the photodiode PD, a second source-drain terminal coupled to a floating diffusion node FD, and a gate terminal configured to receive a charge transfer control signal TX. The charge transfer transistor T1 is sometimes referred to as the charge transfer gate. The floating diffusion node FD is sometimes referred to as the floating diffusion region.

[0026] Pixel 34 may also include a reset transistor T2 having a drain terminal coupled to a positive power supply line (e.g., a power supply terminal on which a positive power supply voltage VDD is provided), a source terminal coupled to a floating diffusion node FD, and a gate terminal configured to receive a reset control signal RST. When referring to the current-conducting terminals of a metal-oxide-semiconductor transistor, the terms "source" terminal and "drain" terminal are used interchangeably and are sometimes referred to as "source-drain" terminals. For example, the drain terminal of reset transistor T2 may be referred to as its first source-drain terminal, and the source terminal of reset transistor T2 may be referred to as its second source-drain terminal, or vice versa.

[0027] Pixel 34 may also include a source follower transistor T3, which has a drain terminal coupled to a positive power supply line, a gate terminal coupled to a floating diffusion node FD, and a source terminal. The source follower transistor T3 is sometimes simply referred to as a "source follower". Pixel 34 may also include a row select transistor T4, which has a drain terminal coupled to the source terminal of the source follower T3, a gate terminal configured to receive a row select control signal RS, and a source terminal coupled to the corresponding column line 38. Figure 3 In the example, transistors T1-T4 may all be n-type metal-oxide-semiconductor (NMOS) transistors. In other embodiments, at least some transistors T1-T4 may alternatively be implemented as p-type metal-oxide-semiconductor (PMOS) transistors. In other embodiments, pixel 34 may optionally include four or more n-channel and / or p-channel transistors. Although Figure 3 Only one pixel 34 is shown, but any number of pixels 34 can be coupled to column lines 38 for readout. For example, column lines 38 can be coupled to more than 10 pixels in a pixel column, 10-100 pixels in a column, hundreds of pixels in a column, or thousands of pixels in a column. Column lines 38 are sometimes called pixel output lines or pixel output column lines.

[0028] Pixel 34 includes four transistors T1-T4. Figure 3 The examples provided are merely illustrative. In other embodiments, pixel 34 may include multiple photodiodes coupled to a shared floating diffusion node, fewer than four transistors, more than four transistors, five or more transistors, six or more transistors, one or more storage capacitors, one or more storage nodes, one or more mode switching transistors, a multi-conversion gain component, a Bloom control component, and / or other pixel structures.

[0029] Pixel output line 38 can be coupled to a corresponding analog-to-digital converter (ADC) circuit 50, which is configured to convert the analog signal read from the selected pixel into its digital equivalent. Pixel output line 38 can also be coupled to a current source 52 configured to absorb a relatively constant amount of current. ADC circuit 50 can be considered as column readout circuit 42 (see...). Figure 2 The analog-to-digital converter (ADC) circuit 50 may include one or more comparator stages (e.g., a first comparator stage 56 and a second comparator stage 58), latch circuitry (e.g., a latch 60), and counter circuitry (e.g., a counter 62). The first comparator stage 56 may be configured to receive a voltage ramp signal Vramp from the voltage generator 54. The ADC circuit 50 that receives the ramp voltage Vramp is sometimes referred to as a ramp analog-to-digital converter.

[0030] The first comparator stage 56 and the second comparator stage 58 can be single-ended voltage comparator circuits. Compared to single-ended voltage comparator circuits, differential voltage comparators include differential input transistors, which typically result in higher noise levels and increased power consumption. Therefore, using single-ended voltage comparator stages in the column ADC 50 is technically advantageous compared to conventional differential comparators, and provides the benefit of reducing power consumption while minimizing the overall noise level of the column ADC 50. Therefore, the first single-ended comparator stage 56 and the second single-ended comparator stage 58 are sometimes collectively referred to as "low-noise" comparator circuits.

[0031] Figure 4 Exemplary details of a first low-noise comparator stage 54 are shown. The first low-noise comparator stage 54 generates an output signal OUT to a second low-noise comparator stage 56. The second comparator stage 58 has a threshold comparison level THRES. The threshold level THRES of the second comparator stage 58 can be fixed to a predetermined or known voltage level, or it can be adjusted. The second low-noise comparator stage 58 can be a single-ended voltage comparator that receives the signal OUT from the first comparator stage 56 and asserts its output when the received OUT signal exceeds THRES. Comparator 58 has an output coupled to latch 60. Latch 60 can be a positive feedback latch (by way of example) configured to provide a clean transition at its output. Latch 60 has an output coupled to an enable input of counter 62. When the output of latch 60 is at a first value, counter 62 is enabled and allowed to continue counting. When the output of latch 60 is at a second value, counter 62 is disabled and counting stops. The final count value output by counter 62 can be a function of the image signal read from the selected pixel 34. Figure 3 The type of ADC circuit 50 shown can be included in any non-sampling ramp ADC design of an image sensor.

[0032] Figure 4 This is a circuit diagram of an exemplary low-noise single-ended comparator stage 56 based on some implementation schemes. For example... Figure 4 As shown, comparator stage 56 can be coupled to transistors N1 and N2 in current source 52. Transistors N1 and N2 can be used as cascaded current source transistors. Current source transistor N1 has a source terminal coupled to a ground line (e.g., a ground power supply line on which a ground power supply voltage is provided), a gate terminal configured to receive a first bias voltage VB1, and a drain terminal. Cascaded current source transistor N2 has a source terminal coupled to the drain terminal of transistor N1, a gate terminal configured to receive a second bias voltage VB2, and a drain terminal coupled to pixel output line 38. Current source transistors N1 and N2 are sometimes considered as part of column ADC circuit 50 or part of first voltage comparator stage 56.

[0033] The first low-noise voltage comparator stage 56 may include transistors N3 and P1, an auto-zero switch Saz, and capacitors C_filter, C1, and C2. Transistor N3 may be an NMOS transistor having a source terminal coupled to the drain terminal of a cascaded current source transistor N2, a drain terminal coupled to the pixel output line 38, and a gate terminal configured to receive a third bias voltage VB3. Transistor N3 may also be considered part of current source 52. The bias voltages VB1, VB2, and VB3 should be selected such that transistor N1 has a drain-to-source voltage (Vds1) greater than the saturation drain voltage Vdsat of N1, and transistor N2 has a drain-to-source voltage (Vds2) greater than the saturation drain voltage Vdsat of N2. The saturation drain voltage Vdsat is defined as the minimum drain-to-source voltage required to keep the transistor in saturation mode. This saturation mode is sometimes referred to as a constant current mode. By maintaining Vds1 and Vds2 of transistors N1 and N2 above their respective Vdsat levels, it is ensured that both current source transistors N1 and N2 operate in constant current saturation mode. For example, Vds1 and Vds2 can be maintained at greater than 50mV, greater than 100mV, 100-200mV, 150-200mV, 175-250mV, greater than 200mV, greater than 250mV, or greater than 300mV. These bias conditions help ensure sufficient voltage swing on pixel output line 38 during dark illumination conditions and during bright charge saturation conditions.

[0034] The node between transistors N2 and N3 is Figure 4 The stage is labeled 66. Transistor P1 may be a PMOS transistor having a source terminal coupled to pixel output line 38, a drain terminal coupled to node 66, and a gate terminal. Capacitor C_filter may have a first terminal coupled to pixel output line 38 and a second terminal coupled to node 66. Arranged in this way, capacitor C_filter can be configured to filter out any broadband and / or thermal noise associated with transistor P1. Capacitor C_filter can also be used to limit the slewing rate at node 66 by absorbing any transient current flowing to the ramp input via the parasitic capacitance associated with transistor P1, thereby mitigating potential backlash from voltage disturbances at the gate of transistor P1. Capacitor C_filter is optional and may be omitted from stage 56 to help reduce circuit area. The capacitor may be 10fF, 20fF, 10-50fF, 50-100fF, less than 50fF, greater than 100fF, several hundred nanofarads, or other capacitances to provide the desired filtering capability.

[0035] Transistor P1 can be configured to compare the voltage on pixel output line 38 with the Vramp voltage. If transistor P1 is fully open, the output signal OUT at the drain terminal of P1 can be pulled up to a voltage close to that on line 38. If transistor P1 is closed, the output signal OUT can drop to a value approximately equal to [VB3-VGS(N3)], where VGS(N3) represents the gate-to-source voltage on current source transistor N3. The value [VB3-VGS(N3)] is independent of the image signal readout level, so a low-power and low-noise comparator 58 can be used to compare the signal OUT with a threshold level THRES. For example, [VB3-VGS(N3)] can be on the order of approximately 600-700 mV, while the threshold level of comparator 58 can be set to a relatively high voltage level of 800-900 mV. As another example, [VB3-VGS(N3)] can be on the order of approximately 500-600mV, while the threshold level of comparator 58 can be set to a relatively high voltage level of 700-800mV. As another example, [VB3-VGS(N3)] can be on the order of approximately 800-900mV, while the threshold level of comparator 58 can be set to a relatively high voltage level of 1-1.1V. The threshold level THRES should be lower than the minimum voltage of the pixel output line 38 corresponding to the pixel's saturation value under bright light conditions. Transistor P1 operating in this manner is sometimes referred to and defined as a "common-source" amplifier transistor.

[0036] The automatic zero-adjustment switch Saz can be coupled to the gate terminal and drain terminal of transistor P1. Capacitor C1 has a first terminal coupled to the gate of transistor P1 and is configured to operate from voltage generator 54 (see...). Figure 3 The second terminal of capacitor C2 receives the ramp voltage signal Vramp. Capacitor C2 has a first terminal coupled to the gate terminal of transistor P1 and a second terminal coupled to the ground power supply (sometimes referred to as the ground wire or ground). Capacitor C1 can be used as an auto-zero capacitor. The auto-zero switch Saz can be opened when Vramp is set to the middle of the sample-hold reset ramp range, allowing the output signal OUT to trip near that value, regardless of the pixel reset value. Capacitor C2 can be used together with capacitor C1 as a capacitive voltage divider to attenuate the voltage Vramp. Attenuating the signal Vramp in this way is technically advantageous by providing analog gain, which helps suppress ramp and quantization noise in comparator stage 56. Capacitor C2 is optional and can be omitted.

[0037] The first voltage comparator stage 56 may also include clamping circuitry, such as voltage clamping circuitry 64. Clamping circuitry 64 may include a clamping transistor Pclamp and a clamping enable switch Sclamp_en. Clamping transistor Pclamp may be a PMOS transistor having a source terminal coupled to node 66, a gate terminal coupled to a node located between current source transistors N1 and N2, and a drain terminal coupled to ground via switch Sclamp_en. Clamping circuitry 64 can be enabled by making the ramp voltage the same as the voltage value during the auto-zeroing phase and activating switch Sclamp_en at the end of the charge transfer phase to help pull the voltage on pixel output line 38 down to the reset voltage level. If the voltage on pixel output line 38 is lower than the voltage value during the charge transfer phase due to… Figure 3 If the feedthrough from transfer gate T2 to source follower T3 becomes higher than the reset level, this will help the pixel output line stabilize more quickly at the end of the charge transfer phase. The threshold voltage of Pclamp should have a value greater than approximately Vb3-Vb2, so that it closes once the pixel output line 38 drops to the reset voltage level. Clamping circuit 64 is optional and can be omitted.

[0038] Combination Figure 5 and Figure 6 The best way to understand and combine timing diagrams Figures 2 to 4 The operation of the ADC circuit 50 described. Figure 5 This is a timing diagram illustrating the operation of analog-to-digital converter 50 using a falling Vramp. Waveform TX represents the control transistor T1 (see...). Figure 3 The waveform PIXOUT represents the voltage at pixel output column line 38. The waveform AZ represents the signal used to activate the auto-zero switch Saz. The waveform CLAMP_EN represents the signal used to activate the clamp switch Sclamp_en. The waveform Vramp represents the ramp signal output from the ramp generator. The waveform OUT represents the signal at the output of the low-noise single-ended comparator stage 56. The waveform COUNTER_EN represents the signal output by latch 60 for selectively enabling and disabling counter 62. The waveform 78 represents the counter enable signal for low-light conditions, while the waveform 79 can represent the counter enable signal for high-light conditions.

[0039] Before time t1, the auto-zero signal AZ can be activated to disconnect switch Saz. At this time, the Vramp voltage can be set to the auto-zero voltage level VR(AZ), which is less than the maximum Vramp voltage of VR(START). For example, the auto-zero voltage level VR(AZ) can be 100mV less than the maximum ramp start level VR(START). This is merely illustrative. In other embodiments, the auto-zero voltage level VR(AZ) can be 120mV less than VR(START), 150mV less than VR(START), 100-200mV less than VR(START), 50-100mV less than VR(START), 200-250mV less than VR(START), or other suitable voltage levels. At this time, the signal OUT can be pulled up or set to [VPIXOUT-VGS(P1)], where VPIXOUT represents the voltage level at output line 38, and VGS(P1) represents the gate-to-source voltage on transistor P1. Capacitor C1 can also be charged to store the auto-zero value. The period during which the auto-zero switch Saz is off is sometimes referred to as the auto-zero phase.

[0040] At time t1, the auto-zero signal AZ can be deasserted to close switch Saz. At time t2, the Vramp signal can be set to its maximum voltage level VR (START). Raising the Vramp in this way closes transistor P1, which allows current source transistors N1 and N2 to pull the signal OUT down to [VB3-VGS(N3)], where VGS(N3) represents the gate-to-source voltage across transistor N3.

[0041] At time t3, the Vramp signal can begin to slope down. This first voltage ramp used to switch the reset voltage level on pixel output line 38 is sometimes referred to as the SHR (Sample-Hold Reset) ramp. The voltage Vramp will continue to decline, and at time t4, transistor P1 can turn off again. When transistor P1 turns off, the signal OUT will rise above the threshold level THRES of the second comparator stage 58. This will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t4 is therefore a function of the reset signal read from the selected pixel. After time t4, the Vramp signal can continue to decrease until it reaches its first ramp stop voltage level VR (SHR STOP).

[0042] At time t5, the charge transfer control signal TX can be a pulse high level. The period during which the signal TX is valid is sometimes referred to as the charge transfer phase. At this time, the PIXOUT signal can begin to increase, and the Vramp signal can rise back to VR(AZ) (if voltage clamping circuit 64 is present), or it can rise back to VR(START) in other cases. As the signal Vramp increases, transistor P1 will close, thus driving the signal OUT down again to [VB3-VGS(N3)], where VGS(N3) represents the gate-to-source voltage across transistor N3.

[0043] At time t6, the PIXOUT signal can remain high in low light conditions as shown in waveform 70, or it can begin to decrease in high light conditions as shown in waveform 72. At time t6, the counter enable signal COUNTER_EN can be activated to allow counter 62 to start incrementing again, and the Vramp signal can reach VR (AZ) in the presence of clamping circuit 64 (as shown), or it can rise to VR (START) under other conditions. Counter 62 can optionally be reset before time t6 to help distinguish the SHR count value from the SHS (sample and hold) count value. Alternatively, counter 62 can have its bits inverted before time t6 to subtract the SHR count value from the SHS count value.

[0044] At time t7, the charge transfer control signal TX can be deactivated to signal the end of the charge transfer phase. At time t7, as shown in waveforms 70 and 72, the PIXOUT waveform can begin to decline in both low-light and high-light conditions. At time t7, if the clamping circuit 64 is included within the comparator stage 56, the signal CLAMP_EN can be a pulsed high level to temporarily activate the clamping circuit. Disconnecting the clamping circuit 64 can help the PIXOUT voltage stabilize to the actual SHS value more quickly. If the clamping circuit 64 is present, the Vramp signal should rise further to the VR(START) value (see time t8).

[0045] At time t9, the Vramp signal can begin to slope down again. This second voltage ramp used to switch the image signal voltage level on pixel output line 38 is sometimes referred to as the SHS (Sample-Hold Signal) ramp. The voltage Vramp will continue to decline, and at some point, transistor P1 can turn off again. The duration of the time interval between t8 and the time when transistor P1 is activated can depend on the actual signal voltage read from pixel output line 38.

[0046] In a low-light scenario, as shown in waveform 78 (counter enable), transistor P1 can be turned off at time t10. When transistor P1 is turned off at time t10, the signal OUT will rise above the threshold level THRES of the second comparator stage 58, as shown in waveform 74. This will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t9 is therefore a function of the weak signal value read from the selected pixel.

[0047] In the bright light scenario shown in waveform 79, where the counter is enabled, transistor P1 may turn off later at time t11. When transistor P1 turns off at time t11, the signal OUT will rise above the threshold level THRES of the second comparator stage 58, as shown in waveform 76. This will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t11 is therefore a function of the bright signal value read from the selected pixel. After time t11, the Vramp signal may continue to decrease until it reaches its second ramp stop voltage level VR (SHS STOP). The second ramp stop voltage level VR (SHS STOP) may be lower than the first ramp stop voltage level VR (SHR STOP). This is merely illustrative. In other embodiments, the first ramp stop voltage level VR (SHR STOP) may be equal to the second ramp stop voltage level VR (SHS STOP).

[0048] The slope of the first SHR ramp after time t3 can be equal to the slope of the second SHS ramp after time t8. The SHR ramp is sometimes referred to as the ramp voltage used during the SHR transition phase or operation, while the SHS ramp is sometimes referred to as the ramp voltage used during the SHS transition phase or operation. This is exemplary. In some implementations, the slope of the first SHR ramp after time t3 can be different from the slope of the second SHS ramp after time t9. As another example, the slope of the first SHR ramp after time t3 can be greater than the slope of the second SHS ramp after time t9. As yet another example, the slope of the first SHR ramp after time t3 can be less than the slope of the second SHS ramp after time t9.

[0049] Figure 6This is a timing diagram illustrating the operation of analog-to-digital converter 50 using a rising Vramp. The rising Vramp is technically advantageous by allowing the pixel output line to stabilize for a longer time during the SHS ramp under dim or dark lighting conditions. The waveform COUNTER_EN represents the signal output by latch 60 for selectively enabling and disabling counter 62. Waveform 88 represents the counter enable signal for low-light conditions, while waveform 89 could represent the counter enable signal for high-light conditions.

[0050] Before time t1, the auto-zero signal AZ can be activated to disconnect switch Saz. At this time, the Vramp voltage can be set to an auto-zero voltage level VR(AZ) greater than the first ramp-start voltage VR(SHR START). For example, the auto-zero voltage level VR(AZ) can be 100mV greater than the first ramp-start voltage VR(SHR START). This is merely illustrative. In other embodiments, the auto-zero voltage level VR(AZ) can be 120mV greater than VR(SHR START), 150mV greater than VR(SHR START), 100-200mV greater than VR(SHR START), 50-100mV greater than VR(SHR START), 200-250mV greater than VR(SHR START), or other suitable voltage amounts greater than VR(SHR START). At this time, the signal OUT can be pulled up or set to [VPIXOUT-VGS(P1)], where VPIXOUT represents the voltage level at output line 38, and VGS(P1) represents the gate-to-source voltage on transistor P1. Capacitor C1 can also be charged to store the auto-zero value. The period during which the auto-zero switch Saz is open is sometimes referred to as the auto-zero phase.

[0051] At time t1, the auto-zero signal AZ can be disabled to close switch Saz. At time t2, the Vramp signal can be set to its first ramp-start voltage level VR (SHR START). Lowering Vramp in this way disconnects transistor P1, which pulls the signal OUT to a higher voltage level, such as... Figure 6 As shown in the image.

[0052] At time t3, the Vramp signal can begin to ramp up from VR (SHR START). This first voltage ramp used to switch the reset voltage level on pixel output line 38 is sometimes referred to as the SHR (Sample-Hold Reset) ramp. The voltage Vramp will continue to rise, and at time t4, transistor P1 can close again. When transistor P1 is closed, current source transistors N1 and N2 pull the signal OUT down to [VB3-VGS(N3)], where VGS(N3) represents the gate-to-source voltage across transistor N3. The signal OUT falling below the threshold level THRES of the second comparator stage 58 will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t4 is therefore a function of the reset signal read from the selected pixel. After time t4, the Vramp signal can continue to increase until it reaches the ramp stop voltage level VR (STOP).

[0053] At time t5, the charge transfer control signal TX can be a pulsed high level. The period during which the signal TX is valid is sometimes referred to as the charge transfer phase. During this time, the PIXOUT signal can begin to increase, and the Vramp signal can drop back to VR (AZ) (if a voltage clamping circuit 64 is present at time t6, as shown in the figure), or it can drop back to VR (SHSSTART) under other conditions. After time t6, the PIXOUT signal can remain high in low light conditions as shown in waveform 80, or it can begin to drop in high light conditions as shown in waveform 82.

[0054] At time t7, the charge transfer control signal TX can be deactivated to signal the end of the charge transfer phase. At time t7, as shown in waveforms 80 and 82, the PIXOUT waveform can begin to decline under both low-light and high-light conditions. At time t7, if the clamping circuit 64 is included within the comparator stage 56, the signal CLAMP_EN can be a pulsed high level to temporarily activate the clamping circuit. Disconnecting the clamping circuit 64 can help the PIXOUT voltage stabilize to the actual SHS value more quickly.

[0055] At time t8, the counter enable signal COUNTER_EN can be made active to allow counter 62 to start incrementing again, and the Vramp signal should further drop to the second ramp start voltage level VR (SHS START). Figure 6In this example, the second ramp-start voltage VR (SHS START) can be less than the first ramp-start voltage VR (SHR START). This is merely illustrative. In other embodiments, the second ramp-start voltage VR (SHS START) can be equal to or greater than the first ramp-start voltage VR (SHR START). Reducing the Vramp in this way disconnects the transistor P1, which pulls the signal OUT to a higher voltage level based on the actual signal read from the selected pixel.

[0056] In low-light conditions, as shown in waveform 88 (counter enable), the signal OUT will rise above the threshold level THRES of the second comparator stage 58, as shown in waveform 84, and the counter 62 can count again. The counter 62 can optionally be reset before time t8 to help distinguish the SHR count value from the SHS (sample-and-hold) count value. Alternatively, the counter 62 can be inverted before time t6 to subtract the SHR count value from the SHS count value. In bright-light conditions, as shown in waveform 89 (counter enable), the signal OUT will rise above the threshold level THRES of the second comparator stage 58, as shown in waveform 86, and the counter 62 can count again.

[0057] At time t9, the Vramp voltage can begin to ramp up from the second ramp start voltage VR (SHS START). In the bright light condition, transistor P1 can close at time t10. When transistor P1 closes at time t10, the signal OUT will drop below the threshold level THRES of the second comparator stage 58, as shown in waveform 86. This will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t10 is therefore a function of the bright signal value read from the selected pixel.

[0058] In low-light conditions, transistor P1 may close later at time t11. When transistor P1 closes at time t11, the signal OUT will drop below the threshold level THRES of the second comparator stage 58, as shown in waveform 84. This will cause comparator 58 to trip, thereby invalidating the counter enable signal output from latch 60. Invalidating the counter enable signal prevents counter 62 from incrementing further. The final count value generated by counter 62 at time t11 is therefore a function of the weak signal value read from the selected pixel. After time t11, the Vramp signal may continue to increase until it reaches the ramp stop voltage level VR (STOP).

[0059] The slope of the first rising SHR ramp after time t3 may be equal to the slope of the second rising SHS ramp after time t9. This is exemplary. In some embodiments, the slope of the first SHR ramp after time t3 may be different from the slope of the second SHS ramp after time t9. As another example, the slope of the first SHR ramp after time t3 may be greater than the slope of the second SHS ramp after time t9. As yet another example, the slope of the first SHR ramp after time t3 may be less than the slope of the second SHS ramp after time t9.

[0060] According to one embodiment, an image sensor is provided, including: a pixel output line; a plurality of pixels coupled to the pixel output line; and a data converter coupled to the pixel output line, and having a first single-ended comparator stage configured to receive a ramp voltage signal and a second single-ended comparator stage configured to receive an output signal from the first single-ended comparator stage.

[0061] According to another embodiment, the image sensor may optionally include: a first current source transistor coupled to a pixel output line; and a second current source transistor coupled between the first current source transistor and the pixel output line.

[0062] According to another embodiment, the first single-ended comparator stage includes a third current source transistor coupled between the second current source transistor and the pixel output line.

[0063] According to another embodiment, the first single-ended comparator stage may optionally include a common-source amplifier transistor having a first source-drain terminal coupled to a pixel output line and a second source-drain terminal coupled to a node located between the second current source transistor and the third current source transistor.

[0064] According to another implementation, the common-source amplifier transistor can be a p-type transistor.

[0065] According to another embodiment, the first single-ended comparator stage may optionally include an auto-zero switch coupled between the gate terminal and the second source-drain terminal of the common-source amplifier transistor.

[0066] According to another embodiment, the first single-ended comparator stage may optionally include a first capacitor having a first terminal coupled to the gate terminal of a common-source amplifier transistor and a second terminal configured to receive a ramp voltage signal.

[0067] According to another embodiment, the first single-ended comparator stage may optionally include a second capacitor having a first terminal coupled to the gate terminal of a common-source amplifier transistor and a second terminal coupled to a power supply line.

[0068] According to another embodiment, the first single-ended comparator stage may optionally include a filter capacitor having a first terminal coupled to a first source-drain terminal of a common-source amplifier transistor and a second terminal coupled to a second source-drain terminal of a common-source amplifier transistor.

[0069] According to another embodiment, the first single-ended comparator stage may optionally include a voltage clamping circuit that is directly coupled to the second source-drain terminal of the common-source amplifier transistor.

[0070] According to another embodiment, the voltage clamping circuit may optionally include: a clamping transistor having a source terminal coupled to a second source-drain terminal of a common-source amplifier transistor and a gate terminal coupled to a node located between a first current source transistor and a second current source transistor; and a clamping enable switch coupled between the drain terminal of the clamping transistor and a power supply line.

[0071] According to another embodiment, the image sensor may optionally include a ramp voltage generator configured to generate a ramp voltage signal, the ramp voltage generator being configured to ramp up the ramp voltage signal to perform a sample-and-hold reset (SHR) transition and a sample-and-hold signal (SHS) transition.

[0072] According to another embodiment, the image sensor may optionally include a ramp voltage generator configured to generate a ramp voltage signal, the ramp voltage generator being configured to ramp up the ramp voltage signal to perform a sample-and-hold reset (SHR) transition and a sample-and-hold signal (SHS) transition.

[0073] According to another embodiment, the data converter may optionally include: a latch circuit configured to receive a signal from a second single-ended comparator stage; and a counter configured to receive an enable signal from the latch circuit.

[0074] According to one embodiment, an analog-to-digital converter (ADC) operable with image sensor pixels is provided. The ADC includes: a first single-ended comparator configured to receive a pixel output signal from the image sensor pixels, receive a ramp voltage signal from a ramp voltage generator, and generate a corresponding output signal; a second single-ended comparator configured to receive the output signal from the first single-ended comparator and configured to output a first value when the output signal is less than a threshold level, and output a second value when the output signal is greater than a threshold level; and a counter enabled based on whether the second single-ended comparator outputs the first or second value.

[0075] According to another embodiment, the ADC may optionally include a first current source transistor coupled between an image sensor pixel and a ground line; a second current source transistor coupled between an image sensor pixel and the first current source transistor; and a third current source transistor coupled between an image sensor pixel and the second current source transistor.

[0076] According to another embodiment, the ADC may optionally include: a common-source amplifier transistor having a first source-drain terminal coupled to an image sensor pixel and a second source-drain terminal thereon for generating an output signal.

[0077] According to another embodiment, the ADC may optionally include an auto-zero switch coupled between a second source-drain terminal and the gate terminal of a common-source amplifier transistor; a first capacitor having a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal configured to receive a ramp voltage signal; and a second capacitor having a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal coupled to ground.

[0078] According to another embodiment, the ADC may optionally include: a filter capacitor coupled across the first source-drain terminal and the second source-drain terminal of the common-source amplifier transistor; and a voltage clamping circuit directly coupled to the second source-drain terminal of the common-source amplifier transistor and configured to selectively pull down the output signal.

[0079] According to one embodiment, a method for operating an optical sensor is provided, comprising: outputting a pixel signal; outputting a rising ramp voltage or a falling ramp voltage; receiving the pixel signal, receiving the rising ramp voltage or the falling ramp voltage through a first single-ended comparator stage, and generating a first output signal; comparing the first output signal with a threshold level through a second single-ended comparator stage and generating a second output signal; and controlling a counter based on the second output signal.

[0080] The above description is merely illustrative and various modifications can be made to the described implementation scheme. The above implementation scheme can be implemented individually or in any combination.

Claims

1. An image sensor, the image sensor comprising: Pixel output line; Multiple pixels, wherein the multiple pixels are coupled to the pixel output line; as well as A data converter coupled to the pixel output line and having a first single-ended comparator configured to receive a ramp voltage signal and a second single-ended comparator configured to receive an output signal from the first single-ended comparator, wherein the first single-ended comparator includes a common-source amplifier transistor having a gate terminal configured to receive the ramp voltage signal and a first source-drain terminal coupled to the pixel output line.

2. The image sensor according to claim 1, further comprising: A first current source transistor is coupled to the pixel output line; as well as A second current source transistor is coupled between the first current source transistor and the pixel output line.

3. The image sensor according to claim 2, wherein, The first single-ended comparator stage includes a third current source transistor coupled between the second current source transistor and the pixel output line.

4. The image sensor according to claim 3, wherein, The common-source amplifier transistor also includes a second source-drain terminal coupled to a node located between the second current source transistor and the third current source transistor.

5. The image sensor according to claim 1, wherein, The common-source amplifier transistor includes a p-type transistor.

6. The image sensor according to claim 4, wherein, The first single-ended comparator stage further includes an auto-zero switch coupled between the gate terminal of the common-source amplifier transistor and the second source-drain terminal.

7. The image sensor according to claim 6, wherein, The first single-ended comparator stage further includes a first capacitor having a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal configured to receive the ramp voltage signal.

8. The image sensor according to claim 7, wherein, The first single-ended comparator stage further includes a second capacitor having a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal coupled to a power supply line.

9. The image sensor according to claim 4, wherein, The first single-ended comparator stage further includes a filter capacitor having a first terminal coupled to the first source-drain terminal of the common-source amplifier transistor and a second terminal coupled to the second source-drain terminal of the common-source amplifier transistor.

10. The image sensor according to claim 6, wherein, The first single-ended comparator stage further includes a voltage clamping circuit, which is directly coupled to the second source-drain terminal of the common-source amplifier transistor.

11. The image sensor according to claim 10, wherein, The voltage clamping circuit includes: A clamping transistor having a source terminal coupled to the second source-drain terminal of the common-source amplifier transistor and a gate terminal coupled to a node located between the first current source transistor and the second current source transistor; and A clamp enable switch is coupled between the drain terminal of the clamp transistor and the power supply line.

12. The image sensor according to claim 1, further comprising: A ramp voltage generator configured to generate the ramp voltage signal, the ramp voltage generator configured to ramp the ramp voltage signal to perform a sample-and-hold reset (SHR) transition and a sample-and-hold signal (SHS) transition.

13. The image sensor according to claim 1, further comprising: A ramp voltage generator configured to generate the ramp voltage signal and to ramp down the ramp voltage signal to perform a sample-and-hold reset (SHR) transition and a sample-and-hold signal (SHS) transition.

14. The image sensor according to claim 1, wherein, The data converter also includes: A latch circuit, configured to receive a signal from the second single-ended comparator stage; and A counter, configured to receive an enable signal from the latch circuit.

15. An analog-to-digital converter capable of operating with pixels of an image sensor, the analog-to-digital converter comprising: The first single-ended comparator is configured to receive pixel output signals from the image sensor pixels, receive ramp voltage signals from the ramp voltage generator, and generate corresponding output signals. A second single-ended comparator is configured to receive the output signal from the first single-ended comparator and to output a first value when the output signal is less than a threshold level and to output a second value when the output signal is greater than the threshold level. The first single-ended comparator stage includes a common-source amplifier transistor having a gate terminal configured to receive the ramp voltage signal and a first source-drain terminal coupled to a pixel of the image sensor.

16. The analog-to-digital converter of claim 15, further comprising: A latch circuit configured to receive a signal from the second single-ended comparator stage; as well as A counter, configured to receive an enable signal from the latch circuit.

17. The analog-to-digital converter of claim 15, further comprising: A first current source transistor is coupled between the image sensor pixel and the ground line; A second current source transistor is coupled between the image sensor pixel and the first current source transistor; as well as A third current source transistor is coupled between the image sensor pixel and the second current source transistor.

18. The analog-to-digital converter according to claim 15: The common-source amplifier transistor has a second source-drain terminal thereon on which the output signal is generated.

19. The analog-to-digital converter of claim 18, further comprising: An automatic zero-adjustment switch is coupled between the second source-drain terminal and the gate terminal of the common-source amplifier transistor; A first capacitor having a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal configured to receive the ramp voltage signal; as well as The second capacitor has a first terminal coupled to the gate terminal of the common-source amplifier transistor and a second terminal coupled to ground.

20. The analog-to-digital converter of claim 18, further comprising: A filter capacitor is coupled across the first source-drain terminal and the second source-drain terminal of the common-source amplifier transistor; as well as A voltage clamping circuit is directly coupled to the second source-drain terminal of the common-source amplifier transistor and is configured to selectively pull down the output signal.

21. A method of operating an optical sensor, the method comprising: Output pixel signals through pixels; The ramp voltage generator outputs either a rising ramp voltage or a falling ramp voltage. The pixel signal is received through the first single-ended comparator, the rising ramp voltage or the falling ramp voltage is received, and a first output signal is generated. The first output signal is compared with a threshold level by a second single-ended comparator to generate a second output signal; The first single-ended comparator stage includes a common-source amplifier transistor having a gate terminal configured to receive the rising or falling ramp voltage and a first source-drain terminal coupled to the pixel.

22. The method of claim 21, further comprising: Based on the second output signal, activate the counter; as well as When the counter is enabled, the voltage clamp in the first single-ended comparator stage is activated.

Images