A driving apparatus, method and display device of a display panel

Abstract

The application discloses a display panel driving device, method and display device, comprising: a level conversion module, a parallelly arranged timing signal input module and a shutdown signal detection module, wherein the timing signal input module is used for generating a timing reference signal for driving the display panel to display; the shutdown signal detection module is used for detecting a shutdown signal for stopping the display panel from displaying; the level conversion module is connected with the timing signal input module, and is used for generating a timing control signal corresponding to the timing reference signal under the control of the timing reference signal, the timing control signal comprising a high voltage signal and a low voltage signal; the level conversion module is connected with the shutdown signal detection module, and is used for generating a shutdown control signal under the control of the shutdown signal, the shutdown control signal being the high voltage signal corresponding to the timing control signal.

Description

Technical Field

[0001] This application generally relates to the field of display technology, and specifically to a driving device, method and display device for a display panel. Background Technology

[0002] With the development of display technology, high resolution and narrow bezels have become the development trend. In response to this trend, Gate Drive on Array (GOA) technology has emerged. GOA technology integrates the gate drive circuitry directly onto the array substrate, thereby replacing the drive chip that is bonded to the panel.

[0003] When a display device is powered off, the charge within the pixels needs to be released to prevent problems such as image retention and flickering caused by prolonged charge accumulation. Current technology typically involves raising a reference voltage, such as VSS (Voltage Series, common ground voltage), at the moment the display panel is powered off to completely discharge the entire GOA circuit. However, the reference voltage is initially low, and raising it to a high level takes time, affecting the release speed of residual charge. This results in charge residue and abnormal image display. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a driving device, method and display device for a display panel that can solve the problem of slow charge release speed during the power-off process of existing display devices.

[0005] In a first aspect, this application provides a driving device for a display panel, comprising: a level conversion module, a timing signal input module and a power-off signal detection module connected in parallel, wherein...

[0006] The timing signal input module is used to generate timing reference signals to drive the display panel for display.

[0007] The power-off signal detection module is used to detect the power-off signal that drives the display panel to stop displaying;

[0008] The level conversion module is connected to the timing signal input module and is used to generate a timing control signal corresponding to the timing reference signal under the control of the timing reference signal. The timing control signal includes a high voltage signal and a low voltage signal. The level conversion module is connected to the power-off signal detection module and is used to generate a power-off control signal under the control of the power-off signal. The power-off control signal is a high voltage signal corresponding to the timing control signal.

[0009] Optionally, the level conversion module includes a first conversion unit, a second conversion unit, and a conversion control unit.

[0010] The first end of the first conversion unit is connected to the first power supply end, the second end of the first conversion unit is connected to the signal output end, and the control end of the first conversion unit is connected to the conversion control unit. The first conversion unit is used to provide the voltage of the first power supply end to the signal output end under the control of the conversion control unit.

[0011] The first end of the second conversion unit is connected to the second power supply terminal, the second end of the second conversion unit is connected to the signal output terminal, and the control terminal of the second conversion unit is connected to the conversion control unit. The second conversion unit is used to provide the voltage of the second power supply terminal to the signal output terminal under the control of the conversion control unit.

[0012] Optionally, the conversion control unit includes a first control sub-circuit and a second control sub-circuit arranged in parallel.

[0013] The first terminal of the first control sub-circuit is connected to the control terminal of the first conversion unit and the control terminal of the second conversion unit. The second terminal of the first control sub-circuit is connected to the first level voltage terminal. The control terminal of the first control sub-circuit is connected to the timing signal input module. The first control sub-circuit is used to provide the voltage of the first level voltage terminal to one of the first conversion unit and the second conversion unit under the control of the timing reference signal.

[0014] The second control sub-circuit is connected to the second level voltage terminal, and the second control sub-circuit is used to provide the voltage of the second level voltage terminal to the other of the first conversion unit and the second conversion unit.

[0015] Optionally, the first power supply terminal is a high voltage signal, the first terminal of the power-off signal detection module is connected to the third level voltage terminal, the second terminal of the power-off signal detection module is connected to the conversion control unit, the control terminal of the power-off signal detection module is connected to the power-off control line that provides the power-off signal, the power-off detection module is used to provide the voltage of the third level voltage terminal to the conversion control unit when the power-off signal is detected, and the conversion control unit is also used to provide the voltage of the first level voltage terminal to the first conversion unit under the voltage control of the third level voltage terminal.

[0016] Optionally, the power-off signal is the power-off of the signal line providing the power-off signal, and the power-off control signal is the power-off of the signal output terminal following the high-voltage signal of the first power supply terminal.

[0017] Optionally, the first conversion unit includes a first transistor, the second conversion unit includes a second transistor, and the first control sub-circuit includes a third transistor.

[0018] The first terminal of the first transistor is connected to the first power supply terminal, the second terminal of the first transistor is connected to the signal output terminal, and the control terminal of the first transistor is connected to the second terminal of the third transistor and the second voltage level terminal.

[0019] The first terminal of the second transistor is connected to the second power supply terminal, the second terminal of the second transistor is connected to the signal output terminal, and the control terminal of the second transistor is connected to the second terminal of the third transistor and the second voltage level terminal.

[0020] The first terminal of the third transistor is connected to the first voltage level terminal, and the control terminal of the third transistor is connected to the timing signal input module and the power-off signal detection module.

[0021] Optionally, the second voltage level terminal shares the same voltage signal as the first power supply terminal, the first terminal of the third transistor is grounded, and the second control sub-circuit includes a current-limiting resistor connected to the second voltage level terminal.

[0022] Optionally, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0023] Optionally, the power-off signal detection module includes a fourth transistor, the first terminal of which is connected to a third voltage level terminal, the control terminal of which is connected to the power-off control line, and the second terminal of which is connected to the control terminal of the third transistor.

[0024] Optionally, the third transistor is an N-type transistor, the fourth transistor is a P-type transistor, and the high-level voltage value of the timing reference signal is equal to the voltage value of the third-level voltage terminal.

[0025] Optionally, the timing of the timing control signal is the same as the timing of the timing reference signal, the voltage value of the first power supply terminal is greater than the high-level voltage value of the timing reference signal, and the voltage value of the second power supply terminal is greater than the low-level voltage value of the timing reference signal.

[0026] Secondly, this application provides a driving method for a display panel, applied to a driving device for a display panel as described above, the method comprising:

[0027] When a power-off signal is detected, the level conversion module generates a power-off control signal corresponding to the power-off signal, and the power-off control signal is a high-voltage signal corresponding to the timing control signal;

[0028] When no power-off signal is detected, the level conversion module generates a timing control signal corresponding to the timing reference signal, the timing control signal including a high voltage signal and a low voltage signal.

[0029] Thirdly, this application provides a display device, including a gate driving circuit and a driving device for at least one display panel as described above, connected to the gate driving circuit.

[0030] Optionally, the gate driving circuit includes a first gate driving sub-circuit for driving the odd-numbered pixel rows of the display panel and a second gate driving sub-circuit for driving the even-numbered pixel rows of the display panel. The first gate driving sub-circuit includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the first gate driving sub-circuit is provided with a first frame start signal. The second gate driving sub-circuit includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the second gate driving sub-circuit is provided with a second frame start signal.

[0031] Optionally, the driving device includes a first driving sub-circuit connected to the first gate driving sub-circuit, the first driving sub-circuit being used to generate a first frame start reference signal, a first frame start signal corresponding to the first frame start reference signal, and a first power-off control signal corresponding to the first frame start signal.

[0032] and / or

[0033] The driving device includes a second driving sub-circuit connected to the second gate driving sub-circuit. The second driving sub-circuit is used to generate a second frame start reference signal, a second frame start signal corresponding to the second frame start reference signal, and a second power-off control signal corresponding to the second frame start signal.

[0034] Optionally, the driving device includes a first driving sub-circuit and a second driving sub-circuit, wherein the first driving sub-circuit and the second driving sub-circuit share the same power-off signal detection module.

[0035] Optionally, the display device includes a display panel and a driving circuit board. The driving circuit board includes a timing controller and a level converter. The timing signal input module is disposed on the timing controller, and the level converter module and the power-off signal detection module are disposed on the level converter.

[0036] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0037] The display panel driving device provided in this application embodiment sets the power-off detection module on the level conversion module of the GOA circuit. While the level conversion module converts the timing signal of GOA, it controls the output terminal of the level conversion module to output a high-level signal corresponding to the timing control signal when the power is off. At the same time, the pixel circuits on the display panel are turned on, realizing the release of residual charge on the display panel, avoiding display abnormalities and improving the display effect. When the power is off, the level conversion module loses power along with the high-level signal on the level conversion module, realizing the power-off of the display panel. Attached Figure Description

[0038] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0039] Figure 1 A schematic diagram of the structure of a display panel provided for an embodiment of this application;

[0040] Figure 2 A schematic diagram of a GOA architecture provided for an embodiment of this application;

[0041] Figure 3 A schematic diagram of the structure of a driving device for a display panel provided for an embodiment of this application;

[0042] Figure 4 A schematic diagram of the structure of another display panel driving device provided for an embodiment of this application;

[0043] Figure 5 A connection diagram of a driving device for a display panel provided for an embodiment of this application;

[0044] Figure 6 A flowchart illustrating a method for driving a display panel, provided as an embodiment of this application;

[0045] Figure 7 A timing diagram of a driving method for a display panel provided for an embodiment of this application;

[0046] Figure 8 Timing diagram of another display panel driving method provided for embodiments of this application;

[0047] Figure 9-10 This is a schematic diagram of the structure of a display device provided for an embodiment of this application. Detailed Implementation

[0048] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0050] For ease of description, the driving device and driving method for the display panel provided in this embodiment will be used in applications such as... Figure 1 The following explanation uses the display panel shown as an example. See also... Figure 1 The display panel includes multiple pixel units P, multiple data lines D, and multiple gate lines G. The pixel units P are arranged in an array, the data lines D extend along the column direction, and the gate lines G extend along the row direction. The data lines D and gate lines G intersect to define the pixel units P. Each data line D connects to a column of pixel units P, and each gate line G connects to a row of pixel units P. The multiple data lines D write data voltages into the pixel units P row by row. The gate driving circuit 200 outputs a gate scan signal, which completes the row-by-row scanning of the pixel array through the gate lines; the data driving circuit 300 outputs a data signal, which is transmitted to the corresponding pixel unit through the data lines to realize image grayscale.

[0051] GOA (Gate On Array) is a technology that integrates the gate driving circuit 200 onto the TFT substrate. Each GOA unit acts as a shift register, sequentially transmitting the scan signal to the next GOA unit, turning on the TFT switch line by line, and completing the data signal input of the pixel unit. In this embodiment, the GOA unit is disposed on one side of the display panel 100, and the GOA is connected to multiple gate lines G, inputting a scan voltage to the gate lines G.

[0052] The above GOA unit is as follows Figure 2 As shown, the display panel 100 can include multiple cascaded GOA units (GOA0, GOA1...GOAn). The frame start signal STVSTV provided by the waveform generation unit is input through the signal input terminal INPUT of the first-stage GOA unit GOA0, driving the GOA unit to start working. In addition, except for the first-stage GOA unit GOA0, the signal input terminal INPUT of each of the other GOA units is connected to the signal output terminal OUTPUT of its adjacent parent GOA unit. In this way, under the control of the clock signals CLK (CLK1 and CLK2), the cascaded GOA units can output gate scan signals (G0, G1...Gn) line by line through the signal output terminal OUTPUT to scan the gate lines in the display panel 100 line by line.

[0053] Of course, the above is merely an example of one GOA unit structure. When each GOA unit also has a reset signal input terminal RESET, except for the last GOA unit GOAn, the reset signal input terminal RESET of the remaining GOA units is connected to the signal output terminal OUTPUT of the next-level GOA unit. This invention does not limit the structure of the GOA unit, as long as it can scan the grid lines in the display panel 100 line by line under the control of the frame start signal STV and the clock signal CLK.

[0054] Optionally, this example only uses the first-level GOA unit connected to the STV signal. Of course, it can also be multiple levels connected to the STV signal, such as the first two levels, or the first three or four levels, etc. There is no limitation here. In addition, there can be one or more STV signals. For example, there are two STV signals: STV1 is the start signal for odd-numbered rows of data, and STV2 is the signal for even-numbered rows of data.

[0055] Regarding the scanning method, it can be either progressive scanning or interlaced scanning; in terms of scanning direction, it can be scanning from top to bottom or from bottom to top. Specific pixel scanning methods can be found in various existing technologies, which will not be described in detail here. In this application embodiment, a progressive scanning method from top to bottom is used as an example.

[0056] In the embodiments of this application, the display panel 100 can be a liquid crystal display panel 100 (LCD), an organic light-emitting display panel 100 (OLED), an electronic paper display panel 100 (E-paper), etc. Here, an LCD panel is used as an example for explanation, and other types of panels are analogous.

[0057] Please see details. Figure 3 This application provides a driving device for a display panel 100, including: a level conversion module 10, a timing signal input module 20 connected in parallel, and a power-off signal XDon detection module 30, wherein...

[0058] The timing signal input module 20 is used to generate timing reference signals to drive the display panel 100 to display.

[0059] The power-off signal XDon detection module 30 is used to detect the power-off signal XDon that drives the display panel 100 to stop displaying;

[0060] The level conversion module 10 is connected to the timing signal input module 20 and is used to generate a timing control signal corresponding to the timing reference signal under the control of the timing reference signal. The timing control signal includes a high voltage signal and a low voltage signal. The level conversion module 10 is connected to the power-off signal XDon detection module 30 and is used to generate a power-off control signal under the control of the power-off signal XDon. The power-off control signal is a high voltage signal corresponding to the timing control signal.

[0061] In this application, by setting a level conversion module 10, the clock signal of the input GOA circuit can be processed to perform level conversion, so that the clock signal input to the display panel 100 can meet the timing requirements of the display panel 100 during normal display and power-off processes.

[0062] In this embodiment, by setting the power-off detection module on the level conversion module 10 of the GOA circuit, the level conversion module 10 converts the timing signal of the GOA while controlling the output terminal OUT of the level conversion module 10 to output a high-level signal corresponding to the timing control signal when the power is off. At the same time, the pixel circuits on the display panel 100 are turned on, thereby releasing the residual charge on the display panel 100, avoiding display abnormalities, and improving the display effect. When the power is off, the level conversion module 10 loses power along with the high-level signal on the level conversion module 10, thereby turning off the display panel 100.

[0063] The timing signal input module 20 can be a timing controller (TCON). The timing signal input module 20 provides a timing reference signal to the level conversion module 10, which further converts the signal to generate a timing control signal output to the gate drive circuit 200200. It is understood that the timing reference signal in this application can include one of the following: a clock signal (e.g., CLK) and a frame start signal (e.g., STV). In this application, the frame start reference signal STV0 and the timing control signal STV are used as examples. In practical applications, the drive signal of the input signal conversion circuit 100 can be other GOA signals used for inputting the GOA circuit, such as CLK1, CLK2, CLK3, etc.

[0064] like Figure 4As shown, the level conversion module 10 described in this application includes a first conversion unit 11, a second conversion unit 12, and a conversion control unit 3. The first terminal of the first conversion unit 11 is connected to the first power supply terminal VGH, the second terminal of the first conversion unit 11 is connected to the signal output terminal OUT, and the control terminal of the first conversion unit 11 is connected to the conversion control unit 3. The first conversion unit 11 is used to provide the voltage of the first power supply terminal VGH to the signal output terminal OUT under the control of the conversion control unit 3. The first terminal of the second conversion unit 12 is connected to the second power supply terminal VGL, the second terminal of the second conversion unit 12 is connected to the signal output terminal OUT, and the control terminal of the second conversion unit 12 is connected to the conversion control unit 3. The second conversion unit 12 is used to provide the voltage of the second power supply terminal VGL to the signal output terminal OUT under the control of the conversion control unit 3.

[0065] In this application, the timing reference signal generated by the timing signal input module 20 can be a digital signal. By inputting the digital signal into the level conversion module 10, a digital-to-analog conversion can be achieved, outputting the analog signal corresponding to the digital signal and inputting it to each pixel row. Alternatively, the timing reference signal can also be an analog signal. The level conversion module 10 further boosts and amplifies the timing reference signal, and then inputs the boosted signal to each pixel row. The choice is made according to requirements in different embodiments.

[0066] In this embodiment, the frame start signal STV of the level conversion module 10 has been amplified and can enable the TFT when the display panel 100 is displaying normally. The voltage value of the frame start signal STV can reach the TFT's turn-on voltage Vgh. Typically, the frame start reference signal STV0 directly transmitted from the timing controller (TCon) to the level conversion circuit has a smaller voltage value, for example, 3.3V. The frame start reference signal STV0 can be amplified to reach the TFT's turn-on voltage Vgh. Vgh (i.e., V STV For example, 20V to 30V.

[0067] It is understood that the timing period of the timing control signal is the same as the timing period of the timing reference signal. The high and low voltages of the timing control signal are set as needed to meet the high-voltage switching signal of the GOA. In this embodiment, the timing of the timing control signal is the same as the timing of the timing reference signal. The voltage value of the first power supply terminal VGH is greater than the high-level voltage value of the timing reference signal, and the voltage value of the second power supply terminal VGL is greater than the low-level voltage value of the timing reference signal.

[0068] In this application, the first conversion unit 11 and the second conversion unit 12 are used to generate the high voltage signal and the low voltage signal of the timing control signal, respectively. It is understood that the first conversion unit 11 and the second conversion unit 12 can be interchanged. In this embodiment of the application, the first conversion unit 11 generates the high voltage signal of the timing control signal and the second conversion unit 12 generates the low voltage signal of the timing control signal for illustrative purposes.

[0069] It is understood that the control terminals of the first conversion unit 11 and the second conversion unit 12 are connected to two levels: a valid level and an invalid level. A valid signal (level) refers to the signal (level) used to turn on the corresponding switching element, and an invalid signal (level) refers to the signal (level) used to turn off the corresponding switching element. Similarly, this interpretation applies to other embodiments of this application. Valid level and invalid level only represent that the signal level has two state quantities; they do not mean that the valid level or invalid level has a specific numerical value throughout the text.

[0070] In this embodiment, the conversion control unit 3 generates two different control levels. The effective level of the first conversion unit 11 is simultaneously the invalid level of the second conversion unit 12, and the invalid level of the second conversion unit 12 is simultaneously the effective level of the first conversion unit 11.

[0071] Specifically, the conversion control unit 3 includes a first control sub-circuit 301 and a second control sub-circuit 302 arranged in parallel. The first terminal of the first control sub-circuit 301 is connected to the control terminal of the first conversion unit 11 and the control terminal of the second conversion unit 12. The second terminal of the first control sub-circuit 301 is connected to a first level voltage terminal V1. The control terminal of the first control sub-circuit 301 is connected to the timing signal input module 20. The first control sub-circuit 301 is used to provide the voltage of the first level voltage terminal V1 to one of the first conversion unit 11 and the second conversion unit 12 under the control of the timing reference signal. The second control sub-circuit 302 is connected to a second level voltage terminal V2. The second control sub-circuit 302 is used to provide the voltage of the second level voltage terminal V2 to the other of the first conversion unit 11 and the second conversion unit 12.

[0072] It is understood that in this embodiment, the first control sub-circuit 301 can generate the effective level (first level) of the first conversion unit 11, and the second control sub-circuit 302 can generate the effective level (second level) of the second conversion unit 12. Of course, in other embodiments, the first control sub-circuit 301 and the second control sub-circuit 302 can be interchanged, and this application does not limit this.

[0073] In this application, the first control sub-circuit 301 is controlled by a timing reference signal. When the timing reference signal controls the first control sub-circuit 301 to be turned on, the first control sub-circuit 301 outputs a first-level signal. When the timing reference signal controls the first control sub-circuit 301 to be turned off, the second control sub-circuit 302 outputs a second-level signal. The conversion control unit 3 ensures that the timing period of the signal output by the level conversion module 10 is the same as the timing period of the timing reference signal. In this embodiment, the first-level voltage terminal V1 is used to provide a first-level voltage signal, and the second-level voltage terminal V2 is used to provide a second-level voltage signal. This is merely an illustrative example; in different embodiments, the first-level voltage terminal V1 and the second-level voltage terminal V2 can be interchanged.

[0074] For example, the first power supply terminal VGH is a high voltage signal, the first terminal of the power-off signal XDon detection module 30 is connected to the third level voltage terminal V3, the second terminal of the power-off signal XDon detection module 30 is connected to the conversion control unit 3, and the control terminal of the power-off signal XDon detection module 30 is connected to the power-off control line that provides the power-off signal XDon. The power-off detection module is used to provide the voltage of the third level voltage terminal V3 to the conversion control unit 3 when the power-off signal XDon is detected. The conversion control unit 3 is also used to provide the voltage of the first level voltage terminal V1 to the first conversion unit 11 under the voltage control of the third level voltage terminal V3.

[0075] In this embodiment, since the first control sub-circuit 301 is used to generate the effective level of the first conversion unit 11, and the first conversion unit 11 is used to generate the high-voltage signal of the timing control signal, the power-off detection module is connected in parallel to the control terminal (first control sub-circuit 301) of the first conversion unit 11. When the power-off signal XDon is detected, the first control sub-circuit 301 generates the effective level of the first conversion unit 11 under the control of the power-off detection module. It can be understood that in this embodiment, the third voltage level V3 is used to provide the effective level that enables the first control sub-circuit 301 to turn on. Depending on the type of components in the first control sub-circuit 301, the third voltage level V3 can be either a high-level signal or a low-level signal.

[0076] The power-off signal XDon is the signal line that provides the power-off signal XDon being powered down, and the power-off control signal is the signal at the signal output terminal OUT that is powered down following the high voltage signal at the first power supply terminal VGH.

[0077] In this embodiment, to meet the power-off timing of the timing reference signal, when the power-off signal XDon is detected, the timing control signal outputs a high-level signal (i.e., the power-off control signal in this application), making the timing signal input to the GOA unit of the display panel 100 a high-level signal. This controls the gate of the transistor to open, thereby releasing the residual charge on the display panel 100. It is understood that in this embodiment, the timing control signal is a periodic signal alternating between high and low levels to satisfy the normal display function of the display panel 100. The power-off control signal includes at least a portion of a high-level signal period to meet the discharge requirements of the display panel 100. In this embodiment, the discharge time is not limited; it can be powered down following the signal of the first voltage terminal V1, thus meeting the requirements.

[0078] This application provides an exemplary connection method for a display panel 100 driving device. Please refer to [link / reference]. Figure 5 .

[0079] The first conversion unit 11 includes a first transistor T1, the second conversion unit 12 includes a second transistor T2, and the first control sub-circuit 301 includes a third transistor T3. The first terminal of the first transistor T1 is connected to the first power supply terminal VGH, the second terminal of the first transistor T1 is connected to the signal output terminal OUT, and the control terminal of the first transistor T1 is connected to the second terminal of the third transistor T3 and the second voltage level terminal V2. The first terminal of the second transistor T2 is connected to the second power supply terminal VGL, the second terminal of the second transistor T2 is connected to the signal output terminal OUT, and the control terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the second voltage level terminal V2. The first terminal of the third transistor T3 is connected to the first voltage level terminal V1, and the control terminal of the third transistor T3 is connected to the timing signal input module 20 and the power-off signal XDon detection module 30. The second control sub-circuit 302 includes a current-limiting resistor R connected to the second voltage level terminal V2.

[0080] The power-off signal XDon detection module 30 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the third level voltage terminal V3. The control terminal of the fourth transistor T4 is connected to the power-off control line. The second terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3.

[0081] In this embodiment, the control terminals of the first transistor T1 and the second transistor T2 are connected at the first node N1. One end of the current-limiting resistor R is connected to the second voltage level V2, and the other end is connected to the first node N1. The second terminal of the third transistor T3 is connected to the first node N1. The signal input module, the control terminal of the third transistor T3, and the second terminal of the fourth transistor T4 are connected at the second node N2.

[0082] In this embodiment, "control terminal" specifically refers to the gate of the transistor, "first terminal" specifically refers to the source of the transistor, and "second terminal" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first terminal" and "second terminal" can be interchanged, that is, the "first terminal" specifically refers to the drain of the transistor, and the "second terminal" specifically refers to the source of the transistor.

[0083] Based on their semiconductor characteristics, transistors can be classified into N-type transistors and P-type transistors. When used as switching transistors, N-type transistors are turned on by a high-level switching signal and turned off by a low-level switching signal; P-type transistors are turned on by a low-level switching signal and turned off by a high-level switching signal.

[0084] In this embodiment, exemplarily, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor. The high-level voltage value of the timing reference signal is equal to the voltage value of the third-level voltage terminal V3. The first power supply terminal VGH is a high-voltage signal, the second power supply terminal VGL is a low-level signal, the first-level voltage terminal V1 is a low-voltage signal, the second-level voltage terminal V2 is a high-voltage signal, and the third-level voltage terminal V3 is a high-level signal. For convenient online arrangement, the second-level voltage terminal V2 and the first power supply terminal VGH share the same voltage signal, and the first terminal of the third transistor T3 is grounded.

[0085] like Figure 6 As shown, this application provides a driving method for a display panel 100, applied to a driving device for a display panel 100 as described above, the method comprising:

[0086] When the power-off signal XDon is detected, the level conversion module 10 generates a power-off control signal corresponding to the power-off signal XDon, and the power-off control signal is a high-voltage signal corresponding to the timing control signal;

[0087] When no power-off signal XDon is detected, the level conversion module 10 generates a timing control signal corresponding to the timing reference signal, the timing control signal including a high voltage signal and a low voltage signal.

[0088] For details, please refer to Figure 7The timing is as follows: when the power-off signal XDon detection module does not detect the power-off signal XDon, that is, XDon is at normal voltage, for example, VXDon = 1.8V, T4 is Pmos (threshold voltage Vth = -1V), and T4 is disconnected. T3 is controlled by the input signal STV0, and T3 is Nmos (threshold voltage Vth = 1.8V).

[0089] When STV0 is high, T3 is on, and the voltage at the first node N1 is the voltage at the first level voltage terminal V1, i.e., N1 = 0V. VGL = -6V, VGH = 25V; at this time, Vgs of T2 = 6V, T2 is Nmos (threshold voltage Vth = 7V), and T2 is off; at this time, Vgs of T1 = -25V, T1 is Pmos (threshold voltage Vth = -1V), and T1 is on. At this time, the voltage at the output terminal OUT is the voltage of VGH, which is 25V.

[0090] When STV0 is low, T3 is off. The voltage at the first node N1 is the voltage provided by the second-level voltage terminal V2 through the current-limiting circuit. The voltage value of the second-level voltage terminal V2 is V2 = 25V, for example, N1 = 24.5V. VGL = -6V, VGH = 24V. At this time, Vgs of T1 is -0.5V, T1 is Pmos (threshold voltage Vth = -1V), and T1 is off. At this time, Vgs of T2 is 30.5V, T2 is Nmos (threshold voltage Vth = 7V), and T2 is on. At this time, the voltage at the output terminal OUT is the voltage of VGL, which is -6V.

[0091] For details, please refer to Figure 8 The timing sequence is as follows: When the power-off signal XDon detection module detects the power-off signal XDon, i.e., the voltage of XDon drops, T4 is at Pmos (threshold voltage Vth = -1V) when VXDon = 0.8V, and T4 is turned on. As VXDon continues to decrease, T4 remains turned on. During power-off, the STV0 signal is forcibly pulled high, and the high-level voltage value of STV0 is equal to the voltage value of the third-level voltage terminal V3. The voltage of the second node N2 is the voltage value of the third-level voltage terminal V3, V3 = 1.8V, i.e., N2 = 1.8V. T3 is controlled by the voltage of the second node N2, and T3 is at Nmos (threshold voltage Vth = 1.8V), and T3 is turned on.

[0092] At this time, the voltage at the first node N1 is the voltage at the first level voltage terminal V1, i.e., N1 = 0V. VGL = -6V, VGH = 25V; at this time, Vgs of T2 = 6V, T2 is Nmos (threshold voltage Vth = 7V), and T2 is off; at this time, Vgs of T1 = -25V, T1 is Pmos (threshold voltage Vth = -1V), and T1 is on. At this time, the voltage at the output terminal OUT is the voltage of VGH, which is 25V.

[0093] In this application, by setting a current-limiting resistor R at the second-level voltage terminal V2, the impact on the transistor control terminal of the level conversion module 10 when the second-level voltage terminal V2 uses a high voltage VGH can be limited, thereby improving the lifespan of the transistor. When the power-off signal XDon is detected, as the timing reference signal is pulled high, the timing control signal is also pulled high under the control of the power-off signal XDon detection module 30, forming a power-off control signal. In this application, during the power-off process of the power-off signal XDon, it can be turned on as soon as the threshold voltage value of the fourth transistor T4 is reached, avoiding the situation where the signal rise is too slow when the timing reference signal is forcibly pulled high, causing the timing control signal to fail to pull high in time, which would result in the display panel 100 releasing charge too slowly and affecting the display effect. The power-off control signal follows the high voltage signal of the first power terminal VGH when it is powered off, thereby realizing power-off control.

[0094] Based on the same inventive concept, this application provides a display device, including a gate driving circuit 200 and a driving device for at least one display panel 100 as described above, connected to the gate driving circuit 200. In one or more embodiments of this application, the display device can be applied to any product or component with display function, such as mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0095] The gate driving circuit 200 includes a first gate driving sub-circuit 210 for driving odd-numbered pixel rows of the display panel 100 and a second gate driving sub-circuit 220 for driving even-numbered pixel rows of the display panel 100. The first gate driving sub-circuit 210 includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the first gate driving sub-circuit 210 is provided with a first frame start signal STV1. The second gate driving sub-circuit 220 includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the second gate driving sub-circuit 220 is provided with a second frame start signal STV2.

[0096] Correspondingly, the driving device includes a first driving sub-circuit 110 connected to the first gate driving sub-circuit 210. The first driving sub-circuit 110 is used to generate a first frame start reference signal STV01, a first frame start signal STV1 corresponding to the first frame start reference signal STV01, and a first power-off control signal corresponding to the first frame start signal STV1.

[0097] The driving device includes a second driving sub-circuit 120 connected to the second gate driving sub-circuit 220. The second driving sub-circuit 120 is used to generate a second frame start reference signal STV02, a second frame start signal STV2 corresponding to the second frame start reference signal STV02, and a second power-off control signal corresponding to the second frame start signal STV2.

[0098] In this embodiment, the display device includes a display panel 100 and a driving circuit board. The driving circuit board includes a timing controller TCON, a timing signal input module 20 is disposed on the timing controller TCON, and a level conversion module 10 and a power-off signal XDon detection module 30 are disposed on the driving circuit board.

[0099] When the driving device in this embodiment is applied to dual-sided driving, one side of the display panel 100 can use the driving method in the prior art, while the other side can use the driving method provided in this application, such as... Figure 9 As shown, the first gate driving sub-circuit 210 uses the existing level converter L / S to output the first frame start signal STV1, and the second gate driving sub-circuit 220 outputs the second frame start signal STV2 through the second driving sub-circuit 120. The timing signal input module 20 of the second driving sub-circuit 120 is set on the timing controller TCON. The timing controller TCON is connected to the level converter L / S and the second driving sub-circuit 120, and provides timing signals to the level converter L / S and the level conversion module 30 through the timing controller TCON.

[0100] In this application, each gate driver sub-circuit can be equipped with a driver sub-circuit. Specifically, the driving device includes a first driver sub-circuit 110 connected to the first gate driver sub-circuit 210 and a second driver sub-circuit 120 connected to the second gate driver sub-circuit 220. This allows for signal conversion of one gate driver sub-circuit and the generation of a power-off control signal through each driving device. During configuration, the timing signal input modules on the first and second driver sub-circuits can be simultaneously configured on the timing controller TCON.

[0101] It is understood that the power-off signal XDon detection module 30 in this embodiment can simultaneously control the level conversion modules 10 of various signals. For example, it can simultaneously control the clock signal and the frame start signal in the same GOA architecture, or simultaneously control the level conversion modules 10 in the first driving sub-circuit 110 and the second driving sub-circuit 120 in bilateral driving. By sharing the same power-off signal XDon detection module 30 between the first driving sub-circuit 110 and the second driving sub-circuit 120, costs are saved, and the power-off timing of various signals is realized at the same time.

[0102] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0104] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “set” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0105] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A driving device for a display panel, characterized in that, include: The module includes a level conversion module, a timing signal input module connected in parallel, and a power-off signal detection module. The timing signal input module is used to generate timing reference signals to drive the display panel for display. The power-off signal detection module is used to detect the power-off signal that drives the display panel to stop displaying; The level conversion module is connected to the timing signal input module and is used to generate a timing control signal corresponding to the timing reference signal under the control of the timing reference signal. The timing control signal includes a high voltage signal and a low voltage signal. The level conversion module is also connected to the power-off signal detection module and is used to generate a power-off control signal under the control of the power-off signal. The power-off control signal is the high voltage signal corresponding to the timing control signal in the normal display state. The power-off control signal is the timing control signal corresponding to the pulled-high timing reference signal obtained when the power-off signal is detected.

2. The driving device for the display panel according to claim 1, characterized in that, The level conversion module includes a first conversion unit, a second conversion unit, and a conversion control unit. The first end of the first conversion unit is connected to the first power supply end, the second end of the first conversion unit is connected to the signal output end, and the control end of the first conversion unit is connected to the conversion control unit. The first conversion unit is used to provide the voltage of the first power supply end to the signal output end under the control of the conversion control unit. The first end of the second conversion unit is connected to the second power supply terminal, the second end of the second conversion unit is connected to the signal output terminal, and the control terminal of the second conversion unit is connected to the conversion control unit. The second conversion unit is used to provide the voltage of the second power supply terminal to the signal output terminal under the control of the conversion control unit.

3. The driving device for the display panel according to claim 2, characterized in that, The conversion control unit includes a first control sub-circuit and a second control sub-circuit connected in parallel. The first terminal of the first control sub-circuit is connected to the control terminal of the first conversion unit and the control terminal of the second conversion unit. The second terminal of the first control sub-circuit is connected to the first level voltage terminal. The control terminal of the first control sub-circuit is connected to the timing signal input module. The first control sub-circuit is used to provide the voltage of the first level voltage terminal to one of the first conversion unit and the second conversion unit under the control of the timing reference signal. The second control sub-circuit is connected to the second level voltage terminal, and the second control sub-circuit is used to provide the voltage of the second level voltage terminal to the other of the first conversion unit and the second conversion unit.

4. The driving device for the display panel according to claim 3, characterized in that, The first power supply terminal is a high voltage signal. The first terminal of the power-off signal detection module is connected to the third level voltage terminal. The second terminal of the power-off signal detection module is connected to the conversion control unit. The control terminal of the power-off signal detection module is connected to the power-off control line that provides the power-off signal. The power-off signal detection module is used to provide the voltage of the third level voltage terminal to the conversion control unit when the power-off signal is detected. The conversion control unit is also used to provide the voltage of the first level voltage terminal to the first conversion unit under the voltage control of the third level voltage terminal.

5. The driving device for the display panel according to claim 4, characterized in that, The power-off signal is the power-off of the signal line providing the power-off signal, and the power-off control signal is the power-off of the signal output terminal following the high-voltage signal of the first power supply terminal.

6. The driving device for the display panel according to claim 4, characterized in that, The first conversion unit includes a first transistor, the second conversion unit includes a second transistor, and the first control sub-circuit includes a third transistor. The first terminal of the first transistor is connected to the first power supply terminal, the second terminal of the first transistor is connected to the signal output terminal, and the control terminal of the first transistor is connected to the second terminal of the third transistor and the second voltage level terminal. The first terminal of the second transistor is connected to the second power supply terminal, the second terminal of the second transistor is connected to the signal output terminal, and the control terminal of the second transistor is connected to the second terminal of the third transistor and the second voltage level terminal. The first terminal of the third transistor is connected to the first voltage level terminal, and the control terminal of the third transistor is connected to the timing signal input module and the power-off signal detection module.

7. The driving device for the display panel according to claim 6, characterized in that, The second voltage level terminal shares the same voltage signal as the first power supply terminal, the first terminal of the third transistor is grounded, and the second control sub-circuit includes a current-limiting resistor connected to the second voltage level terminal.

8. The driving device for the display panel according to claim 6, characterized in that, The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

9. The driving device for the display panel according to claim 6, characterized in that, The power-off signal detection module includes a fourth transistor, the first terminal of which is connected to a third voltage level terminal, the control terminal of which is connected to the power-off control line, and the second terminal of which is connected to the control terminal of the third transistor.

10. The driving device for the display panel according to claim 9, characterized in that, The third transistor is an N-type transistor, the fourth transistor is a P-type transistor, and the high-level voltage value of the timing reference signal is equal to the voltage value of the third-level voltage terminal.

11. The driving device for the display panel according to claim 2, characterized in that, The timing of the timing control signal is the same as that of the timing reference signal. The voltage value of the first power supply terminal is greater than the high-level voltage value of the timing reference signal, and the voltage value of the second power supply terminal is greater than the low-level voltage value of the timing reference signal.

12. A driving method for a display panel, characterized in that, The method, applied to a driving device for a display panel as described in any one of claims 1-11, comprises: When a power-off signal is detected, the level conversion module generates a power-off control signal corresponding to the power-off signal, and the power-off control signal is a high-voltage signal corresponding to the timing control signal; When no power-off signal is detected, the level conversion module generates a timing control signal corresponding to the timing reference signal, the timing control signal including a high voltage signal and a low voltage signal.

13. A display device, characterized in that, The device includes a gate driving circuit and at least one driving device for a display panel as described in any one of claims 1-11, connected to the gate driving circuit.

14. The display device according to claim 13, characterized in that, The gate driving circuit includes a first gate driving sub-circuit for driving the odd-numbered pixel rows of the display panel and a second gate driving sub-circuit for driving the even-numbered pixel rows of the display panel. The first gate driving sub-circuit includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the first gate driving sub-circuit is provided with a first frame start signal. The second gate driving sub-circuit includes a plurality of cascaded GOA units, wherein an initial stage GOA unit on the second gate driving sub-circuit is provided with a second frame start signal.

15. The display device according to claim 14, characterized in that, The driving device includes a first driving sub-circuit connected to the first gate driving sub-circuit. The first driving sub-circuit is used to generate a first frame start reference signal, a first frame start signal corresponding to the first frame start reference signal, and a first power-off control signal corresponding to the first frame start signal. and / or The driving device includes a second driving sub-circuit connected to the second gate driving sub-circuit. The second driving sub-circuit is used to generate a second frame start reference signal, a second frame start signal corresponding to the second frame start reference signal, and a second power-off control signal corresponding to the second frame start signal.

16. The display device according to claim 15, characterized in that, The driving device includes a first driving sub-circuit and a second driving sub-circuit, and the first driving sub-circuit and the second driving sub-circuit share the same power-off signal detection module.

17. The display device according to claim 13, characterized in that, The display device includes a display panel and a driving circuit board. The driving circuit board includes a timing controller and a level converter. The timing signal input module is disposed on the timing controller, and the level converter module and the power-off signal detection module are disposed on the level converter.

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