A dual-gate controlled low on-resistance heterojunction field effect transistor and a manufacturing method thereof

Abstract

The present application provides a dual-gate controlled low on-resistance heterojunction field effect transistor and a manufacturing method thereof, comprising: a substrate, a superjunction structure, a gate structure, a channel structure, a first electrode and a second electrode. The superjunction structure includes a drift layer, and the drift layer is N-type doped. The gate structure includes a barrier layer, a gate cap layer, a first gate and a second gate. The barrier layer and the drift layer are in contact to form a two-dimensional electron gas conductive channel. When forward-conducting, the two-dimensional electron gas conductive channel can reduce the forward on-resistance, increase the forward on-current, and improve the device performance. The gate cap layer is P-type doped. When the transistor is in the off state, the gate cap layer is used to deplete the electrons in the two-dimensional electron gas conductive channel to achieve high withstand voltage performance. The second gate is located on the side surface of the gate cap layer away from the substrate, so that the first gate and the second gate can respectively control the switching state of the transistor, improve the gate reliability, and then improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a dual-gate controlled low on-resistance heterojunction field effect transistor and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor-related technologies, ultra-wide bandgap semiconductor materials are currently being used in a variety of fields with their superior optical and electrical properties. For example, in the fields of geothermal energy production and oil and gas extraction, semiconductor devices made from ultra-wide bandgap semiconductor materials can help achieve higher drilling speeds and lower failure rates. Another example is that semiconductor devices made from ultra-wide bandgap semiconductor materials under high temperature conditions can work in aluminum plants, steel plants, and coal-fired and gas-fired power plants at higher temperatures, thereby improving the energy efficiency of industrial processes.

[0003] Currently, ultra-wide bandgap semiconductor materials can be used to manufacture superjunction-based heterojunction field effect transistors (High Electron Mobility Transistor, HEMT), see Figure 1 However, the current HEMT still has factors that affect the device performance, such as large forward resistance and low gate reliability. Therefore, how to improve the performance of HEMT is an urgent problem to be solved. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a dual-gate controlled low on-resistance heterojunction field effect transistor and a manufacturing method thereof. The dual-gate controlled low on-resistance heterojunction field effect transistor adopts dual-gate control to improve gate reliability, and an additional barrier layer is arranged to form a heterojunction with the N-type doped drift layer below to produce a polarization effect, forming a two-dimensional electron gas conductive channel, thereby reducing the forward on-resistance and further improving the device performance.

[0005] To achieve the above purpose, this application has the following technical solutions:

[0006] The present application provides a dual-gate controlled low on-resistance heterojunction field effect transistor, the dual-gate controlled low on-resistance heterojunction field effect transistor comprising:

[0007] A substrate and a super junction structure located on a surface of one side of the substrate, wherein the super junction structure includes a drift layer, the substrate and the drift layer are N-type doped, and the material of the substrate and the drift layer includes gallium or aluminum;

[0008] A gate structure, wherein the gate structure is located on a side surface of the super junction structure away from the substrate, and projections of the gate structure and the drift layer on the substrate overlap; the gate structure comprises a barrier layer, a gate cap layer, a first gate and a second gate, the barrier layer and the drift layer are in contact to form a two-dimensional electron gas conductive channel, the gate cap layer is located on a side surface of the barrier layer away from the substrate, the gate cap layer is P-type doped, the second gate is located on a side surface of the gate cap layer away from the substrate, the material of the barrier layer comprises aluminum, and the material of the gate cap layer is the same as the material of the drift layer;

[0009] A channel structure, wherein the channel structure is located on both sides of the gate structure along a direction parallel to the surface of the substrate;

[0010] A first electrode and a second electrode, wherein the first electrode is disposed on a surface of the substrate away from the super junction structure, and the second electrode covers the channel structure.

[0011] Optionally, the material of the substrate and the drift layer is gallium oxide, gallium nitride, gallium arsenide or aluminum nitride, and the material of the barrier layer is aluminum gallium oxide, aluminum gallium nitride or aluminum gallium arsenic.

[0012] Optionally, when the material of the substrate and the drift layer is gallium oxide, gallium nitride or gallium arsenide, the material of the barrier layer is also aluminum nitride.

[0013] Optionally, it also includes an insulating layer, which is arranged between the gate structure and the channel structure. The first gate penetrates a portion of the thickness of the insulating layer. The first gate is isolated from the channel structure by the insulating layer. The insulating layer is also arranged on the gate cap layer and the side walls of the second gate.

[0014] Optionally, the channel structure includes at least one channel stack, the channel stack includes a first layer and a second layer, the second layer is located on a side of the first layer away from the substrate, the material of the first layer is the same as that of the drift layer, and the material of the second layer is the same as that of the barrier layer.

[0015] Optionally, the second electrode at least covers a sidewall of the channel stack away from the gate structure.

[0016] Optionally, the channel structure includes a first channel stack and a second channel stack, and the second channel stack is located on a side of the first channel stack away from the substrate.

[0017] Optionally, projections of the channel structure and the drift layer on the substrate partially overlap.

[0018] Optionally, the super junction structure further includes an epitaxial layer, and along a direction parallel to the surface of the substrate, the epitaxial layer is located on both sides of the drift layer, and projections of the epitaxial layer and the channel structure on the substrate overlap;

[0019] The epitaxial layer includes a first epitaxial layer and a second epitaxial layer. The second epitaxial layer is located on a side of the first epitaxial layer away from the substrate. The first epitaxial layer and the second epitaxial layer are made of the same material as the substrate. The second epitaxial layer is P-type doped.

[0020] The present application provides a method for manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor, comprising:

[0021] A super junction structure is formed on one side of the substrate, wherein the super junction structure includes a drift layer, the substrate and the drift layer are N-type doped, and the material of the substrate and the drift layer includes gallium or aluminum;

[0022] A gate structure and a channel structure are formed on a side of the super junction structure away from the substrate, and projections of the gate structure and the drift layer on the substrate overlap; the gate structure includes a barrier layer, a gate cap layer, a first gate and a second gate, the barrier layer and the drift layer are in contact to form a two-dimensional electron gas conductive channel, the gate cap layer is located on a side surface of the barrier layer away from the substrate, the gate cap layer is P-type doped, the second gate is located on a side surface of the gate cap layer away from the substrate, the material of the barrier layer includes aluminum, and the material of the gate cap layer is the same as that of the drift layer; along a direction parallel to the surface of the substrate, the channel structure is located on both sides of the gate structure;

[0023] A first electrode and a second electrode are formed, wherein the first electrode is disposed on a surface of the substrate away from the super junction structure, and the second electrode covers the channel structure.

[0024] The present application provides a dual-gate controlled low on-resistance heterojunction field effect transistor, comprising: a substrate, a superjunction structure, a gate structure, a channel structure, a first electrode and a second electrode, wherein the first electrode is arranged on a side surface of the substrate away from the superjunction structure, and the second electrode covers the channel structure, and the first electrode and the second electrode are used to apply a voltage to turn on the dual-gate controlled low on-resistance heterojunction field effect transistor. The superjunction structure is located on one side surface of the substrate, and the superjunction structure includes a drift layer, and the substrate and the drift layer are N-type doped, so that after the dual-gate controlled low on-resistance heterojunction field effect transistor is turned on, the N-type doped substrate and the drift layer can be used for conduction. The materials of the substrate and the drift layer include gallium or aluminum, that is, the substrate and the drift layer are ultra-wide bandgap semiconductor materials including gallium or aluminum. The gate structure is located on a side surface of the superjunction structure away from the substrate, and the projections of the gate structure and the drift layer on the substrate overlap, that is, the gate structure is located directly above the drift layer, so that the entire dual-gate controlled low on-resistance heterojunction field effect transistor can be controlled. The gate structure includes a barrier layer, a gate cap layer, a first gate and a second gate. The material of the barrier layer includes aluminum. The barrier layer and the drift layer contact to produce a polarization effect, which can form a two-dimensional electron gas conductive channel. In this way, when the dual-gate controlled low on-resistance heterojunction field effect transistor is forward-conducted, the two-dimensional electron gas conductive channel can reduce the forward on-resistance and increase the forward on-current, thereby improving the device performance. The gate cap layer is located on the side surface of the barrier layer away from the substrate. The material of the gate cap layer is the same as that of the drift layer. The gate cap layer is P-type doped. In this way, when the dual-gate controlled low on-resistance heterojunction field effect transistor is in the off state, the gate cap layer can be used to deplete the electrons in the two-dimensional electron gas conductive channel, thereby achieving the high withstand voltage performance of the dual-gate controlled low on-resistance heterojunction field effect transistor. The second gate is located on the side surface of the gate cap layer away from the substrate, so that the first gate and the second gate can respectively control the switching state of the dual-gate controlled low on-resistance heterojunction field effect transistor, improve the gate reliability, and then improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic structural diagram of a superjunction-based heterojunction field effect transistor is shown;

[0027] Figure 2 A schematic structural diagram of a semiconductor device based on a super junction is shown;

[0028] Figure 3A schematic cross-sectional structure diagram of a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application is shown;

[0029] Figure 4 A schematic cross-sectional structure diagram of another dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application is shown;

[0030] Figure 5 A schematic diagram of a three-dimensional structure of a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application is shown;

[0031] Figure 6 A schematic flow chart of a method for manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application is shown;

[0032] Figure 7-Figure 15 A schematic structural diagram of manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor according to a manufacturing method of a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0035] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of this application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0036] Currently, ultra-wide bandgap semiconductor materials can be used to manufacture power devices, which need to have a higher withstand voltage and a lower on-resistance. However, as the withstand voltage increases, the on-resistance also increases, resulting in an increase in the switching loss and conduction loss of the power device, which increases the power consumption of the power device and ultimately reduces energy efficiency. The power consumption caused by the switching loss and conduction loss of the power device is released as heat energy, causing the local temperature of the power device to rise rapidly, which can burn the power device in a short time and cause it to fail permanently. This greatly limits the application of power devices in the high-voltage field.

[0037] The invention of the super junction (SJ) structure breaks through the theoretical limit of traditional power devices and alleviates the contradiction between the withstand voltage and on-resistance of power devices. The super junction structure refers to the use of a higher concentration N column region and a P column region to replace a single conductive type low concentration withstand voltage layer. Figure 2 As shown. When the power device based on the superjunction structure works in reverse, the N-column region and the P-column region in the voltage-resistant layer form a reverse-biased lateral PN junction. Since the width of the N-column region and the P-column region of the superjunction structure is small, they are completely depleted under a lower reverse bias, and the electric lines emitted by the ionized donors in the N-column region almost all terminate at the ionized acceptors in the P-column region. Therefore, when the voltage-resistant layer is completely depleted, the superjunction structure can be approximately equivalent to a longitudinally grounded and fully depleted lateral PN junction and a vertical diode with the voltage-resistant layer being an intrinsic semiconductor layer. Therefore, combining ultra-wide bandgap semiconductor materials with superjunction structures can achieve higher breakdown voltages while optimizing the forward on-resistance of power devices.

[0038] Combining ultra-wide bandgap semiconductor materials with superjunction structures can produce superjunction-based heterojunction field-effect transistors (High Electron Mobility Transistor, HEMT), refer to Figure 1 As shown. In HEMT, the gate is usually a MIS gate structure composed of metal-insulating layer-ultra-wide bandgap semiconductor material. The MIS gate structure is used to control the channel, which can reduce the off-state leakage of the device. However, during forward conduction, since the MIS gate structure requires etching process during production, it will lead to a large number of high-density interface defects. These high-density interface defects exist at the interface between the insulating layer and the ultra-wide bandgap semiconductor. Under long-term switching stress, the threshold voltage (V TH ) offset, saturation output current (I DS ) is reduced and the on-resistance (R ON ) degradation, which causes serious degradation of the device's forward conduction and off-state withstand voltage in the short term, and affects the reliability, stability and compatibility of the device's gate in the long term.

[0039] In other words, the current HEMT has factors that affect device performance, such as large forward on-resistance and low gate reliability. Therefore, how to improve the performance of HEMT is an urgent problem to be solved.

[0040] Based on this, this application will further optimize the design of the device structure based on ultra-wide bandgap semiconductor materials and superjunction structures, and propose a dual-gate controlled low on-resistance heterojunction field effect transistor, further optimizing and reducing the forward on-resistance under the same breakdown voltage conditions, thereby further improving the Baliga figure of merit of the device and laying the foundation for the market application of wide bandgap material devices.

[0041] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0042] refer to Figure 3 As shown, it is a schematic diagram of the structure of a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application. The dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application includes: a substrate (sub) 110, a super junction structure 200, a gate structure 300, a channel structure 400, a first electrode 510 and a second electrode 520.

[0043] In an embodiment of the present application, the super junction structure 200 is located on one side surface of the substrate 110, and the super junction structure 200 may include a drift layer 210. The materials of the substrate 110 and the drift layer 210 are the same, so that the bonding between the substrate 110 and the drift layer 210 is better and there are fewer defects, thereby improving the performance of the device. In addition, both the substrate 110 and the drift layer 210 are N-type doped, and the carrier concentration is increased by N-type doping, and the on-resistance is reduced, thereby achieving a smaller forward on-resistance. The materials of the substrate 110 and the drift layer 210 include gallium or aluminum, and the compounds formed by gallium or aluminum are generally ultra-wide bandgap semiconductor materials, that is, they have a higher bandgap width and can be used as high-voltage resistant materials for power devices.

[0044] As a possible implementation, the materials of the substrate 110 and the drift layer 210 are gallium oxide (Ga 2 O 3 or GaO), gallium nitride (GaN), gallium arsenide (GaAs), or aluminum nitride (AlN).

[0045] In some embodiments, the doping concentration of the drift layer 210 is generally less than the doping concentration of the substrate 110. For example, the doping concentration of the drift layer 210 may be 2E16-2E17 cm -3 The doping concentration of the substrate 110 may be 2E18-2E19cm -3 .

[0046] As an example, the drift layer 210 may be formed by an epitaxial process, and the epitaxial process may be a hydride vapor phase epitaxy (HVPE) process.

[0047] In the embodiment of the present application, the gate structure 300 is located on the surface of the super junction structure 200 away from the substrate 110. The projections of the gate structure 300 and the drift layer 210 on the substrate 110 overlap, that is, the gate structure 300 is located directly above the drift layer 210, so that the control of the entire dual-gate controlled low on-resistance heterojunction field effect transistor can be achieved.

[0048] The gate structure 300 includes a barrier layer 310, a gate cap layer 320, a first gate 330 and a second gate 340. The barrier layer 310 is located on a surface of the drift layer 210 away from the substrate 110. The material of the barrier layer 310 is different from that of the drift layer 210. The barrier layer 310 and the drift layer 210 are in contact to form a heterojunction, and a two-dimensional electron gas (2DEG) conductive channel is formed through a polarization effect. Figure 3 or Figure 4 At the middle red dotted line, the two-dimensional electron gas conductive channel can increase the carrier concentration of the drift layer 210. When forward conduction occurs, a large number of electrons will pass through the drift layer 210, thereby reducing the forward conduction resistance and increasing the forward conduction current. The forward characteristics of the device are enhanced, thereby improving the device performance.

[0049] The material of the barrier layer 310 includes aluminum. As a possible implementation, the material of the barrier layer 310 is aluminum gallium oxide (AlGaO), aluminum gallium nitride (AlGaN) or aluminum gallium arsenic (AlGaAs). The barrier layer 310 can be formed by an epitaxial process.

[0050] As an example, when the material of the drift layer 210 is gallium oxide, the material of the barrier layer 310 is aluminum gallium oxide.

[0051] As another example, when the material of the drift layer 210 is gallium nitride, the material of the barrier layer 310 is aluminum gallium nitride.

[0052] As another example, when the material of the drift layer 210 is gallium arsenide, the material of the barrier layer 310 is aluminum gallium arsenide.

[0053] In some embodiments, when the material of the drift layer 210 is gallium oxide, gallium nitride or gallium arsenide, the material of the barrier layer 310 can also be aluminum nitride. Aluminum nitride and gallium oxide can form a heterojunction. The two-dimensional electron gas conductive channel formed by the polarization effect has a higher carrier concentration than the two-dimensional electron gas conductive channel formed when the material of the barrier layer 310 is aluminum gallium oxygen, aluminum gallium nitrogen or aluminum gallium arsenic, which can further reduce the forward on-resistance and further improve the device performance.

[0054] The gate cap layer 320 is located on the surface of the barrier layer 310 away from the substrate 110, that is, the gate cap layer 320 is located above the barrier layer 310. The material of the gate cap layer 320 is the same as that of the drift layer 210. The gate cap layer 320 is P-type doped, and the drift layer 210 is N-type doped. In this way, when the dual-gate controlled low on-resistance heterojunction field effect transistor is in the off state, the gate cap layer 320 can be used to deplete the electrons in the two-dimensional electron gas conductive channel, thereby achieving high voltage resistance performance of the dual-gate controlled low on-resistance heterojunction field effect transistor.

[0055] As an example, the material of the gate cap layer 320 is gallium oxide (Ga 2O 3 ), gallium nitride (GaN), gallium arsenide (GaAs) or aluminum nitride (AlN). The gate cap layer 320 may be formed by an epitaxial process.

[0056] The first gate 330 can independently control the switching of the device. The first gate 330 and the barrier layer 310 are not in contact with each other as much as possible. Specifically, the first gate 330 can be separated from the sidewall of the barrier layer 310 by an insulating material, such as an insulating layer 610. Figure 3 or Figure 4 shown.

[0057] The second gate 340 can also control the switching of the device. The second gate 340 is located on a surface of the gate cap layer 320 away from the substrate 110 , that is, the second gate 340 is located above the gate cap layer 320 .

[0058] As an example, the material of the first gate 330 and the second gate 340 may be a metal material, such as Ni or Au.

[0059] In the embodiment of the present application, the first gate 330 can control whether the channel structure 400 is turned on. The channel structure 400 is located on both sides of the gate structure 300 along the direction parallel to the surface of the substrate 110, specifically along the connecting direction of the two side walls where the barrier layer 310 and the first gate 330 contact.

[0060] In the embodiment of the present application, the first electrode 510 is disposed on a side surface of the substrate 110 away from the super junction structure 200, and the second electrode 520 covers the channel structure 400. The first electrode 510 and the second electrode 520 are used to apply a voltage to turn on the device. The second electrode 520 may cover a side surface of the channel structure 400 away from the substrate 110 and a sidewall of the channel structure 400.

[0061] In some embodiments, the first electrode 510 may be a source electrode, and the second electrode 520 may be a drain electrode. The materials of the first electrode 510 and the second electrode 520 may be materials with good electrical conductivity, such as metal materials.

[0062] As an example, the material of the first electrode 510 and the second electrode 520 may be titanium, aluminum or gold.

[0063] In the embodiment of the present application, the dual-gate controlled low on-resistance heterojunction field effect transistor further includes an insulating layer 610, which is disposed between the gate structure 300 and the channel structure 400 to prevent the gate structure 300 and the channel structure 400 from directly contacting each other. Accordingly, the insulating layer 610 also isolates the first gate 330 from the channel structure 400. The first gate 330 penetrates a portion of the thickness of the insulating layer 610, and the difference between the extension length of the first gate 330 in the insulating layer 610 and the thickness of the channel structure 400 is less than a threshold value, so that the conduction of the channel structure 400 can be controlled by the first gate 330. In addition to the portion of the insulating layer 610 that penetrates a portion of the thickness, the first gate 330 also includes a portion disposed on the surface of the insulating layer 610 on one side away from the substrate 110, so as to facilitate electrical extraction.

[0064] The insulating layer 610 covers the barrier layer 310 and the gate cap layer 320 on the side surface away from the substrate 110. The insulating layer 610 can also be arranged on the side walls of the gate cap layer 320 and the second gate 340, so that the gate cap layer 320 and the second gate 340 can be isolated from the first gate 330 respectively by the insulating layer 610.

[0065] As an example, the material of the insulating layer 610 may be silicon oxide.

[0066] In practical applications, along the connection direction of the side walls of the barrier layer 310 and the first gate 330, the width of the gate cap layer 320 is smaller than the width of the barrier layer 310, and the width of the second gate 340 is smaller than the width of the gate cap layer 320. Figure 3 or Figure 4 shown.

[0067] In the embodiment of the present application, the channel structure 400 may include at least one channel stack 410. Figure 3 or Figure 4 As shown. The channel stack 410 is used to form a conductive channel. Specifically, the channel stack 410 includes a first layer 411 and a second layer 412. The second layer 412 is located on the side of the first layer 411 away from the substrate 110. The material of the first layer 411 is the same as that of the drift layer 210, and the material of the second layer 412 is the same as that of the barrier layer 310. In other words, a heterojunction is formed between the first layer 411 and the second layer 421, and a two-dimensional electron gas conductive channel is formed through the polarization effect.

[0068] As an example, the material of the first layer 411 is gallium oxide, and the material of the second layer 412 is aluminum gallium oxide.

[0069] As another example, the material of the first layer 411 is gallium nitride, and the material of the second layer 412 is aluminum gallium nitride.

[0070] As another example, the material of the first layer 411 is gallium arsenide, and the material of the second layer 412 is aluminum gallium arsenide.

[0071] As a possible implementation, refer to Figure 3 As shown, the channel structure 400 may include a channel stack 410 , and the channel stack 410 includes a first layer 411 and a second layer 412 . In this case, the first layer 411 and the second layer 412 form a two-dimensional electron gas conductive channel.

[0072] As another possible implementation, refer to Figure 4 As shown, the channel structure 400 may include two channel stacks 410, namely a first channel stack 420 and a second channel stack 430. The second channel stack 430 is located on the side of the first channel stack 420 away from the substrate 110, that is, the second channel stack 430 is located above the first channel stack 420. The first channel stack 420 and the second channel stack 430 each include a first layer 411 and a second layer 412, so that the first channel stack 420 and the second channel stack 430 each form a two-dimensional electron gas conductive channel, which can provide more conductive channels, thereby improving the performance of the entire device.

[0073] In the embodiment of the present application, in order to realize the electron flow between the first electrode 510 and the second electrode 520, the second electrode 520 at least covers the side wall of the channel stack 410 away from the gate structure 300, referring to Figure 3 or Figure 4 As shown, that is, the second electrode 520 covers at least one side of the interface between the first layer 411 and the second layer 412 , so that the second electrode 520 can provide sufficient electrons for the two-dimensional electron gas conductive channel formed by the first layer 411 and the second layer 412 .

[0074] In the embodiment of the present application, the projections of the channel structure 400 and the drift layer 210 on the substrate 110 partially overlap, so that the electrons in the channel structure 400 can smoothly enter the drift layer 210, thereby realizing current flow.

[0075] Specifically, when the first gate 330 and the second gate 340 apply a forward bias voltage, the electrons flow from the second electrode 520 through the two-dimensional electron gas conductive channel between the first layer 411 and the second layer 412 in the channel structure 400, and then flow to the bottom through the two-dimensional electron gas conductive channel between the barrier layer 310 and the drift layer 210, that is, the flow direction of the electrons is connected by two two-dimensional electron gas conductive channels, and finally flow to the first electrode 510 through the drift layer 210. Since the barrier layer 310, the gate cap layer 320 and the second gate 340 are introduced into the gate structure 300, the barrier layer 310 and the drift layer 210 form a high-concentration two-dimensional electron gas conductive channel, so a large number of electrons pass through the N-type doped drift layer 210, the carrier concentration increases, the forward on-resistance decreases, and the forward characteristics of the device are enhanced. When the device is in the off-state withstand voltage, it is only necessary to turn off the second gate 340 or apply a negative voltage to the second gate 340 to deplete the two-dimensional electron gas below, so as to achieve a high withstand voltage. Therefore, under the condition that the withstand voltage remains basically unchanged, it is possible to eliminate the gate reliability problem of the MIS gate due to high-density interface traps, and to introduce a two-dimensional electron gas conductive channel to reduce the forward on-resistance of the device and optimize the forward characteristics of the device.

[0076] In the embodiment of the present application, the super junction structure 200 further includes an epitaxial layer 220, which is located on both sides of the drift layer 210 along a direction parallel to the surface of the substrate 110, that is, along a line connecting the side walls of the barrier layer 310 and the first gate 330, and the epitaxial layer 220 and the drift layer 210 constitute the super junction structure 200. The projections of the epitaxial layer 220 and the channel structure 400 on the substrate 110 overlap.

[0077] The epitaxial layer 220 includes a first epitaxial layer 221 and a second epitaxial layer 222. The second epitaxial layer 222 is located on a side of the first epitaxial layer 221 away from the substrate 110, that is, the second epitaxial layer 222 is above the first epitaxial layer 221. The materials of the first epitaxial layer 221 and the second epitaxial layer 222 are the same as the substrate 110, the second epitaxial layer 222 is P-type doped, and the first epitaxial layer 221 is an undoped (UID) material.

[0078] As an example, the material of the substrate 110 is gallium oxide, the material of the first epitaxial layer 221 is undoped gallium oxide, showing N-type doping characteristics, and the second epitaxial layer 222 is P-type doped gallium oxide.

[0079] In practical applications, a passivation layer 620 may be further disposed between the second electrode 520 and the first gate 330. Figure 3 or Figure 4As shown, the passivation layer 620 is arranged on the side surface of the channel structure 400 away from the substrate 110, the passivation layer 620 and the second electrode 520 cover the side wall contact of the side surface of the channel structure 400 away from the substrate 110, and the passivation layer 620 is also in contact with the side wall of the first gate 330 covering the surface of the insulating layer 610 close to the second electrode 520.

[0080] As an example, the material of the passivation layer 620 may be silicon nitride.

[0081] refer to Figure 5 The figure shows a three-dimensional structure diagram of a dual-gate controlled low on-resistance heterojunction field effect transistor using gallium oxide as an example. In this case, the substrate (sub) is N-type doped gallium oxide, and the drift layer (Drift) is N-type doped gallium oxide. Since the doping concentration of the substrate is greater than that of the drift layer, the substrate can utilize N + The first gate is represented by Gate1, and the second gate is represented by Gate2.

[0082] It can be seen that the dual-gate controlled low on-resistance heterojunction field effect transistor provided in the embodiment of the present application can realize the forward and reverse characteristics of the device when a single gate is used by controlling each gate separately, which is more flexible, and replaces the original MIS gate structure with the current gate structure including a barrier layer, a gate cap layer, a first gate and a second gate, thereby eliminating the reliability problems such as threshold voltage offset, saturation output current reduction and on-resistance degradation caused by the MIS gate structure. A new two-dimensional electron gas conductive channel is formed in the upper part of the drift layer by using the barrier layer and the drift layer. When the device is forward-conducted, the two-dimensional electron gas conductive channel can significantly reduce the device on-resistance compared to the N-type channel of the drift layer with only N-type doping, thereby improving the device saturation current and energy efficiency.

[0083] Based on the dual-gate controlled low on-resistance heterojunction field effect transistor provided in the above embodiments, the present application also provides a method for manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor, referring to Figure 6 , which is a schematic flow chart of a method for manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor provided in an embodiment of the present application.

[0084] The manufacturing method of the dual-gate controlled low on-resistance heterojunction field effect transistor provided in the embodiment of the present application comprises the following steps:

[0085] S601, forming a super junction structure 200 on one side of the substrate 110, referring to Figure 7-Figure 9 shown.

[0086] In an embodiment of the present application, the super junction structure 200 includes a drift layer 210 and an epitaxial layer 220, the substrate 110 and the drift layer 210 are N-type doped, and the materials of the substrate 110 and the drift layer 210 include gallium or aluminum. The epitaxial layer 220 is located on both sides of the drift layer 210. The epitaxial layer 220 includes a first epitaxial layer 221 and a second epitaxial layer 222. The second epitaxial layer 222 is located on a side of the first epitaxial layer 221 away from the substrate 110, that is, the second epitaxial layer 222 is above the first epitaxial layer 221. The materials of the first epitaxial layer 221 and the second epitaxial layer 222 are the same as those of the substrate 110, the second epitaxial layer 222 is P-type doped, and the first epitaxial layer 221 is an undoped (UID) material.

[0087] The specific process steps for forming the super junction structure 200 on one side of the substrate 110 are as follows:

[0088] An epitaxial layer 220 may be first formed on the substrate 110. Specifically, a first epitaxial layer 221 and a second epitaxial layer 222 may be formed by an epitaxial process. Figure 7 shown.

[0089] Then, the first epitaxial layer 221 and the second epitaxial layer 222 are etched to form the first groove 101. Specifically, BCl 3 The first epitaxial layer 221 and the second epitaxial layer 222 are dry-etched by using Ar gas until the etching reaches the surface of the substrate 110. Figure 8 shown.

[0090] A drift layer 210 is formed in the first groove 101. Specifically, the drift layer 210 can be grown in the first groove 101 by using an epitaxial process. Fig. 9 shown.

[0091] S602, forming a gate structure 300 and a channel structure 400 on a side of the super junction structure 200 away from the substrate 110, referring to Figure 10-Figure 15 shown.

[0092] In the embodiment of the present application, after forming the super junction structure 200, a gate structure 300 and a channel structure 400 may be formed on a side of the super junction structure 200 away from the substrate 110. The projections of the gate structure 300 and the drift layer 210 on the substrate 110 overlap. The gate structure 300 includes a barrier layer 310, a gate cap layer 320, a first gate 330, and a second gate 340. The barrier layer 310 and the drift layer 210 are in contact to form a two-dimensional electron gas conductive channel. The gate cap layer 320 is located on a side surface of the barrier layer 310 away from the substrate 110. The gate cap layer 320 is P-type doped. The second gate 340 is located on a side surface of the gate cap layer 320 away from the substrate 110. The first gate 330 is in contact with the barrier layer 310. The material of the barrier layer 310 includes aluminum. The material of the gate cap layer 320 is the same as that of the drift layer 210. Along the direction parallel to the surface of the substrate 110, the channel structure 400 is located on both sides of the gate structure 300.

[0093] The specific process steps for forming the gate structure 300 and the channel structure 400 on one side of the super junction structure 200 are as follows:

[0094] The first layer 411 of the channel stack 410 may be formed on a surface of the super junction structure 200 away from the substrate 110, and then the first layer 411 is etched to form the second groove 102, referring to Fig.10 As shown, 411 can be formed by using an epitaxial process.

[0095] Then, a barrier layer 310 is formed in the second groove 102, and a second layer 412 of the channel stack 410 made of the same material as the barrier layer 310 is formed. Specifically, the barrier layer 310 and the second layer 412 can be formed by an epitaxial process. Fig.11 After the barrier layer 310 and the second layer 412 are formed, the portion of the second layer 412 overlapping the barrier layer 310 may form a gate cap layer 320 .

[0096] The barrier layer 310 and the gate cap layer 320 are selectively etched to form a third groove 103 between the barrier layer 310 and the gate cap layer 320 and the first layer 411 and the second layer 412 of the channel stack 410, respectively. Fig.12 shown.

[0097] An insulating material is filled in the third groove 103 to form an insulating layer 610, which covers the barrier layer 310 and the gate cap layer 320, and the insulating layer 610 can also cover a portion of the surface of the channel structure 400 away from the substrate 110. A passivation layer 620 can also be formed on the channel structure 400, and the passivation layer 620 covers a portion of the surface of the channel structure 400 away from the substrate 110 and covers a portion of the insulating layer 610, Fig.13 shown.

[0098] The insulating layer 610 is etched by a dry etching process to form a fourth groove 104 and a fifth groove 105 that penetrate a portion of the insulating layer 610, respectively. The fourth groove 104 does not expose the side wall of the barrier layer 310, and the fifth groove 105 exposes a surface of the gate cap layer 320 away from the substrate 110. The depth of the fourth groove 104 is greater than the depth of the fifth groove 105. Fig.14 shown.

[0099] Metal materials are filled in the fourth groove 104 and the fifth groove 105 to form a first gate 330 and a second gate 340, respectively. Fig.15 shown.

[0100] S603, forming a first electrode 510 and a second electrode 520, referring to Figure 3 shown.

[0101] In the embodiment of the present application, the first layer 411 and the second layer 412 of the channel stack 410 of a partial width may be etched away. Specifically, the sidewall of the channel stack 410 that is not in contact with the gate structure 300 may be used as the starting point to etch the channel stack 410 of a partial width, and then the second electrode 520 is formed on the sidewall and surface of the channel stack 410. The first electrode 510 is formed on the surface of the side of the substrate 110 away from the super junction structure 200, referring to Figure 3 shown.

[0102] As an example, the material of the first electrode 510 and the second electrode 520 may be titanium, aluminum or gold.

[0103] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the structural embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the structural embodiment.

[0104] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A dual-gate controlled low on-resistance heterojunction field effect transistor, characterized in that: The dual-gate controlled low on-resistance heterojunction field effect transistor comprises: A substrate and a super junction structure located on a surface of one side of the substrate, wherein the super junction structure includes a drift layer, the substrate and the drift layer are N-type doped, and the material of the substrate and the drift layer includes gallium or aluminum; A gate structure, wherein the gate structure is located on a side surface of the super junction structure away from the substrate, and projections of the gate structure and the drift layer on the substrate overlap; the gate structure comprises a barrier layer, a gate cap layer, a first gate and a second gate, the barrier layer and the drift layer are in contact to form a two-dimensional electron gas conductive channel, the gate cap layer is located on a side surface of the barrier layer away from the substrate, the gate cap layer is P-type doped, the second gate is located on a side surface of the gate cap layer away from the substrate, the material of the barrier layer comprises aluminum, and the material of the gate cap layer is the same as the material of the drift layer; A channel structure, wherein the channel structure is located on both sides of the gate structure along a direction parallel to the surface of the substrate; a first electrode and a second electrode, wherein the first electrode is disposed on a surface of the substrate away from the super junction structure, and the second electrode covers the channel structure; The materials of the substrate and the drift layer are gallium oxide, gallium nitride, gallium arsenide or aluminum nitride, and the material of the barrier layer is aluminum gallium oxide, aluminum gallium nitrogen or aluminum gallium arsenic; When the material of the substrate and the drift layer is gallium oxide, gallium nitride or gallium arsenide, the material of the barrier layer is also aluminum nitride; It also includes an insulating layer, which is arranged between the gate structure and the channel structure. The first gate penetrates a portion of the thickness of the insulating layer. The first gate is isolated from the channel structure by the insulating layer, and the first gate is isolated from the barrier layer by the insulating layer.

2. The dual-gate controlled low on-resistance heterojunction field effect transistor according to claim 1, characterized in that: The insulating layer is also disposed on the gate cap layer and the side walls of the second gate.

3. The dual-gate controlled low on-resistance heterojunction field effect transistor according to claim 1, characterized in that: The channel structure includes at least one channel stack, which includes a first layer and a second layer. The second layer is located on a side of the first layer away from the substrate. The material of the first layer is the same as that of the drift layer, and the material of the second layer is the same as that of the barrier layer.

4. The dual-gate controlled low on-resistance heterojunction field effect transistor according to claim 3, characterized in that: The second electrode at least covers a sidewall of the channel stack away from the gate structure.

5. The dual-gate controlled low on-resistance heterojunction field effect transistor according to claim 3, characterized in that: The channel structure includes a first channel stack and a second channel stack, wherein the second channel stack is located on a side of the first channel stack away from the substrate.

6. The dual-gate controlled low on-resistance heterojunction field effect transistor according to any one of claims 1 to 4, characterized in that: Projections of the channel structure and the drift layer on the substrate partially overlap.

7. The dual-gate controlled low on-resistance heterojunction field effect transistor according to any one of claims 1 to 4, characterized in that: The super junction structure further includes an epitaxial layer, and along a direction parallel to the surface of the substrate, the epitaxial layer is located on both sides of the drift layer, and the projections of the epitaxial layer and the channel structure on the substrate overlap; The epitaxial layer includes a first epitaxial layer and a second epitaxial layer. The second epitaxial layer is located on a side of the first epitaxial layer away from the substrate. The first epitaxial layer and the second epitaxial layer are made of the same material as the substrate. The second epitaxial layer is P-type doped.

8. A method for manufacturing a dual-gate controlled low on-resistance heterojunction field effect transistor, characterized in that: include: A super junction structure is formed on one side of the substrate, wherein the super junction structure includes a drift layer, the substrate and the drift layer are N-type doped, and the material of the substrate and the drift layer includes gallium or aluminum; A gate structure and a channel structure are formed on a side of the super junction structure away from the substrate, and projections of the gate structure and the drift layer on the substrate overlap; the gate structure comprises a barrier layer, a gate cap layer, a first gate and a second gate, the barrier layer and the drift layer are in contact to form a two-dimensional electron gas conductive channel, the gate cap layer is located on a surface of the barrier layer away from the substrate, the gate cap layer is P-type doped, the second gate is located on a surface of the gate cap layer away from the substrate, the material of the barrier layer comprises aluminum, and the material of the gate cap layer is the same as that of the drift layer; along a direction parallel to the surface of the substrate, the channel structure is located on both sides of the gate structure; forming a first electrode and a second electrode, wherein the first electrode is disposed on a surface of the substrate away from the super junction structure, and the second electrode covers the channel structure; The materials of the substrate and the drift layer are gallium oxide, gallium nitride, gallium arsenide or aluminum nitride, and the material of the barrier layer is aluminum gallium oxide, aluminum gallium nitrogen or aluminum gallium arsenic; When the material of the substrate and the drift layer is gallium oxide, gallium nitride or gallium arsenide, the material of the barrier layer is also aluminum nitride; It also includes an insulating layer, which is arranged between the gate structure and the channel structure. The first gate penetrates a portion of the thickness of the insulating layer. The first gate is isolated from the channel structure by the insulating layer, and the first gate is isolated from the barrier layer by the insulating layer.

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