Intersatellite laser precise ranging method, device, computer equipment and storage medium

Abstract

The present invention relates to the field of intersatellite laser ranging technology and discloses a method, apparatus, computer equipment, and storage medium for precise intersatellite laser ranging. The method comprises: utilizing an internal clock IP resource of an FPGA to perform multiple phase shifts on a local clock signal; obtaining the local clock signal after each phase shift; sampling the received clock signal based on the local clock signal after each phase shift; determining the phase difference between the local clock signal and the sampled clock signal based on clock signal statistics sampled from the local clock signal after each phase shift; determining the phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled from the local clock signal after the first phase shift; and determining a precise intersatellite laser ranging value based on the phase difference, the phase relationship, and the frequency of a voltage-controlled oscillator within the clock IP resource. The present invention utilizes the internal clock IP resource of the FPGA to implement phase measurement for precise ranging, saving hardware costs.

Description

Technical Field

[0001] The present invention relates to the technical field of intersatellite laser ranging, and in particular to an intersatellite laser precision ranging method, device, computer equipment and storage medium. Background Art

[0002] Existing intersatellite laser ranging methods, operating under an OOK (On-Off Keying) communication system, rely heavily on precise ranging accuracy. Currently, two solutions exist for precise ranging. The first employs the Gardner symbol phase synchronization method. This method samples the photodetector's received signal using an ADC (Analog-to-Digital Converter), performs symbol synchronization on the sampled signal, calculates the error by sampling the strobe (optimal observation point) and midstrobe (the sampling point between two observation points), and then feeds this error into a digitally controlled oscillator through a loop filter for phase tracking and measurement. This phase information can be used to calculate the precise ranging value.

[0003] The second solution uses CDR clock recovery technology to recover the received clock signal through CDR technology and output it through the FPGA's IO. At the same time, the local clock signal is also output through the FPGA's IO. The two signals are input into a high-precision phase detector, and the output voltage signal of the phase detector is sampled through the ADC to obtain the phase difference between the two signals, thereby completing the phase measurement. The precise ranging value can be calculated based on the phase information.

[0004] However, the first solution requires a high-speed ADC to sample the input signal. Developing a space-grade high-speed ADC is difficult and expensive. It also requires algorithms such as interpolation filters, digitally controlled oscillators, and loop filters, which consume significant computational resources within the FPGA (Field-Programmable Gate Array). The second solution requires an additional high-precision phase detector and ADC for phase measurement, which complicates the system, increases hardware costs, and reduces system reliability. Furthermore, determining the lead or lag relationship between the two signals is difficult, resulting in ambiguity. Summary of the Invention

[0005] In view of this, the present invention provides a method, apparatus, computer equipment and storage medium for intersatellite laser precise ranging to solve the problems of high cost and low system reliability of existing methods for obtaining precise ranging values.

[0006] In a first aspect, the present invention provides a method for intersatellite laser precise ranging, the method comprising:

[0007] Utilize the FPGA's internal clock IP resources to perform multiple rounds of phase shifting on the local clock signal. Each round of phase shifting includes a forward phase shift and a reverse phase shift. The frequency of the voltage-controlled oscillator within the clock IP resources determines the number of forward and reverse phase shifts in each round of phase shifting. The phase shift amount of the forward and reverse phase shifts in each round of phase shifting is the same.

[0008] Obtaining the local clock signal after each phase shift in each round of phase shift;

[0009] Sampling the received clock signal based on the local clock signal after each phase shift in each round of phase shifting;

[0010] Determining a phase difference between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after each phase shift in each round of phase shifting;

[0011] Determining a phase relationship between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after the first phase shift;

[0012] An inter-satellite laser precise ranging value is determined based on the phase difference, a phase relationship between the local clock signal and the sampled clock signal, and a frequency of a voltage-controlled oscillator within the clock IP resource.

[0013] In this embodiment, the phase measurement part of the precise ranging is implemented using the internal clock IP resources of the FPGA, without the need for additional high-speed ADC or high-precision phase detector components, thus saving hardware costs.

[0014] In an optional implementation, the determining the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift based on the frequency of the voltage-controlled oscillator inside the clock IP resource includes:

[0015] Inputting the frequency of the voltage-controlled oscillator and the frequency of the local clock signal into a preset round calculation model to obtain the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift, wherein the number of rounds of forward phase shift and the number of rounds of reverse phase shift are the same;

[0016] The preset round calculation model includes:

[0017]

[0018] Where N is the number of rounds of forward phase shift or reverse phase shift, f clk is the frequency of the local clock signal, f vco is the frequency of the voltage controlled oscillator.

[0019] This embodiment only occupies one clock IP resource of the FPGA and a small amount of logic resources to complete high-precision phase measurement, saving hardware costs.

[0020] In an optional implementation, performing multiple rounds of phase shifting on the local clock signal using the FPGA internal clock IP resource includes:

[0021] Use the FPGA internal clock IP resources to perform positive phase shift on the local clock signal;

[0022] When the phase shift amount of the forward phase shift reaches a preset phase shift amount, using the FPGA internal clock IP resource to perform a reverse phase shift on the local clock signal;

[0023] When the phase shift amount of the reverse phase shift reaches a preset phase shift amount, determining whether the current phase shift round number reaches a phase shift round number threshold;

[0024] If the current phase shift round number does not reach the phase shift round number threshold, the process returns to executing the step of performing a positive phase shift on the local clock signal by using the FPGA internal clock IP resource.

[0025] In this embodiment, the phase measurement part of the precise ranging is implemented using the internal clock IP resources of the FPGA, without the need for additional high-speed ADC or high-precision phase detector components, thus saving hardware costs.

[0026] In an optional implementation, determining the phase difference between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after each phase shift in each round of phase shift includes:

[0027] When the number of phase shift rounds currently completed is equal to the window size of the smoothing filter, the clock signals sampled by the local clock signal after each phase shift in each phase shift round are added together to obtain the cumulative value of the clock signals sampled in each phase shift round, and then the cumulative value of the clock signals sampled in all rounds is obtained;

[0028] Smoothing and filtering are performed on the accumulated values ​​of the sampled clock signals in all the acquired rounds to obtain a phase difference between the local clock signal and the sampled clock signal.

[0029] This embodiment suppresses phase jitter errors by smoothing filtering, thereby improving the accuracy of precise ranging values.

[0030] In an optional embodiment, when the number of phase shift rounds currently completed is less than the window size of the smoothing filter, the smoothing filter process is skipped and the step of performing a positive phase shift on the local clock signal using the FPGA internal clock IP resource is returned to be executed.

[0031] This embodiment suppresses phase jitter errors by smoothing filtering, thereby improving the accuracy of precise ranging values.

[0032] In an optional implementation, determining the phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after the first phase shift includes:

[0033] When the clock signal sampled by the local clock signal after the first phase shift is a first preset value, determining that the phase of the local clock signal is ahead of the phase of the sampled clock signal;

[0034] When the clock signal sampled by the local clock signal after the first phase shift is a second preset value, it is determined that the phase of the local clock signal lags behind the phase of the sampled clock signal.

[0035] This embodiment determines the phase relationship between the local clock signal and the sampled clock signal by sampling the clock signal of the local clock signal after the first phase shift, and can clearly determine the lead and lag relationship between the two signals.

[0036] In an optional implementation, determining the inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of a voltage-controlled oscillator within the clock IP resource includes:

[0037] Inputting the phase difference and the frequency of the voltage-controlled oscillator within the clock IP resource into an inter-satellite laser precise ranging value calculation model to obtain the inter-satellite laser precise ranging value;

[0038] In a case where the phase relationship between the local clock signal and the sampled clock signal is such that the phase of the local clock signal leads the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0039]

[0040] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light;

[0041] In a case where the phase relationship between the local clock signal and the sampled clock signal is that the phase of the local clock signal lags behind the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0042]

[0043] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light.

[0044] In this embodiment, the phase measurement part of the precise ranging is implemented using the internal clock IP resources of the FPGA, without the need for additional high-speed ADC or high-precision phase detector components, thus saving hardware costs.

[0045] In a second aspect, the present invention provides an intersatellite laser precision ranging device, the device comprising:

[0046] A clock signal phase shift module is used to perform multiple rounds of phase shift on the local clock signal using the FPGA's internal clock IP resources. Each round of phase shift includes a forward phase shift and a reverse phase shift. The number of forward and reverse phase shifts in each round of phase shift is determined based on the frequency of the voltage-controlled oscillator within the clock IP resources. The phase shift amount of the forward and reverse phase shifts in each round of phase shift is the same.

[0047] A phase-shifted local clock signal acquisition module is used to acquire the local clock signal after each phase shift in each round of phase shift;

[0048] a clock signal sampling module, configured to sample the received clock signal based on the local clock signal after each phase shift in each round of phase shift;

[0049] a phase difference determining module, configured to determine a phase difference between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after each phase shift in each round of phase shift;

[0050] a phase relationship determining module, configured to determine a phase relationship between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after the first phase shift;

[0051] The inter-satellite laser precise ranging value determination module is used to determine the inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator inside the clock IP resource.

[0052] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the intersatellite laser precision ranging method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0053] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the inter-satellite laser precision ranging method of the above-mentioned first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 is a schematic flow chart of a method for precise intersatellite laser ranging according to an embodiment of the present invention;

[0056] Figure 2 is a flow chart of another intersatellite laser precise ranging method according to an embodiment of the present invention;

[0057] Figure 3 is a flow chart of a forward and reverse phase shift sampling method based on an MMCM IP core according to an embodiment of the present invention;

[0058] Figure 4 Schematic diagram of a phase-shift sampling statistics calculation state machine based on FPGA according to an embodiment of the present invention;

[0059] Figure 5 2 is a block diagram of a structure of an intersatellite laser precise ranging device according to an embodiment of the present invention;

[0060] Figure 6 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0061] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0062] In related technologies, intersatellite laser ranging methods, under an OOK (On-Off Keying) communication system, rely on precise ranging for ranging accuracy. Currently, there are two solutions for precise ranging. The first employs the Gardner symbol phase synchronization method. This method samples the photodetector's received signal using an ADC (Analog-to-Digital Converter), performs symbol synchronization on the sampled signal, calculates the error by sampling the strobe (optimal observation point) and midstrobe (the sampling point between two observation points), and then feeds this error into a digitally controlled oscillator through a loop filter to perform phase tracking and measurement. This phase information can be used to calculate the precise ranging value.

[0063] The second solution uses CDR clock recovery technology to recover the received clock signal through CDR technology and output it through the FPGA's IO. At the same time, the local clock signal is also output through the FPGA's IO. The two signals are input into a high-precision phase detector, and the output voltage signal of the phase detector is sampled through the ADC to obtain the phase difference between the two signals, thereby completing the phase measurement. The precise ranging value can be calculated based on the phase information.

[0064] However, the first solution requires a high-speed ADC to sample the input signal. Developing a space-grade high-speed ADC is difficult and expensive. It also requires algorithms such as interpolation filters, digitally controlled oscillators, and loop filters, which consume significant computational resources within the FPGA. The second solution requires an additional high-precision phase detector and ADC for phase measurement, which complicates the system, increases hardware costs, and reduces system reliability. Furthermore, determining the lead or lag relationship between the two signals is difficult, resulting in ambiguity.

[0065] An embodiment of the present invention provides an intersatellite laser precision ranging method, which realizes the phase measurement part of precision ranging by utilizing the internal clock IP resources of FPGA, eliminating the need for additional high-speed ADC or high-precision phase detector components, thereby achieving the effect of saving hardware costs.

[0066] According to an embodiment of the present invention, an embodiment of an intersatellite laser precision ranging method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0067] In this embodiment, a method for inter-satellite laser precise ranging is provided, which can be used in the above-mentioned mobile terminals, such as central processing units, servers, etc. Figure 1 FIG. 1 is a flow chart of a method for intersatellite laser precise ranging according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0068] Step S101 : performing multiple rounds of phase shifting on a local clock signal using the FPGA internal clock IP resource.

[0069] Each round of phase shift includes forward phase shift and reverse phase shift. The number of forward phase shift and reverse phase shift in each round of phase shift is determined based on the frequency of the voltage-controlled oscillator inside the clock IP resource. The phase shift amount of the forward phase shift and the phase shift amount of the reverse phase shift in each round of phase shift are the same.

[0070] It should be noted that the phase shift amount of the forward phase shift and the phase shift amount of the reverse phase shift in each round of phase shift are 180 degrees.

[0071] The FPGA internal clock IP resource may be an MMCM (Mixed-Mode Clock Manager) IP core (Intellectual Property, a general term for integrated circuit cores) inside the FPGA.

[0072] Step S102: Acquire the local clock signal after each phase shift in each round of phase shift.

[0073] After each phase shift is performed on the local clock signal, the local clock signal after each phase shift is obtained.

[0074] Step S103: sampling the received clock signal based on the local clock signal after each phase shift in each round of phase shift.

[0075] After each phase shift of the local clock signal, the phase-shifted local clock signal is used to sample the clock signal received by the CDR technology. The received clock signal is the clock signal sent by other satellites.

[0076] Step S104 : determining a phase difference between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after each phase shift in each round of phase shift.

[0077] After obtaining the received clock signal sampled by the local clock signal after each phase shift, the phase difference between the local clock signal and the sampled clock signal is determined according to the clock signal sampled corresponding to the local clock signal after each phase shift.

[0078] Step S105 : determining a phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after the first phase shift.

[0079] According to the clock signal sampled from the local clock signal after the first phase shift, the phase relationship between the local clock signal and the sampled clock signal is judged to obtain whether the phase relationship between the local clock signal and the sampled clock signal is leading or lagging.

[0080] Step S106 , determining an inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator inside the clock IP resource.

[0081] After determining the phase difference and phase relationship between the local clock signal and the sampled clock signal, the laser precise ranging value between the two satellites is determined in combination with the frequency of the voltage-controlled oscillator inside the clock IP resource.

[0082] The intersatellite laser precise ranging method provided in this embodiment performs multiple rounds of phase shifting on a local clock signal using an internal clock IP resource of an FPGA. Each round of phase shifting includes a forward phase shift and a reverse phase shift. The number of forward and reverse phase shifts in each round of phase shifting is determined based on the frequency of a voltage-controlled oscillator within the clock IP resource, and the phase shift amount of the forward and reverse phase shifts in each round of phase shifting is the same. The method obtains a local clock signal after each phase shift in each round of phase shifting. The method samples the received clock signal based on the local clock signal after each phase shift in each round of phase shifting. The method determines the phase difference between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after each phase shift in each round of phase shifting. The method determines the phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after the first phase shift. The method determines the intersatellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator within the clock IP resource. In this embodiment, the phase measurement part of the precise ranging is implemented using the internal clock IP resources of the FPGA, without the need for additional high-speed ADC or high-precision phase detector components, thus saving hardware costs.

[0083] This embodiment uses the phase shift function of the MMCM IP core to perform phase measurement on the same frequency signal, and the phase measurement accuracy reaches the order of hundreds of picoseconds (ps).

[0084] In this embodiment, a method for inter-satellite laser precise ranging is provided, which can be used in the above-mentioned mobile terminals, such as central processing units, servers, etc. Figure 2 FIG. 1 is a flow chart of a method for intersatellite laser precise ranging according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0085] In step S201, the local clock signal is subjected to multiple rounds of phase shifting using the internal clock IP resource of the FPGA. Each round of phase shifting includes a forward phase shift and a reverse phase shift. The number of forward phase shifts and the number of reverse phase shifts in each round of phase shifting are determined based on the frequency of the voltage-controlled oscillator within the clock IP resource. The phase shift amount of the forward phase shift and the phase shift amount of the reverse phase shift in each round of phase shifting are the same.

[0086] Specifically, the above step S201 includes:

[0087] S2011, using the FPGA internal clock IP resource to perform a positive phase shift on the local clock signal.

[0088] Figure 3 FIG1 is a flow chart showing a forward and reverse phase shift sampling method based on an MMCM IP core according to an embodiment of the present invention. Figure 3 As shown, this embodiment uses the psen input interface, clk_in clock input interface, psincdec input interface, psdone output interface, clk_out output interface, psen generation timing, psdone reception judgment, psincdec generation timing, forward sampling register and reverse sampling register in the MMCM IP core to complete forward and reverse phase shift sampling.

[0089] Specifically, the psen input interface can achieve a fixed-time phase shift each time it receives a pulse.

[0090] The clk_in clock input interface is connected to the local clock signal.

[0091] The psincdec input interface is configured as 0 or 1 to perform reverse or forward phase shift on the signal of the clock input interface respectively.

[0092] The psdone output interface outputs a pulse flag after each phase shift is completed.

[0093] The clk_out output interface outputs the phase-shifted local clock signal, which is required to sample the CDR-recovered receive clock signal.

[0094] The psen generation timing is written in Verilog language to generate a pulse signal with a fixed time interval and a maintenance time equal to the local clock period.

[0095] The psdone reception judgment is written in Verilog language. After each psdone pulse signal is received, the local clock phase shifted signal is used to sample the CDR recovery reception clock signal, and the sampled value is saved to the register. The CDR recovery reception clock signal is sampled through the sampling circuit.

[0096] The PSIncDec generation timing is written in Verilog language. The PSIncDec signal needs to be changed twice in each round. At the beginning of each round, the PSIncDec signal is set to 1, and then a PSENC pulse is generated for forward phase shift sampling until the phase difference between the local clock phase-shifted signal and the local clock signal is 180 degrees. At this time, the PSIncDec is set to 0, and then a PSENC pulse is generated for reverse phase shift sampling until the phase difference between the local clock phase-shifted signal and the local clock signal is 0 degrees, completing this round of sampling.

[0097] The forward sampling register counts when the psincdec signal is set to 1. If the sample value is 1, the psincdec signal is 1, and the psdone pulse arrives, the register value increases by one. If the sample value is 0, the register value remains unchanged until a round of forward sampling is completed and counting stops. The reverse sampling register counts when the psincdec signal is set to 0. If the sample value is 1, the psincdec signal is 0, and the psdone pulse arrives, the register value increases by one. If the sample value is 0, the register value remains unchanged until a round of reverse sampling is completed and counting stops.

[0098] S2012: When the phase shift amount of the forward phase shift reaches a preset phase shift amount, the local clock signal is reversely phase shifted using the FPGA internal clock IP resource.

[0099] As mentioned above, the phase difference between the signal after the local clock is forward phase shifted and the local clock signal is 180 degrees, that is, the phase shift amount of the forward phase shift reaches the preset phase shift amount. At this time, psincdec is set to 0, and then the psen pulse is generated for reverse phase shift sampling until the phase difference between the signal after the local clock is phase shifted and the local clock signal is 0 degrees, completing this round of sampling.

[0100] S2013: When the phase shift amount of the reverse phase shift reaches a preset phase shift amount, determine whether the current phase shift round number reaches a phase shift round number threshold.

[0101] The phase shift amount of the reverse phase shift reaches the preset phase shift amount, that is, the phase difference between the local clock signal after the reverse phase shift and the local clock signal is 0 degrees, and one round of phase shift is completed.

[0102] It is determined whether the number of phase shift rounds currently completed reaches a phase shift round number threshold, wherein the phase shift round number threshold is set by a technician and is not specifically limited here.

[0103] If the number of phase shift rounds currently completed reaches the phase shift round number threshold, the phase difference between the local clock signal and the sampled clock signal is determined based on the local clock signal and the sampled clock signal after each phase shift in each phase shift round, and subsequent steps are performed.

[0104] S2014: If the current phase shift round number does not reach the phase shift round number threshold, return to executing the step of performing a forward phase shift on the local clock signal using the FPGA internal clock IP resource.

[0105] It can be understood that if the current number of phase shift rounds does not reach the phase shift round number threshold, the step of using the FPGA internal clock IP resources to perform forward phase shift on the local clock signal will continue, that is, the next round of local clock signal phase shift will continue until the current number of completed phase shift rounds reaches the phase shift round number threshold.

[0106] Step S202: Acquire the local clock signal after each phase shift in each round of phase shift.

[0107] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0108] Step S203: sampling the received clock signal based on the local clock signal after each phase shift in each round of phase shift.

[0109] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0110] Step S204 : determining a phase difference between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after each phase shift in each round of phase shift.

[0111] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0112] Step S205 : Based on the clock signal sampled by the local clock signal after the first phase shift, determine the phase relationship between the local clock signal and the sampled clock signal.

[0113] For details, please see Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0114] Step S206 , determining an inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator inside the clock IP resource.

[0115] For details, please see Figure 1 Step S106 of the illustrated embodiment will not be described in detail here.

[0116] In this embodiment, the phase measurement part of the fine ranging is implemented using the internal clock IP resources of the FPGA, without the need for additional high-speed ADC or high-precision phase detector components, thus saving hardware costs and obtaining a high-precision fine ranging value.

[0117] In some optional implementations, determining the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift based on the frequency of a voltage-controlled oscillator within the clock IP resource includes:

[0118] Inputting the frequency of the voltage-controlled oscillator and the frequency of the local clock signal into a preset round calculation model to obtain the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift, wherein the number of rounds of forward phase shift and the number of rounds of reverse phase shift are the same;

[0119] Preset round calculation model, including:

[0120]

[0121] Where N is the number of rounds of forward phase shift or reverse phase shift in each round of phase shift, f clk is the frequency of the local clock signal, f vco is the frequency of the voltage controlled oscillator.

[0122] The forward and reverse phase-shift sampling method described above, based on the MMCM IP core, performs forward and reverse phase-shift sampling, storing the sampled values ​​in the forward and reverse sampling registers. The PSENS generation timing is dependent on the frequency of the voltage-controlled oscillator within the clock IP resource and the period of the local clock signal. The number of PSENS pulses generated in each round requires detailed calculation to determine the number of forward and reverse phase shifts in each phase shift.

[0123] Specifically, the number of PSENS pulses in each round is the sum of the number of rounds of forward phase shifting and the number of rounds of reverse phase shifting, where the number of rounds of forward phase shifting is the same as the number of rounds of reverse phase shifting. In other words, half of the number of PSENS pulses generated in each round is used for the forward phase shift of the local clock signal, and half is used for the reverse phase shift of the local clock signal.

[0124] Among them, the MMCM IP core contains an internal VCO (voltage controlled oscillator) with a frequency of f vco .

[0125] The calculation formula for the number of rounds of forward phase shift or reverse phase shift in each round of phase shift is:

[0126]

[0127] Among them, T cycle The time required to complete a 180-degree phase shift, T p is the single phase shift time, T clk is the period of the local clock signal, f clk is the frequency of the local clock signal, f vco is the frequency of the voltage-controlled oscillator, and N is the number of rounds of forward phase shift or reverse phase shift in each round of phase shift.

[0128] In some optional implementations, the above step S204 includes:

[0129] Step a1: When the number of phase shift rounds currently completed is equal to the window size of the smoothing filter, the clock signals sampled by the local clock signal after each phase shift in each phase shift round are added together to obtain the accumulated value of the clock signals sampled in each phase shift round.

[0130] The window size of the smoothing filter is the same as the phase shift round number threshold. The number of phase shift rounds currently completed is equal to the window size of the smoothing filter, that is, the number of phase shift rounds currently completed has reached the phase shift round number threshold, and there is no need to perform the next phase shift round.

[0131] The clock signals sampled by the local clock signals after each phase shift stored in the forward sampling register and the reverse sampling register in each round of phase shift are added together to obtain the cumulative value of the clock signals sampled in each round of phase shift, and then the cumulative value of the clock signals sampled corresponding to all rounds is obtained.

[0132] Step a2: performing smoothing filtering on the accumulated values ​​of the sampled clock signals in all rounds to obtain a phase difference between the local clock signal and the sampled clock signal.

[0133] The accumulated values ​​of the clock signals sampled in each round of phase shift are added together to obtain the accumulated values ​​of the clock signals sampled corresponding to all rounds.

[0134] The smoothing filtering process is to divide the accumulated value of the sampled clock signals corresponding to all rounds by the smoothing filtering window size, and then divide it by 2 to obtain the value after smoothing filtering. The value after smoothing filtering is input into the phase measurement register to obtain the phase difference between the local clock signal and the sampled clock signal.

[0135] For example, the value after smoothing filtering is 50, the number of rounds of positive phase shift is 100, and the phase difference between the local clock signal and the sampled clock signal is 90 degrees.

[0136] Step a3: When the number of phase shift rounds currently completed is less than the window size of the smoothing filter, the smoothing filter process is skipped and the process returns to the step of performing a positive phase shift on the local clock signal using the FPGA internal clock IP resource.

[0137] It can be understood that if the number of phase shift rounds currently completed is less than the window size of the smoothing filter, it means that the number of phase shift rounds currently completed has not reached the phase shift round threshold, then the step of using the FPGA internal clock IP resources to perform a positive phase shift on the local clock signal will continue, that is, the next round of local clock signal phase shift will continue until the number of phase shift rounds currently completed reaches the phase shift round threshold.

[0138] It should be noted that the error in measuring the phase difference using the MMCM IP core comes from the MMCM's absolute phase error and phase jitter error. The absolute phase error can be removed through test calibration, and the phase jitter error can be suppressed through the above-mentioned smoothing filtering method. After smoothing filtering, the MMCM IP core's phase jitter error is less than 100 ps, ​​and the obtained precise ranging value error is less than 3 cm.

[0139] In some optional implementations, the above step S205 includes:

[0140] Step b1: when the clock signal sampled by the local clock signal after the first phase shift is a first preset value, determining whether the phase of the local clock signal is ahead of the phase of the sampled clock signal.

[0141] The clock signal sampled by the local clock signal after the first phase shift is the clock signal sampled by the local clock signal after the first positive phase shift.

[0142] The first preset value is 0. When the clock signal sampled by the local clock signal after the first phase shift is 0, it indicates that the phase of the local clock signal is ahead of the phase of the clock signal recovered and received by the CDR.

[0143] Step b2: When the clock signal sampled by the local clock signal after the first phase shift is a second preset value, determining that the phase of the local clock signal lags behind the phase of the sampled clock signal.

[0144] The second preset value is 1. When the clock signal sampled by the local clock signal after the first phase shift is 1, it indicates that the phase of the local clock signal lags behind the phase of the clock signal recovered and received by the CDR.

[0145] In some optional implementations, the above step S206 includes:

[0146] In step c1, the phase difference and the frequency of the voltage-controlled oscillator in the clock IP resource are input into an inter-satellite laser precise ranging value calculation model to obtain an inter-satellite laser precise ranging value.

[0147] Wherein, when the phase relationship between the local clock signal and the sampled clock signal is that the phase of the local clock signal leads the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0148]

[0149] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vcois the frequency of the voltage-controlled oscillator inside the clock IP resource, c is the speed of light, and the negative sign indicates advance.

[0150] In the case where the phase relationship between the local clock signal and the sampled clock signal is such that the phase of the local clock signal lags behind the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0151]

[0152] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light.

[0153] It should be noted that, in this embodiment, phase-shift sampling is implemented through a phase-shift sampling statistical calculation state machine based on FPGA. Figure 4 FIG. 1 is a schematic diagram of a phase shift sampling statistics calculation state machine based on FPGA according to an embodiment of the present invention. Figure 4 As shown in FIG, the state machine includes four states, namely, S0, S1, S2 and S3. Among them, S0 is the state of waiting for the phase ranging flag, S1 is the state of forward phase shift sampling, S2 is the state of reverse phase shift sampling, and S3 is the state of statistical smoothing filtering.

[0154] Among them, the S0 state is the waiting phase ranging flag state. In this state, after receiving the phase ranging flag recv_flag pulse signal, it jumps to the S1 forward phase shift sampling state. If the recv_flag pulse signal is not received, the current state is maintained.

[0155] like Figure 4 As shown, if the phase ranging flag recv_flag pulse signal is received, it is recv_flag=1, and if the recv_flag pulse signal is not received, it is recv_flag=0.

[0156] The S1 state is the forward phase shift sampling state. In this state, forward phase shift sampling is performed, that is, the psincdec signal is set to 1, and after the first psen pulse signal is generated, the psdone pulse signal is waited for. When the psdone pulse signal comes, the forward sampling register is counted, and then the second psen pulse signal is generated until the number N of psen pulse signals is generated. ps It is equal to the number of times N of positive phase shift in each round, so that the phase of the local clock signal is 180 degrees ahead of the phase of the signal after the local clock phase shift, and then jumps to the S2 state.

[0157] The S1 state includes a phase relationship determination register. When the first psdone signal arrives, the sampled value of 0 or 1 is stored in the phase relationship determination register. If the sampled value is 0, it means that the phase of the local clock signal is ahead of the phase of the CDR recovered receive clock signal. If the sampled value is 1, it means that the phase of the local clock signal is behind the phase of the CDR recovered receive clock signal.

[0158] The S2 state is the reverse phase shift sampling state. In this state, reverse phase shift sampling is performed, that is, the psincdec signal is set to 0, and after the first psen pulse signal is generated, the psdone pulse signal is waited for. When the psdone pulse signal comes, the reverse sampling register is counted, and then the second psen pulse signal is generated until the number N of psen pulse signals is generated. ps It is equal to the number of times N of reverse phase shift in each round, so that the phase of the local clock signal is the same as the phase of the signal after the local clock phase shift, and then jumps to the S3 state.

[0159] The S3 state is a statistical smoothing filter state, which includes register sampling statistics and smoothing filter methods. This state has no jump conditions. After the calculation is completed in this state, it immediately jumps to the S0 state.

[0160] The register sampling statistics method includes a round number statistics register, a sampling accumulation register, and a phase measurement register. The round number statistics register increments by one each time the S3 state is entered. The sampling accumulation register adds the values ​​in the forward and reverse sampling registers after each phase shift to the sampling accumulation register and clears the current values ​​in the forward and reverse sampling registers. The value in the phase measurement register represents the phase difference between the local clock signal and the CDR recovered receive clock signal.

[0161] The smoothing filtering method includes two cases: the first is to perform smoothing filtering, and the second is to skip smoothing filtering. The smoothing filtering method performs smoothing filtering when the value in the round number statistics register is equal to the smoothing filter window size W, that is, when the value in the round number statistics register is equal to the phase shift round number threshold. This smoothing filtering is performed once, dividing the value in the accumulated sampling register by (2*W) and storing the resulting smoothing filtering value in the phase measurement register. Skipping smoothing filtering means that when the value in the round number statistics register is less than the smoothing filter window size, smoothing filtering is skipped.

[0162] The values ​​in the phase measurement register and the phase relationship judgment register are obtained by using the FPGA-based phase shift sampling statistical calculation state machine, which are N phase and N R If the phase relationship judgment register value N RIf it is 0, it means that the local clock signal phase is ahead of the CDR recovery receiving clock signal phase, and the precise ranging L value is

[0163]

[0164] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light.

[0165] If the phase relationship judgment register value N R If it is 1, it means that the local clock signal phase lags behind the CDR recovery receiving clock signal phase, and the precise ranging L value is

[0166]

[0167] The intersatellite laser precision ranging method provided in this embodiment uses FPGA to implement a state machine and completes forward and reverse phase shift sampling, ensuring that the signal after the local clock phase shift at the initial moment of each round is in the same phase as the local clock signal, and no cumulative error will be generated.

[0168] This embodiment also provides an interstellar laser precision ranging device, which is used to implement the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented using software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0169] This embodiment provides an inter-satellite laser precise ranging device, such as Figure 5 Shown, including:

[0170] The clock signal phase shift module 501 is used to perform multiple rounds of phase shift on the local clock signal using the internal clock IP resources of the FPGA. Each round of phase shift includes a forward phase shift and a reverse phase shift. The number of forward phase shifts and the number of reverse phase shifts in each round of phase shift are determined based on the frequency of the voltage-controlled oscillator within the clock IP resources. The phase shift amount of the forward phase shift and the phase shift amount of the reverse phase shift in each round of phase shift are the same.

[0171] The phase-shifted local clock signal acquisition module 502 is configured to acquire the local clock signal after each phase shift in each round of phase shifting.

[0172] The clock signal sampling module 503 is configured to sample the received clock signal based on the local clock signal after each phase shift in each round of phase shift.

[0173] The phase difference determining module 504 is configured to determine a phase difference between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after each phase shift in each round of phase shift.

[0174] The phase relationship determining module 505 is configured to determine the phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after the first phase shift.

[0175] The inter-satellite laser precise ranging value determination module 506 is configured to determine the inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator within the clock IP resource.

[0176] In some optional implementations, the clock signal phase shift module 501 includes:

[0177] a preset round calculation unit, configured to input the frequency of the voltage-controlled oscillator and the frequency of the local clock signal into a preset round calculation model, and obtain the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift, wherein the number of rounds of forward phase shift and the number of rounds of reverse phase shift are the same;

[0178] Preset round calculation model, including:

[0179]

[0180] Where N is the number of rounds of forward phase shift or reverse phase shift, f clk is the frequency of the local clock signal, f VCo is the frequency of the voltage controlled oscillator.

[0181] In some optional implementations, the clock signal phase shift module 501 includes:

[0182] The forward phase shift unit is used to perform a forward phase shift on the local clock signal using the FPGA's internal clock IP resources.

[0183] The reverse phase shift unit is used to reverse phase shift the local clock signal using the FPGA internal clock IP resources when the phase shift amount of the forward phase shift reaches a preset phase shift amount.

[0184] The judging unit is configured to judge whether the current phase shift round number reaches a phase shift round number threshold when the phase shift amount of the reverse phase shift reaches a preset phase shift amount.

[0185] The first return execution unit is used to return to the step of performing a forward phase shift on the local clock signal by using the FPGA internal clock IP resource when the current phase shift round number does not reach the phase shift round number threshold.

[0186] In some optional implementations, the phase difference determination module 504 includes:

[0187] The accumulated value acquisition unit is used to add the clock signals sampled by the local clock signal after each phase shift in each round of phase shift when the number of phase shift rounds currently completed is equal to the window size of the smoothing filter, to obtain the accumulated value of the clock signals sampled in each round of phase shift, and then to obtain the accumulated value of the clock signals sampled in all rounds.

[0188] The phase difference determination subunit is used to perform smoothing filtering on the accumulated values ​​of the sampled clock signals in all rounds to obtain the phase difference between the local clock signal and the sampled clock signal.

[0189] In some optional embodiments, the device comprises:

[0190] The second return execution unit is used to skip the smoothing filtering process when the number of phase shift rounds currently completed is less than the window size of the smoothing filter, and return to the step of using the FPGA internal clock IP resource to perform a positive phase shift on the local clock signal.

[0191] In some optional implementations, the phase relationship determination module 505 includes:

[0192] The phase advance determining unit is configured to determine that the phase of the local clock signal is ahead of the phase of the sampled clock signal when the clock signal sampled by the local clock signal after the first phase shift is a first preset value.

[0193] The phase lag determining unit is configured to determine that the phase of the local clock signal lags behind the phase of the sampled clock signal when the clock signal sampled by the local clock signal after the first phase shift is a second preset value.

[0194] In some optional implementations, the inter-satellite laser precise ranging value determination module 506 includes:

[0195] The intersatellite laser precise ranging value determination subunit is used to input the phase difference and the frequency of the voltage-controlled oscillator inside the clock IP resource into the intersatellite laser precise ranging value calculation model to obtain the intersatellite laser precise ranging value, wherein,

[0196] In the case where the phase relationship between the local clock signal and the sampled clock signal is such that the phase of the local clock signal leads the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0197]

[0198] Among them, L is the intersatellite laser precise ranging value, N phasE is the phase difference between the local clock signal and the sampled clock signal, fVco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light;

[0199] In the case where the phase relationship between the local clock signal and the sampled clock signal is such that the phase of the local clock signal lags behind the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes:

[0200]

[0201] Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light.

[0202] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0203] The intersatellite laser precision ranging device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0204] The embodiment of the present invention also provides a computer device having the above Figure 5 The interstellar laser precision ranging device shown.

[0205] See also Figure 6 , Figure 6 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 601, memory 602, and the interface for connecting each component, including a high-speed interface and a low-speed interface. Each component utilizes different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instruction executed in the computer device, including being stored in the memory or on the memory to display the graphic information of the GUI on an external input / output device (such as, being coupled to the display device of the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides the necessary operation of part (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 601 is taken as an example.

[0206] Processor 601 may be a central processing unit, a network processor, or a combination thereof. Processor 601 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0207] The memory 602 stores instructions that can be executed by at least one processor 601, so as to enable the at least one processor 601 to execute the method shown in the above embodiment.

[0208] The memory 602 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 602 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 602 may optionally include a memory remotely located relative to the processor 601, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0209] The memory 602 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 602 may also include a combination of the above types of memory.

[0210] The computer device further includes a communication interface 603 for the computer device to communicate with other devices or a communication network.

[0211] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0212] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for intersatellite laser precise ranging, characterized in that: The method comprises: Utilize the FPGA's internal clock IP resources to perform multiple rounds of phase shifting on the local clock signal. Each round of phase shifting includes a forward phase shift and a reverse phase shift. The frequency of the voltage-controlled oscillator within the clock IP resources determines the number of forward and reverse phase shifts in each round of phase shifting. The phase shift amount of the forward and reverse phase shifts in each round of phase shifting is the same. Obtaining the local clock signal after each phase shift in each round of phase shift; Sampling the received clock signal based on the local clock signal after each phase shift in each round of phase shifting; Determining a phase difference between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after each phase shift in each round of phase shifting; determining, based on a clock signal sampled by the local clock signal after the first phase shift, a phase relationship between the local clock signal and the sampled clock signal; An inter-satellite laser precise ranging value is determined based on the phase difference, a phase relationship between the local clock signal and the sampled clock signal, and a frequency of a voltage-controlled oscillator within the clock IP resource.

2. The method according to claim 1, characterized in that The determining of the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift based on the frequency of the voltage-controlled oscillator inside the clock IP resource includes: Inputting the frequency of the voltage-controlled oscillator and the frequency of the local clock signal into a preset round calculation model to obtain the number of rounds of forward phase shift and the number of rounds of reverse phase shift in each round of phase shift, wherein the number of rounds of forward phase shift and the number of rounds of reverse phase shift are the same; The preset round calculation model includes: Where N is the number of rounds of forward phase shift or reverse phase shift, f clk is the frequency of the local clock signal, f vco is the frequency of the voltage controlled oscillator.

3. The method according to claim 1, characterized in that The method of performing multiple rounds of phase shifting on the local clock signal by using the FPGA internal clock IP resource includes: Use the FPGA internal clock IP resources to perform positive phase shift on the local clock signal; When the phase shift amount of the forward phase shift reaches a preset phase shift amount, using the FPGA internal clock IP resource to perform a reverse phase shift on the local clock signal; When the phase shift amount of the reverse phase shift reaches a preset phase shift amount, determining whether the current phase shift round number reaches a phase shift round number threshold; If the current phase shift round number does not reach the phase shift round number threshold, the process returns to executing the step of performing a positive phase shift on the local clock signal by using the FPGA internal clock IP resource.

4. The method according to claim 3, characterized in that The determining, based on a clock signal sampled from a local clock signal after each phase shift in each round of phase shifting, a phase difference between the local clock signal and the sampled clock signal, comprises: When the number of phase shift rounds currently completed is equal to the window size of the smoothing filter, the clock signals sampled by the local clock signal after each phase shift in each phase shift round are added together to obtain the cumulative value of the clock signals sampled in each phase shift round, and then the cumulative value of the clock signals sampled in all rounds is obtained; Smoothing and filtering are performed on the accumulated values ​​of the sampled clock signals in all the acquired rounds to obtain a phase difference between the local clock signal and the sampled clock signal.

5. The method according to claim 4, characterized in that When the number of phase shift rounds currently completed is less than the window size of the smoothing filter, the smoothing filter process is skipped and the process returns to the step of performing a positive phase shift on the local clock signal using the FPGA internal clock IP resource.

6. The method according to claim 1, characterized in that The step of determining a phase relationship between the local clock signal and the sampled clock signal based on the clock signal sampled by the local clock signal after the first phase shift comprises: When the clock signal sampled by the local clock signal after the first phase shift is a first preset value, determining that the phase of the local clock signal is ahead of the phase of the sampled clock signal; When the clock signal sampled by the local clock signal after the first phase shift is a second preset value, it is determined that the phase of the local clock signal lags behind the phase of the sampled clock signal.

7. The method according to claim 1, characterized in that The determining the intersatellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator inside the clock IP resource includes: Inputting the phase difference and the frequency of the voltage-controlled oscillator within the clock IP resource into an inter-satellite laser precise ranging value calculation model to obtain the inter-satellite laser precise ranging value; In a case where the phase relationship between the local clock signal and the sampled clock signal is such that the phase of the local clock signal leads the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes: Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light; In a case where the phase relationship between the local clock signal and the sampled clock signal is that the phase of the local clock signal lags behind the phase of the sampled clock signal, the inter-satellite laser precise ranging value calculation model includes: Among them, L is the intersatellite laser precise ranging value, N phase is the phase difference between the local clock signal and the sampled clock signal, f vco is the frequency of the voltage-controlled oscillator inside the clock IP resource, and c is the speed of light.

8. An intersatellite laser precise ranging device, characterized in that: The device comprises: A clock signal phase shift module is used to perform multiple rounds of phase shift on the local clock signal using the FPGA's internal clock IP resources. Each round of phase shift includes a forward phase shift and a reverse phase shift. The number of forward and reverse phase shifts in each round of phase shift is determined based on the frequency of the voltage-controlled oscillator within the clock IP resources. The phase shift amount of the forward and reverse phase shifts in each round of phase shift is the same. A phase-shifted local clock signal acquisition module is used to acquire the local clock signal after each phase shift in each round of phase shift; a clock signal sampling module, configured to sample the received clock signal based on the local clock signal after each phase shift in each round of phase shift; a phase difference determining module, configured to determine a phase difference between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after each phase shift in each round of phase shift; a phase relationship determining module, configured to determine a phase relationship between the local clock signal and the sampled clock signal based on a clock signal sampled by the local clock signal after the first phase shift; The inter-satellite laser precise ranging value determination module is used to determine the inter-satellite laser precise ranging value based on the phase difference, the phase relationship between the local clock signal and the sampled clock signal, and the frequency of the voltage-controlled oscillator inside the clock IP resource.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the intersatellite laser precise ranging method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the inter-satellite laser precise ranging method according to any one of claims 1 to 7.

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