Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes a display area and a routing area. A plurality of signal lines are disposed within the routing area. The signal lines include a first signal line and a second signal line having symmetrical signal waveforms. The first signal line and the second signal line are intersectingly disposed. The first signal line includes a first straight section and a first intersecting section, and the second signal line includes a second straight section and a second intersecting section. Because the clock signals in the two signal lines are symmetrical and the two signal lines are intersecting, the coupling and pulling effects generated between the two different signal lines and a common voltage feedback compensation routing line cancel each other out, thereby reducing the pulling differences between the clock signal lines and the common voltage feedback compensation routing line at different locations, thereby improving the display quality of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display and manufacturing technology, and more specifically, to a display panel and a display device. Background Art

[0002] With the development of display technology, consumers have higher and higher requirements for display products. Various display devices have been widely used as mainstream display components in electronic display products such as laptops, smartphones, and TVs. At the same time, people's performance requirements for various devices are also getting higher and higher.

[0003] With the continuous development of the thin-film transistor liquid crystal display (TFT-LCD) industry, low-cost, narrow-border, and lightweight products have attracted more attention. Against this backdrop, Gate Driver on Array (GOA) technology has emerged. GOA technology integrates the gate drive circuit and thin-film transistor array on the array substrate. Through the cascade relationship of shift register units, the pixels are turned on row by row, thereby enabling the display to display a colorful image. The above-mentioned gate drive circuit typically includes multiple signal lines, such as common voltage feedback compensation lines and clock signal lines, which transmit different control signals through different signal lines.

[0004] However, in the gate driving circuit in the prior art, there is a large interference between different signal lines, and the mutual pulling effect is not ideal, thereby reducing the display effect of the display panel. Summary of the Invention

[0005] In view of the shortcomings of the existing methods, the present application proposes a display panel and a display device to solve the problem of large differences in the pulling effects between different clock signal lines in the gate drive circuit in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area and a wiring area located on at least one side of the display area, wherein a gate drive circuit and a common voltage feedback compensation wiring are provided in the wiring area, and the common voltage feedback compensation wiring extends along a first direction;

[0007] a plurality of signal lines for providing signals to the gate drive circuit, the plurality of signal lines being arranged on a side of the common voltage feedback compensation line close to the display area, and the plurality of signal lines being insulated from each other;

[0008] Among them, the multiple signal lines include a first signal line and a second signal line, the first signal line and the second signal line are arranged to cross each other, the first signal line includes a first straight section and a first crossing section, the second signal line includes a second straight section and a second crossing section, and the first straight section and the second straight section both extend along the first direction.

[0009] According to an embodiment of the present application, the first signal line includes a first clock signal line for transmitting a first clock signal, and the second signal line includes a second clock signal line for transmitting a second clock signal;

[0010] The signal waveform of the first clock signal is symmetrical to the signal waveform of the second clock signal.

[0011] According to an embodiment of the present application, the valid pulse width of the first clock signal is equal to the invalid pulse width of the second clock signal, and the invalid pulse width of the first clock signal is equal to the valid pulse width of the second clock signal.

[0012] According to an embodiment of the present application, the first straight section includes a first subsection and a second subsection, and the first subsection and the second subsection are connected by the first crossing section;

[0013] The second straight section includes a third subsection and a fourth subsection, and the third subsection and the fourth subsection are connected by the second crossing section;

[0014] Wherein, the first sub-portion is arranged close to the common voltage feedback compensation wiring, and the second sub-portion is arranged away from the common voltage feedback compensation wiring;

[0015] The third sub-portion is disposed close to the common voltage feedback compensation line, and the fourth sub-portion is disposed away from the common voltage feedback compensation line.

[0016] According to an embodiment of the present application, the first sub-portion and the second sub-portion are centrally symmetrically arranged relative to the intersection of the first intersection section and the second intersection section;

[0017] The third sub-section and the fourth sub-section are centrally symmetrically arranged relative to an intersection point of the first intersection section and the second intersection section.

[0018] According to an embodiment of the present application, the first sub-portion and the second sub-portion are centrally symmetrically arranged relative to the intersection of the first intersection section and the second intersection section;

[0019] The third sub-section and the fourth sub-section are centrally symmetrically arranged relative to an intersection point of the first intersection section and the second intersection section.

[0020] According to one embodiment of the present invention, the first sub-section, the first intersection section and the second sub-section are continuously arranged, and the third sub-section and the fourth sub-section are disconnected and bridged by the second intersection section;

[0021] Alternatively, the third subsection, the second intersection segment and the fourth subsection are continuously arranged, and the first subsection and the second subsection are disconnected and bridged by the first intersection segment.

[0022] According to an embodiment of the present invention, when the third sub-portion and the fourth sub-portion are disconnected and bridged by the second crossing segment, the second crossing segment is provided on the same layer as the second metal layer or the electrode layer of the display panel;

[0023] When the first sub-portion and the second sub-portion are disconnected and bridged by the first crossing segment, the first crossing segment is provided on the same layer as the second metal layer or the electrode layer of the display panel.

[0024] According to an embodiment of the present application, an orthographic projection of the signal line on the common voltage feedback compensation line coincides with the common voltage feedback compensation line.

[0025] According to an embodiment of the present application, the plurality of signal lines include a first crossing group and a second crossing group;

[0026] The first cross group and the second cross group both include at least an even number of traces, and the clock signals corresponding to the clock signal lines in the first cross group and the second cross group are symmetrical in pairs.

[0027] The first sub-section and the third sub-section are arranged alternately, and the second sub-section and the fourth sub-section are arranged alternately; or,

[0028] Each of the first sub-units is arranged in sequence close to the common voltage feedback compensation routing, each of the third sub-units is arranged in sequence away from the common voltage feedback compensation routing, and each of the second sub-units is arranged in sequence away from the common voltage feedback compensation routing, and each of the fourth sub-units is arranged in sequence close to the common voltage feedback compensation routing.

[0029] According to an embodiment of the present application, the first cross group is arranged close to the common voltage feedback compensation line, and the second cross group is arranged away from the common voltage feedback compensation line;

[0030] The number of the signal lines in the first crossing group is greater than the number of the signal lines in the second crossing group.

[0031] According to an embodiment of the present application, the length of the corresponding crossing segment in the first crossing group is greater than the length of the corresponding crossing segment in the second crossing group.

[0032] According to an embodiment of the present application, the intersection of the first signal line and the second signal line is located on a perpendicular bisector of the common voltage feedback compensation line.

[0033] In a second aspect, an embodiment of the present application provides a display device, which includes the display panel provided in the present application.

[0034] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0035] An embodiment of the present application provides a display panel and a display device. The display panel includes a display area and a routing area arranged on at least one side of the display area. A common voltage feedback compensation routing and a plurality of signal lines are arranged in the routing area. Different signal lines transmit different clock signals, and the clock signal includes at least one group of symmetrically arranged clock signals, and the signal lines corresponding to the symmetrical clock signals are cross-arranged. Since the clock signals in the two signal lines are symmetrical clock signals and the two signal lines are cross-arranged, the coupling pulling effects generated between the two different signal lines and the common voltage feedback compensation routing will cancel each other out, thereby reducing the pulling difference between the clock signal lines and the common voltage feedback compensation routing at different positions, thereby reducing the mutual influence problem between different signal routings and effectively improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0037] Figure 1 A schematic diagram of the planar structure of a display panel provided in the prior art;

[0038] Figure 2 A schematic diagram of the wiring structure of the gate drive circuit in the existing setup;

[0039] Figure 3 for Figure 2 The timing diagram corresponding to each signal line in;

[0040] Figure 4 A schematic diagram of the arrangement of signal lines in the gate drive circuit provided in an embodiment of the present application;

[0041] Figure 5 for Figure 4 The timing diagram corresponding to each signal line provided in;

[0042] Figure 6 This is a schematic diagram of another arrangement structure of clock signal lines provided in an embodiment of the present application;

[0043] Figure 7-11 Schematic diagram of the film layer structure corresponding to the preparation process of the clock signal line provided in the embodiment of the present application;

[0044] Figure 12A schematic diagram of another clock signal line arrangement structure provided in an embodiment of the present application;

[0045] Figure 13 for Figure 12 Timing diagram of the clock signal line in ;

[0046] Figure 14 A schematic diagram of another clock signal line arrangement structure provided in an embodiment of the present application;

[0047] Figure 15 Provided in the embodiments of this application Figure 14 The timing diagram corresponding to each clock signal line in .

[0048] Description of reference numerals:

[0049] 1031-first sub-section, 1032-second sub-section, 1033-first crossing section, 101-third sub-section, 1012-fourth sub-section, 104-second crossing section, 3031-first signal line, 3032-second signal line, 102-gate insulation layer, 103-passivation layer, 104-electrode layer, 30-signal routing, gate drive circuit 301, common voltage feedback compensation routing 302, clock signal line 303, CLK-clock signal line, 304-routing area, 305-display area, 1012-second straight section, 1013-crossing section, 881-first crossing group, 882-second crossing group, 3031-first signal line. DETAILED DESCRIPTION

[0050] The present application is described in detail below. Examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0051] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0052] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "above", and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0053] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0054] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0055] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0056] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0057] The present application provides a display panel and a display device, which are intended to solve the above technical problems in the prior art. The following describes in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments.

[0058] The first aspect, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the planar structure of a display panel provided in the prior art. The display panel includes a display area 305 and a wiring area 304. The wiring area 304 can be located at a corresponding position on at least one side of the display area 305. In the embodiment of the present application, the wiring area 304 is arranged around the display area 305. To avoid affecting the normal display of the display panel, the wiring area 304 can be set as a non-display area at the edge of the display panel, and the panel's luminous display is achieved through the display area 305.

[0059] The wiring area 304 also includes a gate driver circuit 301, a common voltage feedback compensation wiring 302 (Vcom Feedback, Vcom-FB), and multiple signal lines 30. The multiple signal lines 30 are electrically connected to the gate driver circuit 301 and provide signals to the gate driver circuit 301 via the multiple signal lines 30.

[0060] Specifically, since a variety of different signals can be transmitted in the gate drive circuit 301, its signal line 30 also includes a plurality of signal lines with different functions. In the embodiment of the present application, the signal line 30 takes the clock signal line 303 (CLK) as an example. At the same time, multiple clock signal lines 303 are arranged on the side close to the display area 305, and the common voltage feedback compensation line 302 is arranged on the side of the clock signal line 303 away from the wiring area 304. The clock signal line 303 and the common voltage feedback compensation line 302 are both arranged along the first direction, such as the common voltage feedback compensation line 302 is arranged near the edge of the display panel. In the embodiment of the present application, the common voltage feedback compensation line 302 is mainly used to collect the coupling signal in the display panel and transmit the above-mentioned coupling signal to the printed circuit board outside the display panel. After that, the common voltage in the display panel is stabilized through circuit reverse compensation, and the normal operation of the display panel is ensured.

[0061] like Figure 2 as well as Figure 3 middle, Figure 2 Schematic diagram of the gate drive circuit wiring structure in the existing setup. Figure 3 for Figure 2 The timing diagrams for each signal line in the CMOS are shown in Figure 3. Existing designs typically employ a common voltage feedback compensation line 302 placed in parallel with the clock signal line to provide stability. However, due to the different relative positions of the common voltage feedback compensation line 302 and the clock signal line 303, their effects on coupling pull vary. The timing diagram clearly shows that different clock signal lines correspond to different timings, and the timing signal on the Vcom-FB line is unstable, thus affecting the signal transmission of the display panel and causing horizontal stripes on the display.

[0062] In the embodiment of the present application, a new wiring structure of the common voltage feedback compensation line 302 and the clock signal line 303 is provided to effectively improve the display effect of the panel.

[0063] Specifically, such as Figure 4 As shown, Figure 4 Schematic diagram of the arrangement of signal lines in the gate drive circuit provided in the embodiment of the present application. Figure 1 In the structure of the embodiment of the present application, the common voltage feedback compensation line 302 is arranged on one side of the plurality of signal lines 30. In the embodiment of the present application, the signal line 30 is described by taking the clock signal line as an example. Specifically, the signal line 30 is described by taking the first clock signal line (CLK1), the second clock signal line (CLK2), the third clock signal line (CLK3), the fourth clock signal line (CLK4), the fifth clock signal line (CLK5) and the sixth clock signal line (CLK6) as an example, and the above six clock signal lines are all arranged on the same side of the common voltage feedback compensation line 302, and the different clock signal lines are insulated from each other to ensure normal transmission of the signal.

[0064] In an embodiment of the present application, the cross-set clock signal lines can transmit different clock signals, such as one clock signal line transmits a first clock signal, and another clock signal line transmits a second clock signal, and the first clock signal and the second clock signal are symmetrical clock signals.

[0065] Specifically, the first clock signal line CLK1 transmits a first clock signal, and the fourth clock signal line CLK4 transmits a second clock signal. The first clock signal line CLK1 and the fourth clock signal line CLK4 are intersectingly arranged, and the clock signals on the two intersecting clock signal lines have symmetrical waveforms. Thus, since the first clock signal line CLK1 and the fourth clock signal line CLK4 are intersectingly arranged, the signal waveforms are symmetrical.

[0066] After crossing, the positional relationship between the crossed clock signal line and the Vcom-FB line has good consistency, thereby reducing the coupling pull difference between different clock signal lines and the Vcom-FB line, and ensuring the consistency and stability of the display panel transmission signal. In the embodiment of the present application, the first clock signal and the second clock signal are only for reference, which represent two different clock signals and can also be replaced by different names or nouns, such as the third clock signal, the fourth clock signal, etc., which are not specifically limited here.

[0067] See Figure 4In the embodiment of the present application, the vertical length of the common voltage feedback compensation trace 302 is L. Furthermore, the orthographic projections of the various clock signal lines 303 on the common voltage feedback compensation trace 302 completely overlap with the common voltage feedback compensation trace 302. That is, the ends of the clock signal lines 303 are aligned with the ends of the Vcom-FB line, and their vertical lengths are also set to L. The specific value of the length L can be set based on the product specifications and sizes, and will not be further detailed here.

[0068] Specifically, because the clock signals in the intersecting clock signal lines are symmetrical, in the embodiments of the present application, the first clock signal line CLK1 and the fourth clock signal line CLK4 are intersected, the second clock signal line CLK2 and the fifth clock signal line CLK5 are intersected, and the third clock signal line CLK3 and the sixth clock signal line CLK6 are intersected. These two intersecting clock signal lines constitute a group. In the following embodiments, the first clock signal line CLK1 and the clock signal transmitted thereby, and the fourth clock signal line CLK4 and the clock signal transmitted thereby are used as examples for description.

[0069] The first clock signal line CLK1 and the fourth clock signal line CLK4 have an intersection O. To ensure consistency in the pull-pull effects between the different clock signal lines and Vcom-FB, this intersection O is located on the perpendicular bisector of the Vcom-FB line. That is, the projection of the intersection O coincides with the midpoint of Vcom-FB. This ensures good consistency between the different clock signal lines above and below the intersection O, thereby reducing variations in pull-pull effects and improving their effectiveness.

[0070] At the same time, the first clock signal line CLK1 is centrally symmetrically arranged with respect to the intersection O, and the fourth clock signal line CLK4 is also centrally symmetrically arranged with respect to the intersection O, thereby effectively ensuring a consistent pulling effect.

[0071] like Figure 5 As shown, Figure 5 for Figure 4 The timing diagram corresponding to each signal line is provided in . In the embodiment of the present application, since the clock signal within the first clock signal line CLK1 is symmetrical with the clock signal within the fourth clock signal line CLK4, and the two clock signal lines intersect at the intersection O, the clock signals within the two different clock signal lines have opposite polarities at the same timing. When they act on Vcom-FB respectively, they can cancel each other out, thereby effectively reducing the pull of the clock signal lines on the Vcom-FB line and balancing the voltage value of Vcom within the display panel, thereby improving the display quality problem of the panel.

[0072] To further reduce coupling pull variations, in the embodiment of the present application, the effective pulse width of the first clock signal within the first clock signal line CLK1 is equal to the effective pulse width of the second clock signal within the fourth clock signal line CLK4. Furthermore, the inactive pulse width of the first clock signal within the first clock signal line CLK1 is also equal to the inactive pulse width of the second clock signal within the fourth clock signal line CLK4. This effectively ensures that the signals within the interleaved clock signal lines are completely symmetrical at different time periods, thereby effectively reducing coupling pull variations and ensuring the stability of the timing signals within Vcom-FB.

[0073] Further, such as Figure 6 As shown, Figure 6 This is a schematic diagram of another arrangement structure of signal lines provided in an embodiment of the present application. Figure 4 In the wiring structure of the embodiment of the present application, a group of the first signal line 3031 and the second signal line 3032 intersecting is taken as an example. The signal line includes a straight section and a cross section 1013. Specifically, the first signal line 3031 includes a first straight section and a first cross section 1033, and the second signal line 3032 includes a second straight section and a second cross section 104. And each straight section corresponds to a different sub-section, such as the first straight section includes a first sub-section and a second sub-section, and the second straight section includes a third sub-section and a fourth sub-section. For details, see Figure 6 The first signal line 3031 includes a first sub-portion 1031, a second sub-portion 1032, and a first crossing section 1033. The first sub-portion 1031 is electrically connected to one end of the first crossing section 1033, and the other end of the first crossing section 1033 is electrically connected to the second sub-portion 1032. The first signal line 3031 is a continuously arranged signal line.

[0074] Meanwhile, the second signal line 3032 includes a third sub-section 101, a fourth sub-section 1012, and a second cross-section 104. The second cross-section 104 has two ends electrically connected to the third sub-section 101 and the fourth sub-section 1012, respectively. In the embodiment of the present application, the second signal line 3032 can be disconnected, with both sub-sections electrically connected via the second cross-section 104. Furthermore, the second cross-section 104 is connected across the first cross-section 1033 and insulated.

[0075] In the embodiment of the present application, the sub-portions of the first signal line 3031 and the second signal line 3032 extend in the same direction, such as a first direction, which is the same as the extension direction of the common voltage feedback compensation trace 302. Furthermore, the waveform of the clock signal in the first signal line 3031 is symmetrical to the waveform of the clock signal in the second signal line 3032.

[0076] At the same time, the straight section of the first signal line 3031 and the straight section of the second signal line 3032 are arranged parallel to each other, and the straight section of each signal line is parallel to the Vcom-FB line, thereby ensuring that the straight sections at different locations have consistent effects on the Vcom-FB line.

[0077] In the embodiment of the present application, the length of the straight section of the first signal line 3031 can be the same as the length of the straight section of the second signal line 3032. Specifically, the length of the first subsection 1031 of the first signal line 3031 is the same as the length of the second subsection 1032. The length of the first intersection section 1033 of the first signal line 3031 is the same as the length of the second intersection section 104 of the second signal line 3032. Alternatively, the first subsection 1031 of the first signal line 3031 and the third subsection 101 of the second signal line 3032 are arranged in parallel and have the same length, and the second subsection 1032 of the first signal line 3031 and the fourth subsection 1012 of the second signal line 3032 are arranged in parallel and have the same length.

[0078] Furthermore, the first sub-portion 1031 of the first signal line 3031 is set close to the common voltage feedback compensation routing 302, the second sub-portion 1032 is away from the common voltage feedback compensation routing 302, the third sub-portion 101 of the second signal line 3032 is set away from the common voltage feedback compensation routing 302, and the fourth sub-portion 1012 is set close to the common voltage feedback compensation routing 302.

[0079] In the embodiment of the present application, the first sub-section 1031 and the second sub-section 1032 are centrally symmetrically arranged with respect to the intersection O of the first intersection section 1033 and the second intersection section 104. Similarly, the third sub-section 101 and the fourth sub-section 1012 are centrally symmetrically arranged with respect to the intersection O of the first intersection section and the second intersection section. Thus, a cross structure of the embodiment of the present application is formed.

[0080] Furthermore, in an embodiment of the present application, the distance between the first sub-section 1031 and the third sub-section 101 is the same as the distance between the second sub-section 1032 and the fourth sub-section 1012, and the first sub-sections are arranged at equal intervals, the second sub-sections are arranged at equal intervals, the third sub-sections are arranged at equal intervals, and the fourth sub-sections are arranged at equal intervals.

[0081] At the same time, the distance between the first sub-section 1031 and the common voltage feedback compensation routing 302 is equal to the distance between the third sub-section 1012 and the common voltage feedback compensation routing 302; the distance between the third sub-section 101 and the common voltage feedback compensation routing 302 is equal to the distance between the second sub-section 1032 and the common voltage feedback compensation routing 302.

[0082] Furthermore, in an embodiment of the present application, the first sub-section and the third sub-section are alternately arranged, and the second sub-section and the fourth sub-section are alternately arranged.

[0083] In the embodiment of the present application, in the intersection section 1013, the first intersection section of the first signal line 3031 can be disconnected from the straight section and electrically connected through a corresponding connecting bridge. Figure 6 In the example, the second signal line 3032 is disconnected within the intersection section 1013. Similarly, the first signal line 3031 can be disconnected within the intersection section 1013, while the second signal line 3032 is continuously provided. This is not further described here. Furthermore, in the embodiment of the present application, when the corresponding signal line is disconnected within the intersection section 1013, the second intersection section or the first intersection section is provided on the same layer as the second metal layer or electrode layer of the display panel.

[0084] Furthermore, the routing widths of the different clock signal lines may be set to be the same width, and all of them may be smaller than the routing width of the Vcom-FB line.

[0085] In the embodiment of the present application, the first signal line 3031 and the second signal line 3032 can be different clock signal lines. The first signal line 3031 is the first clock signal line CLK1, and the second signal line 3032 is the fourth clock signal line CLK4. Specifically, the routing width of the first clock signal line CLK1 and the routing width of the fourth clock signal line CLK4 are the same, and both are smaller than the routing width of the Vcom-FB line. In the following embodiments, the signal lines are described using clock signal lines as an example.

[0086] In an embodiment of the present application, the routing widths of the cross sections corresponding to each clock signal line may be the same, and the routing widths of the cross sections are the same as the routing widths of the straight sections, thereby ensuring that each clock signal line has consistent impedance and interaction effects.

[0087] Furthermore, in the embodiment of the present application, the material of the first sub-section 1031 and the second sub-section 1032 can be the same metal material, such as the first sub-section 1031 and the second sub-section 1032 both use commonly used metal copper or other connecting wires. At the same time, the connecting bridge corresponding to the cross section 1013 can use a second metal layer or electrode layer, such as the connecting bridge corresponding to the second cross section 104 is a pixel electrode layer, and the material of the pixel electrode layer can be selected as an indium tin oxide film layer, thereby connecting the two separated clock signal lines through the pixel electrode layer in the display panel. In the actual production process, the above connection and arrangement structure only needs to change the mask position of the peripheral routing without setting a new number of masks, thereby effectively simplifying the preparation process of the above wiring and improving the performance of each routing.

[0088] Further, such as Figure 7-11 As shown, Figure 7-11This is a schematic diagram of the film layer structure corresponding to the fabrication process for the clock signal lines provided in the embodiments of the present application. When fabricating the aforementioned clock signal lines, a base substrate 383 is first deposited, and then various gate drive signal lines are deposited and etched on the base substrate 383 to form the various clock signal lines 303 in the embodiments of the present application. Optionally, the clock signal lines 303 are fabricated from a gate metal layer, using the same layer and material as the gate lines in the display area.

[0089] See Figure 7-11 After the clock signal lines 303 are prepared, a gate insulating layer 102 is formed on the clock signal lines 303. The gate insulating layer 102 completely covers each clock signal line 303. A passivation layer 103 is then formed on the gate insulating layer 102, and the passivation layer 103 and the gate insulating layer 102 are patterned. After the etching process is completed, part of the clock signal lines 303 is exposed, and an electrode layer 104 is deposited. The optional electrode layer 104 can be a layer of pixel electrode or common electrode, or an additional electrode layer, which is not limited here. The clock signal lines 303 on both sides are electrically connected through the electrode layer 104 to form a cross-connection bridge structure.

[0090] Further, such as Figure 12 As shown, Figure 12 This is another schematic diagram of the arrangement structure of the clock signal lines provided in the embodiment of the present application. In the embodiment of the present application, the clock signal lines corresponding to multiple groups of different symmetrical clock signals can also be cross-set. For example, the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 are respectively cross-set with the fourth clock signal line CLK4, the fifth clock signal line CLK5 and the sixth clock signal line CLK6. Figure 3 In the cross wiring structure, in the embodiment of the present application, multiple different clock signal lines are cross-arranged in the same cross section 1013.

[0091] Among them, when the above-mentioned multiple different clock signal lines are crossed, the clock signal lines corresponding to the middle of the crossing section 1013 are set continuously, such as the first clock signal line CLK1, the second clock signal line CLK2 and the third clock signal line CLK3 are set continuously, while the clock signal lines corresponding to both sides of the crossing section 1013 are disconnected and connected by means of a connecting bridge.

[0092] In the embodiment of the present application, by changing the number of clock signal lines that are intersected, the coupling pulling effect between different clock signal lines and the Vcom-FB line is further improved. Figure 12 , the CLK1 / 4 is a signal symmetry group, the CLK2 / 5 is a signal symmetry group, and the CLK3 / 6 is a signal symmetry group.

[0093] like Figure 13 As shown, Figure 13 for Figure 12 The timing diagram of the clock signal lines in . Under the corresponding timing, the pull relationship between each clock signal line and the Vcom-FB line can be:

[0094] The pull voltages of the clock signal lines CLK1 / 2 / 3 / 4 / 5 / 6 for Vcom-FB are labeled V1 / V2 / V3 / V4 / V5 / V6, respectively. Considering that each clock signal line can be pulled in both the up and down directions, the pull above the intersection of each clock signal line can be recorded as +V, and the pull below the intersection can be recorded as -V. For example, the pull of the first clock signal line can be recorded as +V1 / -V1.

[0095] Due to relative position and line length, for example, the pull effect on clock signal lines closer to Vcom-FB is stronger. Therefore, the above-mentioned pull effect also follows the following relationship: V1 = V4 > V2 = V5 > V3 = V6. At this point, for clock signal lines at the same distance from Vcom-FB, when CLK1 is pulled up, the pull amplitude on Vcom-FB is (+V1) + (-V4). Therefore, the up-pull and down-pull effects cancel each other out, and the total pull effect is approximately zero. Similarly, when CLK1 is pulled down, the pull amplitude on Vcom-FB is (-V1) + (+V4). The up-pull and down-pull effects also cancel each other out, and the total pull effect is also zero. Similarly, for other symmetrical clock signal lines, the pull effects on other clock signal lines are also approximately canceled out. This reduces the coupling pull differences between different clock signal lines, thereby ensuring the stability and consistency of each clock signal line.

[0096] like Figure 14 As shown, Figure 14 A schematic diagram of another clock signal line arrangement structure provided in an embodiment of the present application. In this embodiment of the present application, the clock signal line further includes a first cross group 881 and a second cross group 882. The first cross group 881 is located close to the Vcom-FB line, and the second cross group 882 is located away from the Vcom-FB line.

[0097] An even number of clock signal lines are provided in each of the first crossbar group 881 and the second crossbar group 882. The number of clock signal lines in the first crossbar group 881 is greater than the number of signal lines in the second crossbar group 882. This allows more clock signal lines to be closer to the Vcom-FB side, ensuring its pull-up effect.

[0098] In the embodiment of the present application, four clock signal lines are provided in the first crossbar group 881, and two clock signal lines are provided in the second crossbar group 882. Furthermore, the clock signals within the clock signal lines within each crossbar group are symmetrical. For example, the first clock signal is symmetrical with the fourth clock signal, the second clock signal is symmetrical with the fifth clock signal, and the third clock signal is symmetrical with the sixth clock signal.

[0099] Furthermore, because the number of signal lines in the first crossover group 881 is greater than the number of signal lines in the second crossover group 882, the length of the connecting bridge corresponding to the crossover segment of each clock signal line in the first crossover group is greater than the length of the connecting bridge in the second crossover group. To ensure the effectiveness of the different clock signal lines, the intersection points within each crossover group are located on the perpendicular bisector of the Vcom-FB line.

[0100] See Figure 15 , Figure 15 Provided in the embodiments of this application Figure 14 The timing diagram corresponding to each clock signal line in . In the embodiment of the present application, when each clock signal line interacts with the Vcom-FB line, V1=V4>V2=V5>V3=V6. At this time, for the clock signal lines with the same distance from the Vcom-FB, when CLK1 is pulled up, the pulling amplitude of Vcom FB is (+V1)+(-V4). Therefore, the up / down pulling can offset each other, and the total pulling effect is approximately 0; similarly, when CLK1 is pulled down, the pulling amplitude of Vcom FB is (-V1)+(+V4). The up / down pulling can offset each other, and the total pulling effect is also 0. Similarly, for other symmetrical clock signal lines, the pulling processes on other clock signal lines can also be approximately offset. This reduces the coupling pulling differences between different clock signal lines, thereby ensuring the stability and consistency of each clock signal line.

[0101] Therefore, in the embodiment of the present application, by changing the arrangement positions of different clock signal lines, two or more clock signal lines that transmit symmetrical clock signals are arranged in a cross-connected manner, thereby reducing the pulling differences between different clock signal lines, ensuring the transmission effect of the signals, and ensuring the normal display of the panel.

[0102] Furthermore, when the above-mentioned clock signal lines are cross-set, the clock signal lines in the same group may also include multiple different cross points, and the multiple different cross points are located at different positions of the clock signal lines. For example, if an even number of cross points are set, the even number of cross points divides each clock signal line into an even number of segments. After the clock signal lines in each segment interact with Vcom-FB, they can offset each other, thereby effectively improving the pulling difference between different clock signal lines.

[0103] Based on the same inventive concept, an embodiment of the present application further provides a display device, which includes the display panel provided in the above embodiment, wherein the display panel is provided with signal lines provided in the embodiment of the present application, and each signal line is arranged according to the above structure, thereby ensuring the normal operation of the display device and improving its display effect.

[0104] In summary, the application of the embodiments of the present application can achieve at least the following beneficial effects:

[0105] The display panel provided by the embodiment of the present application has multiple signal lines arranged in the routing area, wherein the signal lines include a common voltage feedback compensation routing line and multiple clock signal lines. Different clock signal lines transmit different clock signals, and the clock signals include at least one group of symmetrically arranged clock signals. At the same time, the clock signal lines corresponding to the symmetrical clock signals are cross-arranged. Since the clock signals in the two clock signal lines are symmetrical clock signals and the two clock signals are cross-arranged, the coupling pulling effects generated between the two different clock signal lines and the common voltage feedback compensation routing line will cancel each other out, thereby reducing the pulling difference between the clock signal lines and the common voltage feedback compensation routing line at different positions, thereby reducing the mutual influence problem between different signal routing lines and effectively improving the display effect of the display panel.

[0106] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0107] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A display panel comprising a display area and a wiring area located on at least one side of the display area, characterized in that: The routing area is provided with a gate drive circuit and a common voltage feedback compensation routing line, and the common voltage feedback compensation routing line extends along a first direction; a plurality of signal lines for providing signals to the gate drive circuit, the plurality of signal lines being arranged on a side of the common voltage feedback compensation line close to the display area, and the plurality of signal lines being insulated from each other; The plurality of signal lines include a first signal line and a second signal line, the first signal line and the second signal line are arranged to intersect, the first signal line includes a first straight section and a first crossing section, the second signal line includes a second straight section and a second crossing section, and the first straight section and the second straight section both extend along the first direction; The first signal line includes a first clock signal line for transmitting a first clock signal, and the second signal line includes a second clock signal line for transmitting a second clock signal; The signal waveform of the first clock signal is symmetrical to the signal waveform of the second clock signal.

2. The display panel according to claim 1, wherein: The effective pulse width of the first clock signal is equal to the ineffective pulse width of the second clock signal, and the ineffective pulse width of the first clock signal is equal to the effective pulse width of the second clock signal.

3. The display panel according to claim 1, wherein: The first straight section includes a first subsection and a second subsection, and the first subsection and the second subsection are connected by the first crossing section; The second straight section includes a third subsection and a fourth subsection, and the third subsection and the fourth subsection are connected by the second crossing section; Wherein, the first sub-portion is arranged close to the common voltage feedback compensation wiring, and the second sub-portion is arranged away from the common voltage feedback compensation wiring; The third sub-portion is arranged away from the common voltage feedback compensation line, and the fourth sub-portion is arranged close to the common voltage feedback compensation line.

4. The display panel according to claim 3, wherein: The first sub-section and the second sub-section are centrally symmetrically arranged relative to an intersection of the first intersection section and the second intersection section; The third sub-section and the fourth sub-section are centrally symmetrically arranged relative to an intersection point of the first intersection section and the second intersection section.

5. The display panel according to claim 3, wherein: The distance between the first sub-section and the third sub-section is equal to the distance between the second sub-section and the fourth sub-section; Furthermore, the first sub-sections are arranged at equal intervals, the second sub-sections are arranged at equal intervals, the third sub-sections are arranged at equal intervals, and the fourth sub-sections are arranged at equal intervals.

6. The display panel according to claim 3, wherein: The first sub-section, the first intersection section and the second sub-section are continuously arranged, and the third sub-section and the fourth sub-section are disconnected and bridged by the second intersection section; Alternatively, the third subsection, the second intersection segment and the fourth subsection are continuously arranged, and the first subsection and the second subsection are disconnected and bridged by the first intersection segment.

7. The display panel according to claim 6, wherein: When the third sub-section and the fourth sub-section are disconnected and bridged by the second crossing section, the second crossing section is provided on the same layer as the second metal layer or the electrode layer of the display panel; When the first sub-portion and the second sub-portion are disconnected and bridged by the first crossing segment, the first crossing segment is provided on the same layer as the second metal layer or the electrode layer of the display panel.

8. The display panel according to claim 3, wherein: The first sub-section and the third sub-section are arranged alternately, and the second sub-section and the fourth sub-section are arranged alternately; Alternatively, each of the first sub-units is arranged in sequence close to the common voltage feedback compensation routing, each of the third sub-units is arranged in sequence away from the common voltage feedback compensation routing, and each of the second sub-units is arranged in sequence away from the common voltage feedback compensation routing, and each of the fourth sub-units is arranged in sequence close to the common voltage feedback compensation routing.

9. The display panel according to claim 1, wherein: The orthographic projection of the signal line on the common voltage feedback compensation line coincides with the common voltage feedback compensation line.

10. The display panel according to claim 1, wherein The plurality of signal lines include a first cross group and a second cross group; The first cross group and the second cross group both include at least an even number of traces, and the clock signals corresponding to the signal lines in the first cross group and the second cross group are symmetrical in pairs.

11. The display panel according to claim 10, wherein: The first cross group is arranged close to the common voltage feedback compensation line, and the second cross group is arranged away from the common voltage feedback compensation line; The number of the signal lines in the first crossing group is greater than the number of the signal lines in the second crossing group.

12. The display panel according to claim 10, wherein: The length of the corresponding crossing segment in the first crossing group is greater than the length of the corresponding crossing segment in the second crossing group.

13. The display panel according to claim 1, wherein: The intersection of the first signal line and the second signal line is located on the perpendicular bisector of the common voltage feedback compensation line.

14. A display device, characterized in that: The device comprises a display panel according to any one of claims 1 to 13.

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