FPGA external large-capacity memory multi-port access system based on data tag technology

Abstract

The present invention relates to the technical field of FPGA system design, and in particular to an FPGA external large-capacity memory multi-port access system based on data tag technology. The system comprises a data path corresponding to an external memory access module, a time slice generation module, a tag binding module, a tag management module, a tag cache, and a data tag identification module. The read and write instructions of the memory access module and the corresponding data path are both processed in a single cycle and have no mutual influence. The system can immediately respond to read and write requests from other modules without waiting for the end of the instruction processing cycle. The time slice generation module uses a maximum time slice scheduling method to provide authorization signals to the data path, the tag binding module, and the tag management module, thereby avoiding abnormal interface occupation and improving the stability and robustness of the system. The system uses data tags as verification data to complete data reading, so that the DRAM link has a self-recovery feature and further eliminates coupling interference between memory access modules.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA system design, and in particular to an FPGA external large-capacity memory multi-port access system based on data tag technology. Background Art

[0002] As a large-scale programmable logic, FPGA provides abundant register and routing resources. However, due to process and cost constraints, its on-chip memory capacity is limited. Most existing FPGAs have on-chip memory capacity at the MB level. However, with the development of various sensors, the data that FPGAs need to cache has reached the GB level, and the on-chip memory capacity can no longer meet the needs of the system. When expanding the FPGA system's large-capacity memory, large-capacity, high-speed, low-cost DRAM-type memory is usually used externally, such as DDR2, DDR3, DDR4, etc. At the same time, in typical application scenarios, there are often multiple functional modules in the system that need to access the external DRAM memory, and DRAM memory only has one read and write port. To solve this problem, a variety of memory sharing methods have been developed, including physical bus interfaces, using IP to access multiple DRAM ports, and access arbitration methods. However, these methods still have the following problems:

[0003] 1) The physical bus interface method requires special processing of the switching function circuit wiring, which increases the cost and complexity of the system;

[0004] 2) Using IP to access the multi-port DRAM requires designing the access interface of the functional module as an AXI bus standard interface, but the AXI bus interface protocol is complex and difficult to implement;

[0005] 3) The main disadvantage of using access arbitration is that due to the inherent read latency of DRAM, returned data has a certain time lag, and other access requests must wait for the current operation to complete before responding to other access requests. This disadvantage results in long access gaps when the memory access module's memory access needs are discontinuous, resulting in frequent module switching, which greatly reduces the bandwidth utilization of the memory interface. In addition, if the memory access module encounters an anomaly, such as an inability to cancel the arbitration request signal or an incorrect data operation length, the arbitration logic will not function, indirectly affecting the use of the interface by other memory access modules, and lacking fault tolerance. Summary of the Invention

[0006] In order to solve the above problems, the present invention provides an FPGA external large-capacity memory multi-port access system based on data tag technology. The memory access modules are independent of each other and there is no mutual coupling influence. The instructions are all single-cycle instructions. There is no need to wait for the response of the instruction to be completed. The pipeline characteristics of DRAM can be fully utilized to continuously initiate access, which solves the shortcomings of the existing methods such as low bandwidth utilization, high cost, complex interface implementation, large coupling between access ports, and poor fault tolerance.

[0007] The FPGA external large-capacity memory multi-port access system based on data tag technology provided by the present invention includes a data path, a time slice generation module, a tag binding module, a tag management module, a tag cache and a data tag identification module; wherein,

[0008] The external memory access module sends read and write instructions to the time slice generation module, label binding module and data label identification module through a unified interface through the data path, and the number of data paths is consistent with the number of memory access modules;

[0009] The data path is used to transmit read and write instructions and storage data from the memory access module, and to control the flow of the memory access module;

[0010] The time slice generation module is used to detect the read and write instructions in the data path and send an authorization signal to the data path and label binding module. The data path transmits the read and write instructions and storage data to the label binding module according to the authorization signal;

[0011] The tag binding module combines the authorization signal with the unique data tag of each access module and integrates the data tag and the stored data to generate a signature data packet;

[0012] The tag management module is used to receive the signed data packet and parse the read / write instructions, data tags, and instruction addresses in the signed data packet: if the read / write instructions in the signed data packet are write instructions, the signed data packet is sent to the external DRAM controller; if the read / write instructions in the signed data packet are read instructions, the signed data packet is sent to the external DRAM controller and simultaneously sent to the tag cache for caching the data tags and instruction addresses;

[0013] The tag cache is connected to the data feedback terminal of the DRAM controller and is used to receive feedback data provided by the DRAM controller from the external DRAM according to the read instruction, synchronously read the data tag and instruction address in the tag cache, integrate the feedback data and its corresponding data tag and instruction address into a new signature data packet, and transmit it to the data tag identification module;

[0014] The data tag identification module extracts the corresponding data tag based on the new signature data packet, and transmits the feedback data to the corresponding memory access module through the data path according to the data tag.

[0015] Furthermore, the data path uses a first-in-first-out memory to provide a unified data interface for the memory access module. The data interface is divided into three fields: command segment, address segment and data segment. The command segment is used to store read and write instructions, the address segment is used to store the instruction address of the stored data, and the data segment is used to store the stored data.

[0016] The data path also includes a write clock signal and a write enable signal for controlling the first-in-first-out memory;

[0017] The data path provides a full signal to the memory access module to control the flow of the memory access module; the data path feeds back a valid signal and a time slice threshold T to the time slice generation module. The valid signal is used to start the time slice generation module; the time slice threshold T is a different maximum length time slice threshold preset according to each memory access module.

[0018] Furthermore, the time slice generation module includes scheduling logic and a time slice counter;

[0019] After receiving the valid signal, the scheduling logic sends an authorization signal, feeds back a ready signal to the data path, and sends a working signal to the time slice counter.

[0020] After receiving the working signal, the time slice counter starts counting the time slices in combination with the time slice threshold T:

[0021] When the count reaches the time slice threshold T, the time slice counter sends an end signal to the scheduling logic to revoke the authorization;

[0022] When the count reaches the time slice threshold T, if the data path actively withdraws the valid signal, the scheduling logic controls the time slice counter to end counting in advance.

[0023] Furthermore, the label binding module includes a label generator and data flow control; wherein,

[0024] Data flow control is used to control the flow of data from the data path;

[0025] The tag generator generates exclusive tag data according to the number of memory access modules, and packages the output data of the data flow control in a bit-expanded manner to obtain a signature data packet.

[0026] Furthermore, the write clock signal, write enable signal and the operation of binding the read and write instructions to the tag in the tag binding module are synchronized with the module operation clock, are single-cycle operations, and the write clock signal and write enable signal are valid at high level.

[0027] Furthermore, the tag management module includes instruction word judgment logic and a timing controller; wherein,

[0028] The instruction word judgment logic extracts and judges the read and write instructions in the current signature data packet: If the read or write instruction is a read instruction, the instruction word judgment logic passes the read instruction to the timing controller, extracts the data tag and instruction address in the signature data packet, and writes them together into the tag cache;

[0029] The timing controller sends the read / write instructions, storage data, and instruction address in the current signature data packet to the DRAM controller, and the DRAM controller outputs feedback data through the data feedback terminal;

[0030] The timing controller also feeds back a ready signal to the data flow control, and the data flow control adjusts the data flow according to the ready signal. That is, when the timing controller continuously feeds back a ready signal to the data flow control, the data flow control extracts instructions, addresses, and data from the data path to which they belong, and passes them to the label generator for label binding operations.

[0031] Furthermore, the tag cache synchronously reads out the data tag and instruction address corresponding to the feedback data, and superimposes them with the feedback data to generate a new signature data packet and transmit it to the data tag identification module.

[0032] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0033] 1) The system provided by the present invention is implemented by logic software, without the need to modify existing circuit designs and dedicated chips, thus reducing hardware costs;

[0034] 2) No need to implement complex AXI bus protocol overhead; the maximum time slice scheduling method is adopted to avoid abnormal interface occupancy and improve the stability and robustness of the system;

[0035] 3) A data tagging scheme is proposed. Read and write instructions of each memory access module are processed in a single cycle without affecting each other. Read and write requests from other modules can be immediately responded to without waiting for the instruction processing cycle to end. This solves the problem of read data crosstalk caused by interleaved read accesses from multiple modules, greatly improving the access efficiency of the DRAM interface.

[0036] 4) The tag itself can be used as verification data, and mismatched data will be discarded, making the DRAM link self-recovering. This further eliminates the coupling interference between memory access modules and realizes completely independent and efficient DRAM multi-port access technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is an overall structural diagram of an FPGA external large-capacity memory multi-port access system based on data tag technology provided according to an embodiment of the present invention;

[0038] Figure 2is a schematic structural diagram of a time slice generation module provided according to an embodiment of the present invention;

[0039] Figure 3 is a structural diagram of a label binding module provided according to an embodiment of the present invention;

[0040] Figure 4 FIG. 4 is a structural diagram of a tag management module provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0042] The present invention provides an FPGA external large-capacity memory multi-port access system based on data tag technology, which is implemented by logic software and proposes a data tag scheme. The read and write instructions of each memory access module are all processed in a single cycle and have no influence on each other. This greatly improves the access efficiency of the DRAM interface. At the same time, the DRAM link has a self-recovery feature, which further eliminates the coupling interference between memory access modules and realizes a completely independent and efficient DRAM multi-port access technology.

[0043] Figure 1 The overall structure of the FPGA external large-capacity memory multi-port access system based on data tag technology provided according to an embodiment of the present invention is shown.

[0044] like Figure 1 As shown, the FPGA external large-capacity memory multi-port access system based on data tag technology provided by the embodiment of the present invention includes a data path, a time slice generation module, a tag binding module, a tag management module, a tag cache and a data tag identification module.

[0045] Among them, the data path is bidirectionally connected to the external memory access module through a unified interface, and the number of data paths is consistent with the number of memory access modules, which is used to complete the transmission of read and write instructions and storage data in the memory access module, as well as to control the flow of the memory access module.

[0046] The data path is also bidirectionally connected to the time slice generation module, the tag binding module, and the data tag identification module. The time slice generation module detects read and write instructions in the data path and issues authorization signals to the data path and tag binding module. Based on the authorization signals, the data path transmits the read and write instructions and stored data to the tag binding module. The tag binding module, combined with the authorization signals, generates a signature data packet based on the unique data tag for each memory access module and the stored data.

[0047] The tag management module is used to receive signed data packets and parse the read and write instructions, data tags and instruction addresses in the signed data packets: if the read and write instructions in the signed data packets are write instructions, the signed data packets are sent to the external DRAM controller; if the read and write instructions in the signed data packets are read instructions, the signed data packets are sent to the external DRAM controller and sent to the tag cache for caching of the data tags and instruction addresses.

[0048] The tag cache is connected to the data feedback end of the DRAM controller, and is used to receive the feedback data provided by the DRAM controller from the external DRAM according to the read instruction, synchronously read the data tag and instruction address in the tag cache, integrate the feedback data and its corresponding data tag and instruction address into a new signature data packet, and transmit it to the data tag identification module.

[0049] The data tag identification module extracts the corresponding data tag based on the new signature data packet, and transmits the feedback data to the corresponding memory access module through the data path according to the data tag.

[0050] The data path uses a first-in, first-out memory to provide a unified data interface for the memory access module. In this embodiment of the present invention, the data interface is 547 bits of data, divided into three fields: command segment, address segment, and data segment. The command segment occupies 3 bits and is used to store read and write instructions; the address segment occupies 32 bits and is used to store the instruction address of the stored data; and the data segment occupies 512 bits and is used to store the stored data.

[0051] The data path also includes a write clock signal and a write enable signal to control the first-in, first-out memory. The write enable signal is synchronized with the write clock signal and is active high for a single cycle, eliminating the overhead of complex protocols such as AXI interfaces.

[0052] The data path provides a full signal to the memory access module to control its traffic flow. It also feeds a valid signal and a time slice threshold T back to the time slice generation module. The valid signal activates the time slice generation module. The time slice threshold T uses a maximum time slice scheduling method, which sets a different maximum time slice threshold based on the actual traffic flow of each memory access module.

[0053] Figure 2 The structure of the time slice generation module provided according to an embodiment of the present invention is shown.

[0054] like Figure 2 As shown, the time slice generation module includes scheduling logic and a time slice counter.

[0055] After receiving the valid signal, the scheduling logic sends a grant signal, feeds a ready signal back to the data path, and sends a working signal to the time slice counter. After receiving the working signal, the time slice counter starts counting time slices based on the time slice threshold T.

[0056] The authorization signal has two termination conditions: the absence of valid read or write instructions on the currently authorized path and the current count reaching the time slice threshold T. Once the time slice generation module determines that the termination condition has been met, it immediately terminates the current authorization. The time slice counter sends an end signal to the scheduling logic to revoke the authorization and begins detecting the status of the next data path.

[0057] When the count reaches the time slice threshold T, if the data path actively withdraws the valid signal, the scheduling logic controls the time slice counter to end counting in advance.

[0058] Figure 3 The structure of the label binding module provided according to an embodiment of the present invention is shown.

[0059] like Figure 3 As shown, the label binding module includes a label generator and data flow control.

[0060] The data flow control receives a ready signal from the tag management module to control the flow of data from the data path. The tag generator generates exclusive tag data based on the number of memory access modules and packages the output data of the data flow control using bit expansion to obtain a signed data packet.

[0061] During this process, as long as the data flow control receives the ready signal, the data flow control and label generator continue to bind labels to read and write instructions. This operation is synchronized with the module operation clock and is a single-cycle operation. There is no need to wait for the signature data packet corresponding to the read instruction to be returned from DRAM, which overcomes the impact of read latency on the software. There is no waiting state, and the bandwidth of the DRAM interface is more fully utilized.

[0062] Figure 4 The structure of the tag management module provided according to an embodiment of the present invention is shown.

[0063] like Figure 4 As shown, the tag management module includes instruction word judgment logic and a timing controller.

[0064] Among them, the instruction word judgment logic extracts and judges the read and write instructions in the current signature data packet: if the read and write instructions are read instructions, the instruction word judgment logic transmits the read instruction to the timing controller while extracting the data tag and instruction address in the signature data packet and writing them into the tag cache together.

[0065] The timing controller sends the read and write instructions, storage data and instruction address in the current signature data packet to the DRAM controller, and the DRAM controller outputs feedback data through the data feedback terminal.

[0066] The timing controller also feeds back a ready signal to the data flow control, and the data flow control adjusts the data flow according to the ready signal. That is, when the timing controller continuously feeds back a ready signal to the data flow control, the data flow control extracts instructions, addresses, and data from the data path to which they belong, and passes them to the label generator for label binding operations.

[0067] The tag cache synchronously reads out the data tag and instruction address corresponding to the feedback data, and superimposes them with the feedback data to generate a new signature data packet and transmit it to the data tag discrimination module.

[0068] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. This is not limited herein.

[0069] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A FPGA external large-capacity memory multi-port access system based on data tag technology, characterized in that: It includes data path, time slice generation module, label binding module, label management module, label cache and data label identification module; among them, The external memory access module sends read and write instructions to the time slice generation module, the label binding module and the data label identification module through the data path using a unified interface, and the number of the data paths is consistent with the number of the memory access modules; The data path is used to transmit the read and write instructions and the storage data from the memory access module, and to control the flow of the memory access module; The time slice generation module is used to detect the read and write instructions in the data path and send an authorization signal to the data path and the label binding module, and the data path transmits the read and write instructions and storage data to the label binding module according to the authorization signal; The tag binding module combines the authorization signal with a unique data tag for each memory access module and integrates the data tag and the stored data to generate a signature data packet; The tag management module is used to receive the signature data packet and parse the read / write instruction, data tag, and instruction address in the signature data packet: if the read / write instruction in the signature data packet is a write instruction, the signature data packet is sent to the external DRAM controller; if the read / write instruction in the signature data packet is a read instruction, the signature data packet is sent to the external DRAM controller and simultaneously sent to the tag cache for caching the data tag and the instruction address; The tag cache is connected to the data feedback terminal of the DRAM controller, and is used to receive feedback data obtained by the DRAM controller from the external DRAM according to the read instruction, synchronously read out the data tag and instruction address in the tag cache, integrate the feedback data and its corresponding data tag and instruction address into a new signature data packet, and transmit it to the data tag identification module; The data tag identification module extracts the corresponding data tag according to the new signature data packet, and transmits the feedback data to the corresponding memory access module through the data path according to the data tag.

2. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 1 is characterized in that: The data path adopts a first-in-first-out memory and provides a unified data interface for the memory access module. The data interface is divided into three fields: a command segment, an address segment, and a data segment. The command segment is used to store the read and write instructions, the address segment is used to store the stored data at the instruction address, and the data segment is used to store the stored data. The data path also includes a write clock signal and a write enable signal for controlling the first-in first-out memory; The data path provides a full signal to the memory access module for controlling the flow of the memory access module; the data path feeds back a valid signal and a time slice threshold T to the time slice generation module, and the valid signal is used to start the time slice generation module; the time slice threshold T is a maximum length time slice threshold preset according to each memory access module.

3. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 2 is characterized in that: The time slice generation module includes scheduling logic and a time slice counter; The scheduling logic sends a grant signal after receiving the valid signal, feeds back a ready signal to the data path, and sends a working signal to the time slice counter; After receiving the working signal, the time slice counter starts counting time slices in combination with the time slice threshold T: When the count reaches the time slice threshold T, the time slice counter sends an end signal for revoking authorization to the scheduling logic; When the count reaches the time slice threshold T, if the data path actively withdraws the valid signal, the scheduling logic controls the time slice counter to end counting in advance.

4. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 3 is characterized in that: The label binding module includes a label generator and data flow control; wherein, The data flow control is used to control the flow of data from the data path; The label generator generates exclusive label data according to the number of the memory access modules, and packages the output data of the data flow control in a bit extension manner to obtain the signature data packet.

5. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 4 is characterized in that: The write clock signal, the write enable signal and the operation of binding the read and write instructions to the tag in the tag binding module are synchronized with the module operation clock and are all single-cycle operations, and the write clock signal and the write enable signal are valid at high level.

6. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 4 is characterized in that: The tag management module includes instruction word judgment logic and a timing controller; wherein, The instruction word judgment logic extracts and judges the read / write instruction in the current signature data packet: if the read / write instruction is a read instruction, the instruction word judgment logic transmits the read instruction to the timing controller, extracts the data tag and instruction address in the signature data packet, and writes them together into the tag cache; The timing controller sends the read and write instructions, storage data and instruction address in the current signature data packet to the DRAM controller, and the DRAM controller outputs the feedback data through the data feedback terminal; The timing controller also feeds back a ready signal to the data flow control, and the data flow control adjusts the data flow according to the ready signal. That is, when the timing controller continuously feeds back a ready signal to the data flow control, the data flow control extracts instructions, addresses and data from the data path to which they belong, and passes them to the label generator for label binding operation.

7. The FPGA external large-capacity memory multi-port access system based on data tag technology according to claim 6 is characterized in that: The tag cache synchronously reads out the data tag and instruction address corresponding to the feedback data, and superimposes them with the feedback data to generate the new signature data packet and transmit it to the data tag identification module.

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