An oxide array substrate with reduced parasitic capacitance effect and its fabrication method

Abstract

This invention provides an oxide array substrate with reduced parasitic capacitance effect and its fabrication method, comprising a substrate, a bottom gate, a first insulating layer, a semiconductor layer, a second insulating layer, a top gate, driving circuit traces, a first intermediate insulating layer, a first transparent conductive layer, a third metal layer, a second intermediate insulating layer, and a second transparent conductive layer. The semiconductor layer has conductive regions at both ends of a first semiconductor unit, and a second semiconductor unit corresponds to the bottom gate. The top gate is located above the first semiconductor unit. The first source and drain of the third metal layer are connected to the conductive regions, and the second source and drain are connected to the second semiconductor unit. The first metal unit is connected to the driving circuit traces. The top gate corresponds to a TFT driving circuit region, the bottom gate corresponds to a TFT display region, and the driving circuit traces correspond to a metal line region. This invention has fewer film layers, higher light transmittance, and higher thin film utilization, thus improving the problem of large parasitic capacitance in existing structures.

Description

[Technical Field]

[0001] This invention relates to the field of liquid crystal display technology, specifically to an oxide array substrate that can reduce parasitic capacitance effect and its preparation method. [Background Technology]

[0002] In the field of liquid crystal displays (LCDs), FFS (Fringe Field Switching) technology is a liquid crystal display technology that utilizes the edge electric field generated between the top strip pixel electrodes and the bottom planar COM electrodes (Bottom COM) or between the top COM pixel electrodes and the bottom planar pixel electrodes (Bop COM) on the TFT substrate. This allows liquid crystal molecules between the electrodes and directly above the electrodes to rotate in a plane parallel to the substrate. LCD panels employing the FFS pixel structure feature high transmittance, high viewing angle, high contrast, and high color gamut, making it the primary pixel structure type for high-end LCD panels.

[0003] Thin-film transistors (Mox-TFTs) fabricated using metal-oxide-semiconductor materials have become one of the important development technologies for array substrates in display panels due to their advantages such as low leakage current, high field-effect mobility, and good regional uniformity. Existing array substrates fabricated using Mox-TFTs generally employ bottom-gate TFT structures, such as etch-block (ESL) and back-channel (BCE) types, or top-gate TFT structures, such as self-aligned top-gate types. Different types of TFTs have their own structural advantages when applied to array substrates. Back-channel bottom-gate TFTs have advantages such as simple structure, short process flow, low cost, and high yield. However, due to the large overlap area between the gate and source / drain electrodes in the bottom-gate structure, and the fact that the gate and source / drain electrodes are only separated by a gate insulating layer, the small spacing results in a large parasitic capacitance between the upper and lower metal lines, increasing power consumption and hindering the development of high-resolution, high-refresh-rate display panels. In the self-aligned top-gate TFT structure, there is virtually no overlap between the gate and the source / drain. A thicker intermediate insulating layer is provided between the upper and lower metals, resulting in a smaller overall parasitic capacitance. However, the self-aligned top-gate TFT structure is relatively complex and the fabrication process is quite cumbersome. An additional light-shielding layer is also required in the liquid crystal display panel to reduce the impact of backlight on the light leakage of the semiconductor material. This metal layer only serves as a light-shielding layer, resulting in a high processing time but low film utilization, which is not conducive to cost reduction. [Summary of the Invention]

[0004] One of the technical problems to be solved by the present invention is to provide an oxide array substrate that can reduce the parasitic capacitance effect. It has fewer film layers and higher light transmittance, which can improve the problems of large parasitic capacitance and single function of light shielding layer in the existing structure. It also has the advantages of low cost and high film utilization.

[0005] The present invention achieves one of the above-mentioned technical problems in the following way:

[0006] An oxide array substrate for reducing parasitic capacitance effects, the oxide array substrate comprising: a substrate,

[0007] A first metal layer is disposed on the substrate, and the first metal layer includes a bottom gate;

[0008] A first insulating layer is disposed on the first metal layer;

[0009] A semiconductor layer is disposed on the first insulating layer. The semiconductor layer includes a first semiconductor unit and a second semiconductor unit. The two ends of the first semiconductor unit are respectively conductive to form conductive regions. The position of the second semiconductor unit corresponds to the position of the bottom gate.

[0010] A second insulating layer is disposed on the semiconductor layer;

[0011] A first transparent conductive layer is disposed on the second insulating layer;

[0012] A second metal layer is disposed on the second insulating layer. The second metal layer includes a top gate and driving circuit traces. The top gate is located above the first semiconductor cell.

[0013] An intermediate insulating layer is disposed on the second metal layer. The first intermediate insulating layer has a first through-hole, a second through-hole, and a third through-hole. There are two first through-holes, which are respectively located on both sides of the top gate, penetrate downward through the second insulating layer, and expose the upper surface of the conductor regions at both ends of the first semiconductor unit. There are two second through-holes, which are respectively located above the second semiconductor unit, penetrate downward through the second insulating layer, and expose the upper surface of the second semiconductor unit. The third through-hole is located above the driving circuit trace, exposing the upper surface of the driving circuit trace.

[0014] A second transparent conductive layer is disposed on the intermediate insulating layer;

[0015] A third metal layer is disposed on the intermediate insulating layer. The third metal layer includes a first source, a first drain, a second source, a second drain, and a metal unit one. The first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias. The second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias. The metal unit one is connected to the driving circuit traces through a third via.

[0016] When the first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode, the driving circuit traces are laid on the first transparent conductive layer, and one end of the second drain is also connected to one end of the second transparent conductive layer.

[0017] The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

[0018] Furthermore, the non-channel regions at both ends of the first semiconductor unit are subjected to ion doping treatment to make the region conductive, forming a conductive region.

[0019] Furthermore, when the first transparent conductive layer is a pixel electrode and the second transparent conductive layer is a common electrode, a fourth through hole is also provided on the intermediate insulating layer. The fourth through hole is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer overlaps with the metal unit.

[0020] The second technical problem to be solved by the present invention is to provide a method for preparing an oxide array substrate that can reduce the parasitic capacitance effect. The prepared oxide array substrate can improve the problems of large parasitic capacitance and single function of light-shielding layer in the existing structure, and also has the advantages of low cost, simple structure and high thin film utilization.

[0021] The present invention achieves the second technical problem mentioned above in the following way:

[0022] A method for fabricating an oxide array substrate that can reduce parasitic capacitance effect, the method comprising the following steps:

[0023] Step 1: Form a first metal layer on the substrate to fabricate the bottom gate and related drive signal lines;

[0024] Step 2: Form a first insulating layer on the first metal layer; the first insulating layer in the display area serves as the bottom gate TFT gate insulating layer, and the first insulating layer in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit;

[0025] Step 3: Form a semiconductor layer on the first insulating layer and prepare the first semiconductor unit and the second semiconductor unit. Then, perform conductor treatment on the left and right ends of the first semiconductor unit to form a conductor region.

[0026] Step 4: Form a second insulating layer on the semiconductor layer as the gate insulating layer of the top gate TFT;

[0027] Step 5: Form a first transparent conductive layer on the second insulating layer.

[0028] Step 6: Form a second metal layer on the second insulating layer, and fabricate the top gate and drive circuit traces, or other signal traces;

[0029] Step 7: Form an intermediate insulating layer on the second metal layer;

[0030] Step 8: Form a second transparent conductive layer on the intermediate insulating layer; then, prepare a first through-hole, a second through-hole, and a third through-hole on the intermediate insulating layer, exposing the upper surface of the conductor region at both ends of the first semiconductor unit, the upper surface of the second semiconductor unit, and the upper surface of the driving circuit trace, respectively.

[0031] Step 9: Form a third metal layer on the intermediate insulating layer, and fabricate a first source, a first drain, a second source, a second drain, and a metal unit 1; wherein the first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias; the second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias; the metal unit 1 is connected to the driving circuit traces through a third via;

[0032] When the first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode, the driving circuit traces are laid on the first transparent conductive layer, and one end of the second drain is also connected to one end of the second transparent conductive layer.

[0033] The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

[0034] Furthermore, when the first transparent conductive layer is a pixel electrode and the second transparent conductive layer is a common electrode, a fourth through hole is also provided on the intermediate insulating layer. The fourth through hole is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer overlaps with the metal unit.

[0035] Furthermore, the first metal layer, the second metal layer, and the third metal layer are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0036] Furthermore, the first insulating layer, the second insulating layer, and the intermediate insulating layer are single-layer or multi-layer structures, and the materials are selected from inorganic oxides or compounds with insulating properties.

[0037] Furthermore, the first transparent conductive layer and the second transparent conductive layer are made of ITO.

[0038] The present invention has the following advantages:

[0039] The present invention provides top-gate and bottom-gate TFT devices at corresponding positions in the driving circuit area and display area of ​​the array substrate, respectively. Therefore, the array substrate structure retains the low parasitic capacitance driving advantage of the top-gate structure and overcomes the disadvantage of the single function of the added light-shielding layer in the existing structure, thereby improving the utilization of the thin film. By placing the first transparent conductive layer below the second metal layer, the present invention can further simplify the film structure and has higher light transmittance, which can further reduce the manufacturing cost and is suitable for the low-cost development of high-resolution and high-refresh-rate display panels.

[0040] In addition, the present invention performs conductor treatment on both ends of the semiconductor layer at the top gate TFT position, which can reduce the contact resistance of the source and drain contact regions. [Attached Image Description]

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0042] Figure 1 This is a schematic diagram of the structure of an oxide array substrate that can reduce parasitic capacitance effect according to the present invention.

[0043] Figure 2 This is another structural schematic diagram of an oxide array substrate that can reduce parasitic capacitance effect according to the present invention.

[0044] Figure 3 This is a flowchart of steps 1-5 of a method for fabricating an oxide array substrate that can reduce parasitic capacitance effect according to the present invention.

[0045] Figure 4 This is a flowchart of steps 6-9 of a method for fabricating an oxide array substrate that can reduce parasitic capacitance effect according to the present invention.

[0046] Explanation of reference numerals in the attached figures:

[0047] Glass substrate 1;

[0048] First metal layer 2, bottom gate 21;

[0049] First insulating layer 3;

[0050] Semiconductor layer 4, first semiconductor unit 41, second semiconductor unit 42, conductor region 43;

[0051] Second insulating layer 5;

[0052] First transparent conductive layer 6;

[0053] Second metal layer 7, top gate 71, drive circuit trace 72;

[0054] Intermediate insulating layer 8, first through hole 81, second through hole 82, third through hole 83, fourth through hole 84;

[0055] Second transparent conductive layer 9;

[0056] Third metal layer 10, first source 101, first drain 102, second source 103, second drain 104, metal unit 105;

[0057] The driving circuit area is TFT 100, the display area is TFT 200, and the metal line area is 300.

Detailed Implementation Methods

[0058] The following will be combined with the appendix Figure 1-4 The technical solution of the present invention will be clearly and completely described in detail with specific embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.

[0059] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0060] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0061] Please see Figure 1 As shown, the present invention relates to an oxide array substrate that can reduce parasitic capacitance effects, the oxide array substrate comprising: a substrate 1,

[0062] A first metal layer 2 is disposed on the substrate 1, and the first metal layer 2 includes a bottom gate 21;

[0063] A first insulating layer 3 is disposed on the first metal layer 2;

[0064] Semiconductor layer 4 is disposed on the first insulating layer 3. Semiconductor layer 4 includes a first semiconductor unit 41 and a second semiconductor unit 42. The two ends of the first semiconductor unit 41 are respectively conductive to form a conductive region 43. The position of the second semiconductor unit 42 corresponds to the position of the bottom gate 21.

[0065] A second insulating layer 5 is disposed on the semiconductor layer 4;

[0066] A first transparent conductive layer 6 is disposed on the second insulating layer 5;

[0067] The second metal layer 7 is disposed on the second insulating layer 5. The second metal layer 7 includes a top gate 71 and a driving circuit trace 72. The top gate 71 is located above the first semiconductor unit 41.

[0068] An intermediate insulating layer 8 is disposed on the second metal layer 7. The intermediate insulating layer 8 has a first through hole 81, a second through hole 82, and a third through hole 83. There are two first through holes 81, which are located on both sides of the top gate 71 and penetrate downward through the second insulating layer 5, exposing the upper surface of the conductor regions 43 at both ends of the first semiconductor unit 41. There are two second through holes 82, which are located above the second semiconductor unit 42 and penetrate downward through the second insulating layer 5, exposing the upper surface of the second semiconductor unit 42. The third through hole 83 is located above the driving circuit trace 72 and exposes the upper surface of the driving circuit trace 72.

[0069] A second transparent conductive layer 9 is disposed on the intermediate insulating layer 8;

[0070] A third metal layer 10 is disposed on the intermediate insulating layer 8. The third metal layer 10 includes a first source 101, a first drain 102, a second source 103, a second drain 104, and a metal unit 105. The first source 101 and the first drain 102 are respectively connected to the corresponding conductor region 43 through corresponding first vias 81. The second source 103 and the second drain 104 are respectively connected to the two ends of the second semiconductor unit 42 through corresponding second vias 82. The metal unit 105 is connected to the driving circuit trace 72 through a third via 93.

[0071] When the first transparent conductive layer 6 is a common electrode and the second transparent conductive layer 9 is a pixel electrode, the driving circuit trace 72 is laid on the first transparent conductive layer 6, and one end of the second drain 104 is also connected to one end of the second transparent conductive layer 9.

[0072] The film structure corresponding to the top gate 71 is the driving circuit area TFT 100, the film structure corresponding to the bottom gate 21 is the display area TFT 200, and the film structure corresponding to the driving circuit trace 72 is the metal line area 300.

[0073] In a preferred embodiment, the non-channel regions at both ends of the first semiconductor unit 41 are subjected to ion doping treatment to make the region conductive, forming a conductor region 43.

[0074] See Figure 2 As shown, in a preferred embodiment, when the first transparent conductive layer 6 is a pixel electrode and the second transparent conductive layer 9 is a common electrode, a fourth through hole 84 is also provided on the intermediate insulating layer 8. The fourth through hole 84 is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer 9 overlaps with the metal unit 105.

[0075] This invention also relates to a method for fabricating an oxide array substrate that can reduce parasitic capacitance effects, the method comprising the following steps:

[0076] Step 1: Form a first metal layer 2 on substrate 1 to fabricate the bottom gate 21 and related driving signal lines;

[0077] Step 2: Form a first insulating layer 3 on the first metal layer 2; the first insulating layer 3 in the display area serves as the bottom gate TFT gate insulating layer, and the first insulating layer 3 in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit 41.

[0078] Step 3: A semiconductor layer 4 is formed on the first insulating layer 3, and a first semiconductor unit 41 and a second semiconductor unit 42 are prepared. Then, the left and right ends of the first semiconductor unit 41 are conductiveized to form a conductive region 43. The present invention conducts conductive treatment on both ends of the semiconductor layer at the top gate TFT position, which can reduce the contact resistance of the source and drain contact regions.

[0079] Step 4: Form a second insulating layer 5 on the semiconductor layer 4 as the gate insulating layer of the top gate TFT;

[0080] Step 5: Form a first transparent conductive layer 6 on the second insulating layer 5.

[0081] Step 6: Form a second metal layer 7 on the second insulating layer 5, and fabricate the top gate 71 and the drive circuit trace 72, or other signal traces;

[0082] Step 7: Form an intermediate insulating layer 8 on the second metal layer 5;

[0083] Step 8: Form a second transparent conductive layer 9 on the intermediate insulating layer 8; then, prepare a first through hole 81, a second through hole 82 and a third through hole 83 on the intermediate insulating layer 8, and expose the upper surface of the conductor region 43 at both ends of the first semiconductor unit 41, the upper surface of the second semiconductor unit 42 and the upper surface of the driving circuit trace 72, respectively.

[0084] Step 9: A third metal layer 10 is formed on the intermediate insulating layer 8, and a first source 101, a first drain 102, a second source 103, a second drain 104, and a metal unit 105 are fabricated; wherein the first source 101 and the first drain 102 are respectively connected to the corresponding conductor region 43 through corresponding first vias 81; the second source 103 and the second drain 104 are respectively connected to the two ends of the second semiconductor unit 42 through corresponding second vias 82; the metal unit 105 is connected to the driving circuit trace 72 through a third via 83.

[0085] When the first transparent conductive layer 6 is a common electrode and the second transparent conductive layer 9 is a pixel electrode, the driving circuit trace 72 is laid on the first transparent conductive layer 6, and one end of the second drain 104 is also connected to one end of the second transparent conductive layer 9.

[0086] The film structure corresponding to the top gate 71 is the driving circuit area TFT 100, the film structure corresponding to the bottom gate 21 is the display area TFT 200, and the film structure corresponding to the driving circuit trace 72 is the metal line area 300.

[0087] See Figure 3-4 In a preferred embodiment, when the first transparent conductive layer 6 is a pixel electrode and the second transparent conductive layer 9 is a common electrode, during the preparation process in step 8, a fourth through hole 84 is also provided on the intermediate insulating layer 8. The fourth through hole 84 is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer 9 overlaps with the metal unit 105.

[0088] In a preferred embodiment, the first metal layer 2, the second metal layer 7, and the third metal layer 10 are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0089] In a preferred embodiment, the first insulating layer 3, the second insulating layer 5, and the intermediate insulating layer 8 are single-layer or multi-layer structures, and the materials are inorganic oxides or insulating compounds.

[0090] In a preferred embodiment, the first transparent conductive layer 6 and the second transparent conductive layer 9 are made of ITO.

[0091] In summary, this invention provides top-gate and bottom-gate TFT devices at corresponding positions in the driving circuit area and display area of ​​the array substrate, respectively. Therefore, this array substrate structure retains the low parasitic capacitance driving advantage of the top-gate structure and overcomes the disadvantage of the single function of the added light-shielding layer in the existing structure, thus improving the utilization of the thin film. By placing the first transparent conductive layer below the second metal layer, this invention can further simplify the film structure and has higher light transmittance, which can further reduce the manufacturing cost and is suitable for the low-cost development of high-resolution and high-refresh-rate display panels.

[0092] In addition, the present invention performs conductor treatment on both ends of the semiconductor layer at the top gate TFT position, which can reduce the contact resistance of the source and drain contact regions.

[0093] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An oxide array substrate capable of reducing parasitic capacitance effects, characterized in that: The oxide array substrate includes: a substrate, A first metal layer is disposed on the substrate, and the first metal layer includes a bottom gate; A first insulating layer is disposed on the first metal layer; A semiconductor layer is disposed on the first insulating layer. The semiconductor layer includes a first semiconductor unit and a second semiconductor unit. The two ends of the first semiconductor unit are respectively conductive to form conductive regions. The position of the second semiconductor unit corresponds to the position of the bottom gate. A second insulating layer is disposed on the semiconductor layer; A first transparent conductive layer is disposed on the second insulating layer; A second metal layer is disposed on the second insulating layer. The second metal layer includes a top gate and driving circuit traces. The top gate is located above the first semiconductor cell. An intermediate insulating layer is disposed on the second metal layer. The intermediate insulating layer has a first through-hole, a second through-hole, and a third through-hole. There are two first through-holes, which are located on both sides of the top gate and penetrate downward through the second insulating layer, exposing the upper surface of the conductor regions at both ends of the first semiconductor unit. There are two second through-holes, which are located above the second semiconductor unit and penetrate downward through the second insulating layer, exposing the upper surface of the second semiconductor unit. The third through-hole is located above the driving circuit trace and exposes the upper surface of the driving circuit trace. A second transparent conductive layer is disposed on the intermediate insulating layer; A third metal layer is disposed on the intermediate insulating layer. The third metal layer includes a first source, a first drain, a second source, a second drain, and a metal unit one. The first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias. The second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias. The metal unit one is connected to the driving circuit traces through a third via. When the first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode, the driving circuit traces are laid on the first transparent conductive layer, and one end of the second drain is also connected to one end of the second transparent conductive layer. The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

2. The oxide array substrate with reduced parasitic capacitance effect according to claim 1, characterized in that: The non-channel regions at both ends of the first semiconductor unit are subjected to ion doping treatment to make the region conductive, forming a conductive region.

3. An oxide array substrate with reduced parasitic capacitance effect according to claim 1, characterized in that: When the first transparent conductive layer is a pixel electrode and the second transparent conductive layer is a common electrode, a fourth through hole is also provided on the intermediate insulating layer. The fourth through hole is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer overlaps with the metal unit.

4. A method for fabricating an oxide array substrate that can reduce parasitic capacitance effect, characterized in that: The array substrate prepared by the method is an oxide array substrate with reduced parasitic capacitance effect as described in claim 1 or 2, and the method steps are as follows: Step 1: Form a first metal layer on the substrate to fabricate the bottom gate and related drive signal lines; Step 2: Form a first insulating layer on the first metal layer; the first insulating layer in the display area serves as the bottom gate TFT gate insulating layer, and the first insulating layer in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit; Step 3: Form a semiconductor layer on the first insulating layer and prepare the first semiconductor unit and the second semiconductor unit. Then, perform conductor treatment on the left and right ends of the first semiconductor unit to form a conductor region. Step 4: Form a second insulating layer on the semiconductor layer as the gate insulating layer of the top gate TFT; Step 5: Form a first transparent conductive layer on the second insulating layer. Step 6: Form a second metal layer on the second insulating layer, and fabricate the top gate and drive circuit traces, or other signal traces; Step 7: Form an intermediate insulating layer on the second metal layer; Step 8: Form a second transparent conductive layer on the intermediate insulating layer; then, prepare a first through-hole, a second through-hole, and a third through-hole on the intermediate insulating layer, exposing the upper surface of the conductor region at both ends of the first semiconductor unit, the upper surface of the second semiconductor unit, and the upper surface of the driving circuit trace, respectively. Step 9: Form a third metal layer on the intermediate insulating layer, and fabricate a first source, a first drain, a second source, a second drain, and a metal unit 1; wherein the first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias; the second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias; the metal unit 1 is connected to the driving circuit traces through a third via; When the first transparent conductive layer is a common electrode and the second transparent conductive layer is a pixel electrode, the driving circuit traces are laid on the first transparent conductive layer, and one end of the second drain is also connected to one end of the second transparent conductive layer. The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

5. The method for fabricating an oxide array substrate with reduced parasitic capacitance effect according to claim 4, characterized in that: When the first transparent conductive layer is a pixel electrode and the second transparent conductive layer is a common electrode, a fourth through hole is also provided on the intermediate insulating layer. The fourth through hole is located below the second drain electrode, and the second drain electrode is also connected to the first transparent conductive layer through the fourth through hole; one end of the second transparent conductive layer overlaps with the metal unit.

6. The method for fabricating an oxide array substrate with reduced parasitic capacitance effect according to claim 4, characterized in that: The first metal layer, the second metal layer, and the third metal layer are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

7. The method for fabricating an oxide array substrate with reduced parasitic capacitance effect according to claim 4, characterized in that: The first insulating layer, the second insulating layer, and the intermediate insulating layer are single-layer or multi-layer structures, and the materials are inorganic oxides or insulating compounds.

8. The method for fabricating an oxide array substrate with reduced parasitic capacitance effect according to claim 4, characterized in that: The first and second transparent conductive layers are made of ITO.

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