A double-sided double-junction silicon-based GaAs photodetector and its preparation method

Abstract

The present invention provides a double-sided double-junction silicon-based GaAs photodetector and a preparation method thereof. The photodetector includes a GaAs substrate, and on one side of the GaAs substrate, an Al x Ga 1‑x As stress release layer, a GaAs absorption layer, an Al y Ga 1‑y As contact layer and interdigital electrodes are epitaxially grown in sequence; on the other side of the GaAs substrate, an insulating layer and a Si thin film layer are epitaxially grown in sequence; a raised Si ridge waveguide is provided on the Si thin film layer, and a p+-doped Si region is formed at the top of the Si ridge waveguide, and p++-doped Si regions are formed on the surfaces of the Si thin film layers on both sides close to the Si ridge waveguide; an intrinsic i-Ge absorption layer and an n++-doped Ge layer are epitaxially grown on the p+-doped Si region in sequence. The photodetector heterogeneously integrates a silicon-based germanium PIN and a GaAs photodetector without interference; the photodetector has a wide band, high detection sensitivity, a small volume, and is widely applicable.

Description

Technical Field

[0001] The present invention relates to the technical field of photoelectric detectors, and in particular to a double-sided double-junction silicon-based GaAs photoelectric detector and a preparation method thereof. Background Art

[0002] Silicon-based photodetectors are devices that convert optical signals into electrical signals, and are also one of the core components in silicon-based photonics. Due to the limitations of the bandgap structure of silicon materials, effective light detection cannot be achieved in the communication band based on pure silicon materials. For example, the detection wavelength range of detectors made of pure silicon materials is concentrated in the 400-700nm band. In the near-infrared, mid-infrared and even far-infrared regions, the detection efficiency of silicon-based photodetectors gradually decreases. Therefore, photodetectors based on a single silicon material can no longer meet the needs of social development.

[0003] The existing technology improves the requirements of photodetectors for detection bands by using silicon-based photodetectors in combination with photodetectors that detect other bands. However, using multiple photodetectors together not only makes the connection between devices more complicated, but also causes the overall size of the device to be large, which is often inconvenient; and there will be mutual interference between different photodetectors, which will seriously affect the sensitivity and detection range of the photodetectors, resulting in the inability to realize multi-band detection of signals by the photodetectors and low sensitivity. Therefore, it is necessary to reduce the complexity of the combination of multiple photodetector devices and develop photodetectors with high integration, wide detection band range and higher efficiency. Summary of the invention

[0004] The purpose of the present invention is to solve the above technical problems and provide a double-sided double-junction silicon-based GaAs photodetector; another purpose of the present invention is to provide a method for preparing the double-sided double-junction silicon-based GaAs photodetector.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A double-sided double-junction silicon-based GaAs photodetector comprises a GaAs substrate, one side of which is epitaxially grown with Al x Ga 1-x As stress release layer, GaAs absorption layer, Al y Ga 1-yAs contact layer and interdigital electrodes; an insulating layer and a Si thin film layer are epitaxially grown in sequence on the other side of the GaAs substrate; a raised Si ridge waveguide is provided on the Si thin film layer, a p+ doped Si region is formed on the top of the Si ridge waveguide, and p++ doped Si regions are respectively formed on the surfaces of the Si thin film layer on both sides of the Si ridge waveguide; an intrinsic i-Ge absorption layer and an n++ doped Ge layer are epitaxially grown in sequence on the p+ doped Si region; a first electrode layer and a second electrode layer are sequentially formed on the surfaces of the p++ doped Si region and the n++ doped Ge layer, both of which include a ground electrode and a signal electrode; the inner electrode in the first electrode layer is connected to the p++ doped Si region, and the signal electrode is connected to the n++ doped Ge layer; the inner electrode and the signal electrode in the second electrode layer are respectively connected to the inner electrode and the signal electrode in the first electrode layer.

[0007] The present invention combines a silicon-based photodetector with a GaAs photodetector and realizes heterogeneous integration of a silicon-based germanium PIN photodetector on a GaAs substrate by combining wafer bonding and ion beam stripping technology; at the same time, a GaAs detector is epitaxially grown on the other side of the GaAs substrate, and the GaAs detector and the silicon-based germanium PIN photodetector are electrically isolated by an insulating layer; the detectable wavelength range of the photodetector is expanded to a 400-1100nm band, and each detector has no influence on each other. Compared with a single photodetector, the detection efficiency and detection sensitivity of the photodetector can be greatly improved, while the device volume is saved, and no interference occurs between the devices, and the applicable field is greatly expanded.

[0008] Furthermore, the Al x Ga 1-x The thickness of the As stress release layer is 0.01-20 μm, wherein the value range of x is 0<x<1.

[0009] Furthermore, the thickness of the GaAs absorption layer is 0.01-20 μm.

[0010] Furthermore, the Al y Ga 1-y The thickness of the As contact layer is 10-500 nm, wherein the value range of y is 0<y<1.

[0011] Furthermore, the thickness of the intrinsic i-Ge absorption layer is 0.01-10 μm, and the thickness of the n++ doped Ge layer is 10-500 nm.

[0012] The present invention also provides a method for preparing the above-mentioned double-sided double-junction silicon-based GaAs photoelectric detector, comprising the following steps:

[0013] S1. Epitaxial growth of Al on GaAs substratex Ga 1-x As stress release layer, GaAs absorption layer, Al y Ga 1-y As contact layer;

[0014] S2. Depositing an insulating layer on the other side of the GaAs substrate, fixing the ion-doped intrinsic Si substrate on the surface of the insulating layer, performing high-temperature annealing, peeling off part of the intrinsic Si substrate, and retaining an initial Si thin film layer on the insulating layer; etching the initial Si thin film layer to form a Si thin film layer and a raised Si ridge waveguide located on the top of the Si thin film layer;

[0015] S3. doping ions on the Si surface at the top of the Si ridge waveguide to form a p+ doped Si region; heavily doping the Si surface of the Si thin film layer on both sides of the Si ridge waveguide to form a p++ doped Si region; epitaxially growing an intrinsic i-Ge absorption layer and an n++ doped Ge layer above the Si ridge waveguide;

[0016] S4. In Al y Ga 1-y Growing interdigital electrodes on the As contact layer; growing ground electrodes on the p++-doped Si region, growing signal electrodes on the n++-doped Ge layer, and the ground electrodes and signal electrodes forming a first electrode layer; growing ground electrodes on the ground electrodes of the first electrode layer, and growing signal electrodes on the signal electrodes of the first electrode layer, and the newly grown ground electrodes and signal electrodes forming a second electrode layer.

[0017] Furthermore, the interdigital electrodes, signal electrodes and ground electrodes are formed by magnetron sputtering or thermal evaporation coating methods.

[0018] Furthermore, the insulating layer is a layer component of SiO2, Si3N4 or Al2O3 material.

[0019] Furthermore, the doping ions are doped by ion implantation.

[0020] Furthermore, the material of the interdigital electrodes in step S4 is selected from gold (Au), silver (Ag), copper (Cu), and aluminum (Al).

[0021] Furthermore, in step S1, the GaAs substrate is an n-type GaAs substrate, and the doping concentration of the n-type GaAs substrate is 1×10 17 / cm 3 ~1×10 20 / cm 3 .

[0022] Furthermore, the thickness of the GaAs substrate in step S1 is 400-700 μm.

[0023] Preferably, the epitaxial growth in step S1 is carried out by metal organic chemical vapor deposition (MOCVD).

[0024] Further, in step S1, y Ga 1-y As contact layer is p-type Al y Ga 1-y As contact layer, the p-type Al y Ga 1- y The doping concentration of the As contact layer is 1×10 17 / cm 3 ~1×10 20 / cm 3 .

[0025] Furthermore, in step S2, the doping ions are hydrogen ions and helium ions, and the implantation dose of the hydrogen ions is 1×10 15 / cm 2 ~1×10 19 / cm 2 , the injection energy is 1×10 -3 ~6×10 3 MeV, the helium ion implantation dose is 1×10 15 / cm 2 ~2×10 19 / cm 2 , the injection energy is 1×10 -3 ~6×10 3 MeV.

[0026] Furthermore, the thickness of the insulating layer in step S2 is 0.005-10 μm.

[0027] Furthermore, the method used for fixing the ion-doped intrinsic Si substrate on the surface of the insulating layer in step S2 is bonding or transfer printing.

[0028] Furthermore, before fixing the ion-doped intrinsic Si substrate on the surface of the insulating layer in step S2, the deposited surface needs to be planarized to reduce the surface roughness to less than 0.5 nm.

[0029] Furthermore, in step S2, the high temperature annealing is performed at a temperature of 400 to 900° C. and for a time of 2 to 24 hours.

[0030] Furthermore, the high temperature annealing in step S2 is performed under inert gas conditions.

[0031] Furthermore, the etching in step S2 is to spin-coat a layer of photoresist on the initial Si thin film layer, and then bake the photoresist at a temperature of 80 to 110° C. for 5 to 10 minutes. After the photoresist is baked, the photoresist is exposed to ultraviolet light with a mask, developed, and part of the Si thin film on the initial Si thin film layer is removed to form a Si ridge waveguide 8.

[0032] Furthermore, the initial Si thin film layer needs to be polished before the spin coating of the photoresist.

[0033] Furthermore, in step S2, a layer of photoresist is spin-coated on the top Si surface of the Si ridge waveguide and the Si surface of the Si thin film layer on both sides of the Si ridge waveguide, respectively, and then the photoresist is baked, and the photoresist at the Si ridge waveguide and the Si thin film layer on both sides of the Si ridge waveguide is ultraviolet exposed using a mask, and the surface photoresist is removed by development to expose the top Si surface of the Si ridge waveguide and the Si surface of the Si thin film layer.

[0034] Furthermore, the temperature of baking the photoresist is set to 80-110° C., and the baking time is 5-10 minutes.

[0035] Preferably, the doping ions in step S3 are implanted with boron ions, and the implantation dose is 1×10 14 / cm 2 ~1×10 16 / cm 2 , the injection energy is 5~800keV.

[0036] Furthermore, the heavy doping in step S3 is to implant boron ions with an implantation dose of 1×10 14 / cm 2 ~1×10 18 / cm 2 , the injection energy is 5~800keV.

[0037] Furthermore, the epitaxial growth in step S3 adopts a selective epitaxial growth technology or a low-temperature buffer layer technology.

[0038] Furthermore, the intrinsic i-Ge absorption layer in step S3 has a thickness of 0.01 to 10 μm.

[0039] Furthermore, the n++ doped Ge layer in step S3 has a doping concentration of 1×10 17 / cm 3 ~1×10 20 / cm 3 The doped ions are phosphorus ions, and the thickness of the epitaxial growth is 10 to 500 nm.

[0040] Preferably, the interdigital electrodes in step S4 are metal interdigital electrodes, and the interdigital electrodes include an interdigital electrode positive electrode and an interdigital electrode negative electrode.

[0041] Furthermore, in step S2, an insulating layer is deposited on the other surface of the GaAs substrate, and the ion-doped intrinsic Si substrate is fixed on the surface of the insulating layer by wafer bonding or transfer imprinting.

[0042] The beneficial effects of the present invention are as follows:

[0043] (1) The present invention integrates a silicon-based germanium PIN high-speed detector with a GaAs detector by using wafer bonding, ion implantation, epitaxial growth and other technologies to prepare a double-sided double-junction photoelectric detector. Compared with Si detectors and GaAs detectors, a single detector has the advantages of wide detection band, high integration, low material loss, omitting device layers, small size, flexible response, etc.; it can improve the working efficiency of the detector and expand its application field. The combination of each detector greatly reduces the resistivity of the device, and there is no mutual interference and influence, so as to achieve high conversion efficiency of the device.

[0044] (2) The preparation process of the present invention is simple and mature, and is suitable for industrial large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 The schematic diagram of the structure of each layer of epitaxial layer growth on a GaAs substrate is shown in the figure for preparing the photodetector of the present invention.

[0046] Figure 2 This is a schematic diagram of ion implantation into an intrinsic Si substrate for preparing the photodetector of the present invention.

[0047] Figure 3 It is a schematic diagram of the structure in which the intrinsic Si substrate and the GaAs photodetector are bonded together in the preparation of the photodetector of the present invention.

[0048] Figure 4 It is a schematic diagram of the structure formed after the intrinsic Si substrate is peeled off in the preparation of the photodetector of the present invention.

[0049] Figure 5 It is a schematic diagram of the structure of forming a Si ridge waveguide in the preparation of the photodetector of the present invention.

[0050] Figure 6 The schematic diagram of the structure of forming a p+ doped Si region and a p++ doped Si region in the preparation of the photodetector of the present invention.

[0051] Figure 7 It is a schematic diagram of the structure of a silicon-based germanium PIN detector formed in the preparation of the photodetector of the present invention.

[0052] Figure 8 Schematic diagram of the overall structure of the photoelectric detector of the present invention.

[0053] Fig. 9 It is a schematic diagram of the top interdigital electrode structure of the double-sided double-junction silicon-based GaAs photodetector of the present invention.

[0054] Fig.10 Schematic diagram of the Si / GaAs interface scanning electron microscope.

[0055] Fig.11 Schematic diagram of the test in which the light source observed under a microscope irradiates the detector through the optical fiber.

[0056] Fig.12 Schematic diagram of the device testing apparatus.

[0057] Fig.13 This is a picture of the packaged device.

[0058] The meanings of the labels in the figure are as follows: 1 is GaAs substrate; 2 is Al x Ga 1-x As stress release layer; 3 is GaAs absorption layer; 4 is Al y Ga 1-y As contact layer; 5 is the interdigital electrode; 51 is the positive electrode of the interdigital electrode; 52 is the negative electrode of the interdigital electrode; 6 is the insulating layer; 7 is the Si thin film layer; 71 is the p++ doped Si region; 8 is the Si ridge waveguide; 9 is the p+ doped Si region; 10 is the intrinsic i-Ge absorption layer; 11 is the n++ doped Ge layer; 12 is the first electrode layer; 13 is the second electrode layer; 14 is the ground electrode; 15 is the signal electrode; 16 is the intrinsic Si substrate; 17 is the initial Si thin film layer. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0060] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0061] Example 1

[0062] Reference Figure 8 and Fig. 9 A double-sided double-junction silicon-based GaAs photodetector comprises a GaAs substrate 1, on one side of which Al x Ga 1-x As stress release layer 2, GaAs absorption layer 3, Al y Ga 1-y As contact layer 4 and interdigital electrodes 5; an insulating layer 6 and a Si thin film layer 7 are epitaxially grown on the other side of the GaAs substrate 1 in sequence; a raised Si ridge waveguide 8 is provided on the Si thin film layer 7, a p+ doped Si region 9 is formed on the top of the Si ridge waveguide 8, and p++ doped Si regions 71 are respectively formed on the surface of the Si thin film layer 7 on both sides of the Si ridge waveguide 8; an intrinsic i-Ge absorption layer 10 and an n++ doped Ge layer 11 are epitaxially grown on the p+ doped Si region 9 in sequence; a first electrode layer 12 and a second electrode layer 13 are formed on the surfaces of the p++ doped Si region 71 and the n++ doped Ge layer 11 in sequence, and the first electrode layer 12 and the second electrode layer 13 both include a ground electrode 14 and a signal electrode 15; the ground electrode 14 in the first electrode layer 12 is connected to the p++ doped Si region 71, and the signal electrode 15 is connected to the n++ doped Ge layer 11; the ground electrode 14 and the signal electrode 15 in the second electrode layer 13 are respectively connected to the ground electrode 14 and the signal electrode 15 in the first electrode layer 12.

[0063] As an optional solution, the Al x Ga 1-x The thickness of the As stress release layer 2 is 0.01 to 20 μm, where the value of x is in the range of 0 < x < 1. In this embodiment, the thickness is 0.5 μm, and the value of x is 0.90. As an optional solution, the thickness of the GaAs absorption layer 3 is 0.01 to 20 μm, and in this embodiment, it is 2 μm. As an optional solution, the Al y Ga 1-yThe thickness of the As contact layer 4 is 10 to 500 nm, wherein the value range of y is 0<y<1, and the thickness in this embodiment is 300 nm, wherein the value of y is 0.15. As an optional solution, the thickness of the n++ doped Ge layer 11 is 10 to 500 nm, and the thickness in this embodiment is 300 nm. As an optional solution, the thickness of the GaAs substrate 1 is 400 to 700 μm, and the thickness in this embodiment is 500 μm. As an optional solution, the thickness of the insulating layer 6 is 0.005 to 10 μm, and the thickness in this embodiment is 2 μm. As an optional solution, the thickness of the intrinsic i-Ge absorption layer 10 is 0.01 to 10 μm, and the thickness in this embodiment is 5 μm. As an optional solution, the interdigital electrode 5 is a metal interdigital electrode, and the interdigital electrode 5 includes an interdigital electrode positive electrode 51 and an interdigital electrode negative electrode 52, and the material of the interdigital electrode 5 is selected from gold (Au), silver (Ag), copper (Cu), and aluminum (Al). In this embodiment, the material of the interdigital electrodes 5 is gold (Au) and the thickness is 1 μm.

[0064] The above-mentioned double-sided double-junction silicon-based GaAs photodetector is prepared by the following method, referring to Figure 1-7 , including the following steps:

[0065] S1. Epitaxial growth of Al on GaAs substrate 1 x Ga 1-x As stress release layer 2, GaAs absorption layer 3, Al y Ga 1-y As contact layer 4; As an optional solution, the GaAs substrate 1 is an n-type GaAs substrate, and the doping concentration of the n-type GaAs substrate is 1×10 17 / cm 3 ~1×10 20 / cm 3 As an optional solution, in step S1, y Ga 1-y As contact layer 4 is p-type Al y Ga 1-y As contact layer, the p-type Al y Ga 1-y The doping concentration of the As contact layer is 1×10 17 / cm 3 ~1×10 20 / cm 3 .

[0066] S2. Depositing an insulating layer 6 on the other side of the GaAs substrate 1, as an optional solution, the insulating layer 6 is a layer member of SiO2, Si3N4 or Al2O3 material; fixing the ion-doped intrinsic Si substrate 16 on the surface of the insulating layer 6, performing high-temperature annealing, peeling off part of the intrinsic Si substrate 16, and retaining an initial Si thin film layer 17 on the insulating layer 6; etching the initial Si thin film layer 17 to form a Si thin film layer 7 and a Si ridge waveguide 8 protruding on the top of the Si thin film layer 7;

[0067] As an optional solution, the doping ions are hydrogen ions and helium ions, and the hydrogen ion implantation dose is 1×10 15 / cm 2 ~1×10 19 / cm 2 , the injection energy is 1×10 -3 ~6×10 3 MeV, the helium ion implantation dose is 1×10 15 / cm 2 ~2×10 19 / cm 2 , the injection energy is 1×10 -3 ~6×10 3 MeV. As an optional scheme, the method used to fix the ion-doped intrinsic Si substrate 16 on the surface of the insulating layer 6 in step S2 is bonding or transfer imprinting. As an optional scheme, before fixing the ion-doped intrinsic Si substrate 16 on the surface of the insulating layer 6 in step S2, the deposited surface needs to be flattened to reduce its surface roughness to less than 0.5nm. As an optional scheme, the high-temperature annealing is carried out under inert gas conditions, and the high-temperature annealing has an annealing temperature of 400 to 900°C and an annealing time of 2 to 24h.

[0068] As an optional solution, the etching is to spin-coat a layer of photoresist on the initial Si thin film layer 17, and then bake the photoresist at a temperature of 80 to 110° C. for 5 to 10 minutes; after the photoresist is baked, the photoresist is exposed to ultraviolet light with a mask, developed, and part of the Si thin film on the initial Si thin film layer 17 is removed to form a Si ridge waveguide 8. As an optional solution, the initial Si thin film layer 17 needs to be polished before the spin-coating of the photoresist.

[0069] As an optional solution, the top Si surface of the Si ridge waveguide 8 and the Si surface of the Si thin film layer 7 are respectively coated with a layer of photoresist on the top of the Si ridge waveguide 8 and the Si thin film layer 7 on both sides of the Si ridge waveguide 8, and then the photoresist is baked, and the photoresist at the Si ridge waveguide 8 and the Si thin film layer 7 on both sides of the Si ridge waveguide 8 is ultraviolet-exposed using a mask, and the surface photoresist is removed by development to expose the top Si surface of the Si ridge waveguide 8 and the Si surface of the Si thin film layer 7. Preferably, the temperature of baking the photoresist is set to 80-110° C., and the baking time is 5-10 minutes.

[0070] S3. Doping ions on the Si surface at the top of the Si ridge waveguide 8 to form a p+ doped Si region 9; heavily doping the Si surface of the Si thin film layer 7 on both sides of the Si ridge waveguide 8 to form a p++ doped Si region 71; epitaxially growing an intrinsic i-Ge absorption layer 10 and an n++ doped Ge layer 11 on the Si ridge waveguide 8; as an optional solution, the n++ doped Ge layer 11 in step S3 has a doping concentration of 1×10 17 / cm 3 ~1×10 20 / cm 3 , the doped ions are phosphorus ions.

[0071] As an optional solution, the doping ions are implanted with boron ions, and the implantation dose is 1×10 14 / cm 2 ~1×10 16 / cm 2 The implantation energy is 5 to 800 keV. As an optional solution, the heavy doping is implantation of boron ions with an implantation dose of 1×10 14 / cm 2 ~1×10 18 / cm 2 , the injection energy is 5~800keV.

[0072] As an optional solution, the epitaxial growth in step S3 adopts a selective epitaxial growth technology or a low-temperature buffer layer technology.

[0073] S4. In Al y Ga 1-y The interdigitated electrodes 5 are grown on the As contact layer 4; the ground electrodes 14 are grown on the p++ doped Si region 71, and the signal electrodes 15 are grown on the n++ doped Ge layer 11, and the ground electrodes 14 and the signal electrodes 15 form the first electrode layer 12; the ground electrodes 14 are newly grown on the ground electrodes 14 of the first electrode layer 12, and the signal electrodes 15 are newly grown on the signal electrodes 15 of the first electrode layer 12, and the newly grown ground electrodes 14 and the signal electrodes 15 constitute the second electrode layer 13.

[0074] As an optional solution, the interdigital electrodes 5, the signal electrode 15 and the ground electrode 14 are formed by magnetron sputtering or thermal evaporation coating methods.

[0075] The specific preparation steps are as follows:

[0076] (1) Epitaxial growth of GaAs detectors. Figure 1 A GaAs substrate 1 is provided. The GaAs substrate 1 is an n-type GaAs substrate with a thickness of 500 μm. A 500 nm thick Al 0.90 Ga 0.10 As stress release layer 2, n-type doping concentration is 1×10 19 / cm 3 In the Al 0.90 Ga 0.10 A 2 μm thick GaAs absorption layer 3 is epitaxially grown on the As stress release layer 2, and an Al 0.15 Ga 0.85 As contact layer 4, Al 0.15 Ga 0.85 The thickness of the As contact layer 4 is 300 nm. 0.15 Ga 0.85 As contact layer, p-type doping concentration is 1×10 19 / cm 3 ;

[0077] (2) Ion implantation of Si substrate. Figure 2 , provide an intrinsic Si substrate 16, and perform ion implantation on the intrinsic Si substrate 16 ( Figure 2 The middle arrow indicates the ion implantation in the intrinsic Si substrate 16 at the dotted line), and the hydrogen ions (H + ) and helium ions (He + ), H + The implantation dose is 6×10 16 / cm 2 , the injection energy is 400keV, He + The implantation dose is 5×10 15 / cm 2 , the injection energy is 450keV;

[0078] (3) Integration of intrinsic Si substrate 16 and GaAs detector. Figure 3 , depositing a layer of insulating layer 6 of SiO2 material on the other side of the GaAs substrate 1, the thickness of the insulating layer 6 is 2 μm. After the deposition is completed, the deposited surface is planarized by CMP method to reduce the surface roughness to less than 0.5 nm. Then, the intrinsic Si substrate 16 after ion implantation is bonded to the surface of the insulating layer 6;

[0079] (4) Stripping of Si film. Figure 4 , the bonded wafer is placed in an annealing furnace for high temperature annealing, and argon protective gas is continuously introduced into the chamber during the annealing process. The annealing temperature is set to 600°C, and the annealing time is set to 4 hours. The Si film will peel off along the ion implantation depth, and an initial Si film layer 17 will remain on the insulating layer 6;

[0080] (5) Etching of Si ridge waveguide 8. Figure 5 First, a chemical mechanical polishing process is performed on the surface of the initial Si thin film layer 17 that has been peeled off to improve its surface smoothness. Then a layer of photoresist is spin-coated on the initial Si thin film layer 17, and then the photoresist is baked. The baking temperature is set to 80°C and the baking time is 5 minutes. After the photoresist is baked, the photoresist is exposed to ultraviolet light using a mask. After the exposure is completed, part of the photoresist is removed with a developer. After the development is completed, the surface of the Si layer is cleaned with a nitrogen gun. Then, part of the Si layer is etched away by photolithography, and finally a Si thin film layer 7 and a Si ridge waveguide 8 located on the Si thin film layer 7 are formed;

[0081] (6) Preparation of p+ doped Si region and p++ doped Si region. Figure 6 After the Si ridge waveguide 8 is etched, a layer of photoresist is spin-coated on the surface of the Si thin film layer 7 and the Si ridge waveguide 8 located on the Si thin film layer 7 again, and then the photoresist is baked. The baking temperature is set to 80°C and the baking time is 5 minutes. After the photoresist is baked, the photoresist at the Si ridge waveguide 8 is exposed to ultraviolet light using a mask. After the exposure is completed, the photoresist above the Si ridge waveguide 8 and part of the Si thin film layer 7 on both sides are removed with a developer to expose the Si ridge waveguide 8 and the Si surface of the Si thin film layer 7 on both sides. Then, ion implantation is performed on the Si ridge waveguide 8. The implanted ions are boron (B) ions to form a p+ doped Si region 9. The implantation dose of the B ions is 1×10 15 / cm 2 The implantation energy is 30 keV. The Si surface on both sides of the Si ridge waveguide 8 is heavily doped to form a p++ doped Si region 71. The implantation dose of boron ions is 1×10 16 / cm 2 , the injection energy is 30keV;

[0082] (7) Preparation of silicon-based germanium PIN detectors. Figure 7An intrinsic i-Ge absorption layer 10 is epitaxially grown on the p+ doped Si region 9 by using the selective epitaxial technology. The thickness of the intrinsic i-Ge absorption layer 10 is 5 μm. An n++ doped Ge layer 11 is further epitaxially grown on the intrinsic i-Ge absorption layer 10. The concentration of n-type doping is 1×10 18 / cm 3 , the doped ions are phosphorus (P) ions, and the thickness of the epitaxial growth is 300nm;

[0083] (8) Preparation of metal electrodes. After the upper and lower photodetectors are prepared, metal electrodes are prepared on the surface of the GaAs detector and the surface of the Si detector respectively. A forked electrode 5 is formed on the surface of the GaAs detector. The material of the electrode can be Au. The thickness of the electrode is 1 μm, and the duty cycle of the forked electrode 5 is 20%. A first metal electrode layer 12 and a second metal electrode layer 13 are formed on the surface of the Si detector respectively. Each metal electrode layer is composed of a ground electrode 14, a signal electrode 15 and a ground electrode 14. The part of each metal electrode layer except the electrode is an insulating layer of SiO2 material. After the metal electrode is prepared, a double-sided double-junction silicon-based GaAs photodetector is obtained.

[0084] Example 2 Fabrication of a double-sided double-junction silicon-based GaAs photodetector using transfer imprinting technology

[0085] A double-sided double-junction silicon-based GaAs photodetector with Al 0.90 Ga 0.10 The thickness of the As stress release layer is 1 μm, and other structures are the same as those in Example 1.

[0086] The preparation method of the above double-sided double-junction silicon-based GaAs photodetector is as follows:

[0087] (1) Same as Example 1, only Al 0.90 Ga 0.10 The thickness of the As stress release layer is 1 μm;

[0088] (2) The same as (5) in Example 1, except that etching away part of the Si layer by photolithography is changed to etching away part of the Si layer by dry etching;

[0089] (3) Same as (6) in Example 1;

[0090] (4) Same as (7) in Example 1;

[0091] (5) Preparation of Si thin film layer 7 and insulating layer 6. On the other side of the Si thin film layer 7, a Si3N4 insulating layer with a thickness of 5 nm is deposited on the Si thin film layer 7 by plasma enhanced chemical vapor deposition (PECVD);

[0092] (6) GaAs photodetectors are integrated onto Si substrates. The device structure of the GaAs photodetector is fabricated on the GaAs detector epitaxial wafer, and then a layer of photoresist is spin-coated on the surface of the GaAs photodetector device. These photoresists are connected to the substrate of the source material, and there is a certain gap at the edge to expose the buffer layer to the air. Then, the Al in the epitaxial layer is etched by a corresponding etchant (the etchant ratio is H2O:H3PO4:H2O2=9:1:1). 0.90 Ga 0.10 The As stress release layer is etched away, and the thickness of the stress release layer is 1μm. The device layer is fixed on the fixture by photoresist and lifted up. Then it is transferred and imprinted onto the corresponding Si3N4 insulating layer;

[0093] (7) The same as (8) in Example 1, a double-sided double-junction silicon-based GaAs photodetector is prepared.

[0094] Compared with the wafer bonding technology in Example 1 to achieve heterogeneous integration of GaAs photodetectors and silicon-based germanium PIN photodetectors, this technology does not make high use of III-V source materials and is not compatible with existing CMOS processes; the transfer imprinting technology in the method of this embodiment is a technology that selectively extracts a small part of the device from the source material and then imprints it onto a target substrate. The subsequent production of the device is all completed on the substrate material, which can effectively utilize the source material, and different devices can be transferred and imprinted from different source materials to the same target substrate, maximizing the utilization of the source material and the target substrate material.

[0095] Example 3

[0096] A double-sided double-junction silicon-based GaAs photodetector, which is different from the structure of the embodiment 1 with only Al x Ga 1-x The value of X in the As stress release layer 2 is different, which is Al 0.70 Ga 0.30 As stress release layer, other structures remain unchanged.

[0097] Preparation method only Al x Ga 1-x The material used for the As stress release layer 2 is different, while the other materials remain unchanged, and a double-sided double-junction silicon-based GaAs photodetector is prepared.

[0098] Example 4

[0099] A double-sided double-junction silicon-based GaAs photodetector, the structure of which is different from that of Example 1 only in the electrode material, the electrode material is Al, the electrode thickness is 2 μm, the interdigital electrode duty cycle is 30%, and other structures remain unchanged.

[0100] The preparation method only differs in the material used for the electrodes while other aspects remain unchanged, thereby obtaining a double-sided double-junction silicon-based GaAs photodetector.

[0101] Comparative Example 1

[0102] A GaAs detector containing the same electrodes was prepared according to the method of Example 1.

[0103] Comparative Example 2

[0104] A silicon-based germanium PIN detector containing the same electrodes is prepared according to the method of Example 1, but a Si substrate with a thickness of 400-700 μm is required.

[0105] Comparative Example 3

[0106] The change to the product structure is not the structure in claim 1, but a Si film is directly bonded to the other side of the GaAs substrate and the insulating layer is removed to obtain a photodetector structure.

[0107] Comparative Example 4

[0108] The change to the product structure is not the structure in claim 1, but replacing the interdigital metal electrodes on the surface of the GaAs photodetector with ordinary metal electrodes. The resulting photodetector.

[0109] Comparative Example 5

[0110] A detector with the same structure as Example 1 is prepared, except that the doping method is changed from ion implantation to thermal diffusion, which is different from the steps in claim 6, and a detector with the same structure is prepared.

[0111] Comparative Example 6

[0112] Referring to Comparative Example 5, the doping dose of B ions in step (6) was increased from 1×10 15 / cm 2 Modified to 1×10 14 / cm 2 , a detector with the same structure was prepared.

[0113] Experimental Example 1

[0114] 1. Experimental Methods

[0115] The Si / GaAs interface morphology of the silicon-based GaAs photodetector was characterized using a scanning electron microscope (SEM). The sensitivity and band width of the sample devices of Examples 1, 3 and 4 and Comparative Examples 1-4, as well as the sample devices connected in series in Comparative Example 1 and Comparative Example 2 were measured using visible light-infrared absorption spectra. The measurement method is as follows: The infrared detection performance of different samples was studied using a test device self-assembled from a Keithley 4200-SCS semiconductor parameter tester and a 980nm infrared light source. The dark current I of different devices was measured respectively. d and photocurrent I l The ratio of photocurrent to dark current can reflect the sensitivity of the device. The schematic diagram of the device test device is as follows: Fig.12 Then, a visible-infrared tunable supercontinuum laser source (with an output wavelength of 400-2400nm) is used to irradiate different devices, as shown in FIG. Fig.11 As shown, the light source observable under the microscope is irradiated onto the detector through the optical fiber, and the detectable band range of different devices is tested.

[0116] 2. Experimental results

[0117] (1) The Si / GaAs interface morphology of the silicon-based GaAs photodetector in Example 1 was characterized. The schematic diagram of the scanning electron microscope is shown in FIG. Fig.10 As shown, a uniform Si / GaAs interface can be seen. Actual device image of a silicon-based GaAs photodetector packaged Fig.13 shown.

[0118] (2) The sensitivity and bandwidth test results of the above-mentioned Examples 1-4 and Comparative Examples 1-6 are shown in Table 1.

[0119] The experimental results are analyzed as follows: From the test results of Examples 1, 2, 4 and Comparative Examples 1, 2, 3, 4, it can be seen that the device prepared in Example 2 has the best performance. Example 2 is mainly based on the transfer imprinting technology, which shows that the detector prepared by the transfer imprinting technology has better sensitivity and band detection range. This technology can realize the effective utilization of materials, and the interface of the prepared device is not damaged, which can effectively exert the performance of the device. Fig.10 Schematic diagram of scanning electron microscopy of the Si / GaAs interface in the device prepared by transfer imprinting technology in Example 2.

[0120] It can be seen from the test results of Examples 1 and 2 and Comparative Examples 5 and 6 that the device prepared in Example 2 has the best performance, so the method of Example 2 is the best preparation method of the present invention. The present invention proposes to combine the GaAs photodetector with the silicon-based germanium PIN photodetector. During the preparation process, it overcomes the problems of directly combining the two photodetectors, the lattice mismatch and thermal expansion coefficient mismatch between the GaAs substrate and the Si thin film material, and the mutual electrical interference between the two photodetectors, which in turn affects the low sensitivity and short and narrow wavelength of the detector.

[0121] Table 1 Sensitivity and bandwidth of Examples 1-4 and Comparative Examples 1-6

[0122] Serial number Sensitivity Wide band Example 1 <![CDATA[4.52×10 2 ]]> 500-1600nm Example 2 <![CDATA[4.81×10 2 ]]> 400-1800nm Example 4 <![CDATA[3.52×10 2 ]]> 600-1800nm Comparative Example 1 <![CDATA[2.93×10 2 ]]> 600-1500nm Comparative Example 2 <![CDATA[2.75×10 2 ]]> 700-1200nm Comparative Example 3 <![CDATA[2.51×10 2 ]]> 700-1100nm Comparative Example 4 <![CDATA[2.42×10 2 ]]> 700-1050nm Comparative Example 1 and Comparative Example 2 are connected in series <![CDATA[3.01×10 2 ]]> 600-1500nm Comparative Example 5 <![CDATA[3.12×10 2 ]]> 600-1100nm Comparative Example 6 <![CDATA[2.81×10 2 ]]> 700-1000nm

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the solution. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents based on the understanding of the present solution without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A double-sided double-junction silicon-based GaAs photodetector, characterized in that: It comprises a GaAs substrate (1), on one side of which Al is epitaxially grown in sequence. x Ga 1-x As stress release layer (2), GaAs absorption layer (3), Al y Ga 1-y As contact layer (4) and interdigital electrodes (5); An insulating layer (6) is epitaxially grown on the other side of the GaAs substrate (1), and a Si thin film layer (7) is bonded or transferred and embossed on the insulating layer (6); a raised Si ridge waveguide (8) is provided on the Si thin film layer (7), a p+ doped Si region (9) is formed on the top of the Si ridge waveguide (8), and p++ doped Si regions (71) are respectively formed on the surface of the Si thin film layer (7) on both sides close to the Si ridge waveguide (8); an intrinsic i-Ge absorption layer (10) and an n++ doped Ge layer (11) are epitaxially grown in sequence on the p+ doped Si region (9); a first electrode layer (12) and a second electrode layer (13) are sequentially formed on the surfaces of the p++ doped Si region (71) and the n++ doped Ge layer (11); The first electrode layer (12) and the second electrode layer (13) both comprise a ground electrode (14) and a signal electrode (15); the ground electrode (14) in the first electrode layer (12) is connected to the p++ doped Si region (71), and the signal electrode (15) is connected to the n++ doped Ge layer (11); the ground electrode (14) and the signal electrode (15) in the second electrode layer (13) are respectively connected to the ground electrode (14) and the signal electrode (15) in the first electrode layer (12); The thickness of the insulating layer (6) is 0.005-10 μm, and the insulating layer (6) is a layer component made of SiO2, Si3N4 or Al2O3 material; the Al x Ga 1-x The thickness of the As stress release layer (2) is 0.01-20 μm, wherein the value range of x is 0<x<1.

2. The double-sided double-junction silicon-based GaAs photodetector according to claim 1, characterized in that: The thickness of the GaAs absorption layer (3) is 0.01-20 μm.

3. The double-sided double-junction silicon-based GaAs photodetector according to claim 1, characterized in that: The Al y Ga 1-y The thickness of the As contact layer (4) is 10-500 nm, where the value range of y is 0<y<1.

4. The double-sided double-junction silicon-based GaAs photodetector according to claim 1, characterized in that: The thickness of the intrinsic i-Ge absorption layer (10) is 0.01-10 μm, and the thickness of the n++ doped Ge layer (11) is 10-500 nm.

5. The method for preparing the double-sided double-junction silicon-based GaAs photodetector according to any one of claims 1 to 4, characterized in that: The steps include: S1. Epitaxial growth of Al on GaAs substrate (1) x Ga 1-x As stress release layer (2), GaAs absorption layer (3), Al y Ga 1- y As contact layer (4); S2. depositing an insulating layer (6) on the other surface of the GaAs substrate (1), fixing an ion-doped intrinsic Si substrate (16) on the surface of the insulating layer (6), performing high-temperature annealing, peeling off a portion of the intrinsic Si substrate (16), and retaining an initial Si thin film layer (17) on the insulating layer (6); etching the initial Si thin film layer (17) to form a Si thin film layer (7) and a Si ridge waveguide (8) protruding from the top of the Si thin film layer (7); S3. doping ions on the Si surface at the top of the Si ridge waveguide (8) to form a p+ doped Si region (9); heavily doping the Si surface of the Si thin film layer (7) on both sides of the Si ridge waveguide (8) to form a p++ doped Si region (71); epitaxially growing an intrinsic i-Ge absorption layer (10) and an n++ doped Ge layer (11) above the Si ridge waveguide (8); S4. In Al y Ga 1-y An interdigitated electrode (5) is grown on the As contact layer (4); a ground electrode (14) is grown on the p++ doped Si region (71), and a signal electrode (15) is grown on the n++ doped Ge layer (11); each ground electrode (14) and the signal electrode (15) form a first electrode layer (12); and a ground electrode (14) is grown on the ground electrode (14) of the first electrode layer (12); and a signal electrode (15) is grown on the signal electrode (15) of the first electrode layer (12); and the newly grown ground electrode (14) and the signal electrode (15) form a second electrode layer (13).

6. The preparation method according to claim 5, characterized in that: The interdigital electrodes (5), the signal electrode (15) and the ground electrode (14) are produced by magnetron sputtering or thermal evaporation coating methods.

7. The preparation method according to claim 5, characterized in that: The insulating layer (6) is a layer component made of SiO2, Si3N4 or Al2O3 material.

8. The preparation method according to claim 5, wherein the doping ions are doped by ion implantation.

9. The detector preparation method according to claim 5, characterized in that: In step S2, the ion-doped intrinsic Si substrate (16) is fixed on the surface of the insulating layer (6) by wafer bonding or transfer imprinting.

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