A Single-Clock High-Speed ​​Half-Band Interpolator Based on Overlapping Pipeline

Abstract

The present invention discloses a single-clock high-speed half-band interpolator based on overlapping pipeline, which includes a polyphase structure filter and an overlapping pipeline module. The overlapping pipeline module is passed between two adjacent polyphase structure filters to output multi-channel high-multiple interpolation data; the overlapping pipeline module includes a shift register, and the current polyphase structure filter outputs two n The signal is input to the initial bit array of the shift register connected to the output end of the current polyphase structure filter. The initial bit array is used as the length to convert 2 n The signal slides on the sorted bits until it reaches the last bit, and the shift register outputs the current 2 n The signal corresponds to 2 n times interpolated data; the 2 n The interpolated data is input to the next polyphase structure filter or through 2 n The half-band interpolator does not need to increase the clock frequency step by step in a multi-channel high-multiple interpolation system, which greatly reduces the chip area and power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of interpolators, and in particular to a single-clock high-speed half-band interpolator based on overlapping pipelining. Background Art

[0002] Multi-rate signal processing is a branch of digital signal processing. Taking double interpolation as an example, its basic structure is as follows Figure 5 As shown in the figure, after upsampling, the interpolation filter is used to achieve interpolation. In this structure, the interpolation filter needs to work under a high-frequency clock. If multi-level interpolation is required, the clock frequency will be doubled each time it passes through the upsampling module, and there are strict requirements on the frequency deviation and jitter of these multiplied clocks, especially in the chip process. It poses a severe challenge to the layout and routing of the back-end design.

[0003] Figure 6 It is a multi-phase structure filter with two-fold interpolation. This structure can post-position the upsampling module, double the clock frequency in the last stage, and make the interpolation filter work under the base frequency clock. However, when implementing interpolation with a higher multiple, due to the need for multi-stage cascading, it is still inevitable to need an upsampling module in the middle, and the clock rate will still increase. And when the filter order is high, there is a problem of initial phase inconsistency between different branches. In the multi-stage interpolation process, there is a demand to post-position the upsampling module to the last stage and keep the clock frequency of the intermediate stage consistent, but the industry does not have a good solution. Summary of the invention

[0004] Based on the technical problems existing in the background technology, the present invention proposes a single-clock high-speed half-band interpolator based on overlapping pipelines, which does not need to increase the clock frequency step by step in a multi-channel high-multiple interpolation system, thereby greatly reducing the chip area and power consumption.

[0005] The present invention proposes a single-clock high-rate half-band interpolator based on overlapping pipelining, which includes a polyphase structure filter and an overlapping pipelining module. The overlapping pipelining module is passed between two adjacent polyphase structure filters to output multi-channel high-multiple interpolation data.

[0006] The overlapping pipeline module includes a shift register, the number of bits of the shift register is arranged in sequence, and the current polyphase structure filter outputs 2 n The signal is input to the initial bit array of the shift register connected to the output end of the current polyphase structure filter. The initial bit array is used as the length to convert 2 n The signal slides on the sorted bits until it reaches the last bit, and the shift register outputs the current 2 n The signal corresponds to 2 n times interpolated data; the 2 n The interpolated data is input to the next polyphase structure filter or through 2 nThe number of bits in the initial bit array is the same as 2 n The signals correspond in sequence, and n represents the number of interpolation levels.

[0007] Furthermore, currently 2 n When a signal slides on the bits of the shift register, the data bits that slide over will be used for the next 2 n A signal slide.

[0008] Furthermore, the selection of the number of bits of the shift register in each overlapping pipeline module is independent of each other.

[0009] Further, when n=4, four-stage interpolation is performed, and the four-stage half-band interpolator specifically includes a polyphase structure filter HB1, a first overlapping pipeline module, a polyphase structure filter HB2, a second overlapping pipeline module, a polyphase structure filter HB3, a third overlapping pipeline module, and a polyphase structure filter HB4, two polyphase structure filters HB2 are arranged in parallel, four polyphase structure filters HB3 are arranged in parallel, and eight polyphase structure filters HB4 are arranged in parallel;

[0010] The input end of the first overlapping pipeline module is connected to the output end of the multi-phase structure filter HB1, and the output end is respectively connected to the input ends of two multi-phase structure filters HB2; the input end of the second overlapping pipeline module is connected to the output ends of the two multi-phase structure filters HB2, and the output end is connected to the input end of four multi-phase structure filters HB3; the input end of the third overlapping pipeline module is connected to the output ends of the four multi-phase structure filters HB3, and the output end is connected to eight multi-phase structure filters HB4; the eight multi-phase structure filters HB4 output sixteen-fold interpolated data by sixteen-fold clock upsampling.

[0011] Further, the first overlapping pipeline module uses a 12-bit register, the number of bits is r0, r1, ···, r10, r11 respectively, and the two signals output by the polyphase structure filter HB1 first enter r0, r1. After the storage is completed, the two signals slide from the current r0, r1 bits to r2, r3 bits, and the two signals slide in sequence until they slide to r10, r11 bits, and then the first overlapping pipeline module inputs the data to the polyphase structure filter HB2 to obtain two-stage interpolation data;

[0012] The second overlapping pipeline module uses an 8-bit register, the bits are r0, r1, ···, r7, r8 respectively. The four-way signal output by the polyphase structure filter HB2 first enters r0, r1, r2, r3. After the storage is completed, the four-way signal slides from the current r0, r1, r2, r3 bits to r4, r5, r6, r7 bits. Then, the second overlapping pipeline module inputs the data to the polyphase structure filter HB3 to obtain three-level interpolation data;

[0013] The third overlapping pipeline module uses a 16-bit register, with the bit numbers r0, r1, ···, r14, r15 respectively. The eight signals output by the multi-phase structure filter HB3 first enter r0, r1, r2, r3, r4, r5, r6, r7. After the storage is completed, the eight signals slide from the current r0, r1, r2, r3, r4, r5, r6, r7 bit numbers to r8, r9, r10, r11, r12, r13, r14, r15 bit numbers, and then the third overlapping pipeline module inputs the data into the multi-phase structure filter HB4 to obtain four-level interpolation data.

[0014] The advantages of the single-clock high-rate half-band interpolator based on overlapping pipelining provided by the present invention are: the single-clock high-rate half-band interpolator based on overlapping pipelining provided in the structure of the present invention has an exponential decrease in the number of half-band filters in a high-rate high-multiple interpolation system, which greatly reduces the chip area and power consumption. The half-band interpolator that realizes integer multiple interpolation at low cost and low power consumption based on the setting of the present application is conducive to chipization and large-scale integration, especially in the application of quantum bit measurement and control chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of the present invention;

[0016] Figure 2 is a schematic diagram of the working principle of the first overlapping water flow module;

[0017] Figure 3 is a schematic diagram of the working principle of the second overlapping pipeline module;

[0018] Figure 4 is a schematic diagram of the working principle of the third overlapping pipeline module;

[0019] Figure 5 It is a schematic diagram of the traditional classical interpolation scheme;

[0020] Figure 6 Schematic diagram of a traditional double interpolation polyphase structure filter. DETAILED DESCRIPTION

[0021] Below, the technical solution of the present invention is described in detail through specific embodiments. Many specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific implementation disclosed below.

[0022] like Figures 1 to 6As shown, the present invention proposes a single-clock high-rate half-band interpolator based on overlapping pipelining, which includes a multi-phase structure filter and an overlapping pipelining module. The overlapping pipelining module is passed between two adjacent multi-phase structure filters to output multi-channel high-multiple interpolation data;

[0023] The overlapping pipeline module includes a shift register, the number of bits of the shift register is arranged in sequence, and the current polyphase structure filter outputs 2 n The signal is input to the initial bit array of the shift register connected to the output end of the current polyphase structure filter. The initial bit array is used as the length to convert 2 n The signal slides on the sorted bits until it reaches the last bit, and the shift register outputs the current 2 n The signal corresponds to 2 n times interpolated data; the 2 n The interpolated data is input to the next polyphase structure filter or through 2 n The number of bits in the initial bit array is the same as 2 n The signals correspond in sequence, and n represents the number of interpolation levels.

[0024] In this embodiment, in the multi-stage cascade, there is no need to set up sampling to perform data sampling and transmission between stages, so in the multi-channel high-multiple interpolation system, there is no need to increase the clock frequency step by step, and the entire interpolator only needs one base frequency clock, which greatly reduces the complexity of chip implementation;

[0025] In addition, in the traditional multi-stage cascade, multiple registers are set corresponding to the increase in clock frequency. In this embodiment, since the clock frequency does not need to be increased step by step during the multi-stage cascade process, the number of filters used is synchronously reduced. That is, the number of half-band filters in the high-speed and high-multiple interpolation system decreases exponentially step by step, which greatly reduces the chip area and power consumption. The low-cost, low-power half-band interpolator that realizes integer multiple interpolation based on the setting of this application is conducive to chipization and large-scale integration, especially in the application of quantum bit measurement and control chips.

[0026] This embodiment can realize multi-stage cascade interpolation to obtain 2, 4, 8, 16 times interpolation data, especially for the output of multi-channel high-multiple interpolation data. The number of bits of the shift register in each overlapping pipeline module is independent of each other, and each shift register can process different signals at the same time according to the number of bits set, that is, the current 2 n When a signal slides on the bits of the shift register, the data bits that slide over will be used for the next 2 n A signal slide.

[0027] The following uses four-stage cascade (n=4) to implement 2, 4, 8, and 16 times interpolation respectively as an example.

[0028] The four-stage half-band interpolator specifically includes a polyphase structure filter HB1, a first overlapping pipeline module, a polyphase structure filter HB2, a second overlapping pipeline module, a polyphase structure filter HB3, a third overlapping pipeline module, and a polyphase structure filter HB4. Two polyphase structure filters HB2 are arranged in parallel, four polyphase structure filters HB3 are arranged in parallel, and eight polyphase structure filters HB4 are arranged in parallel. The output of each polyphase structure filter passes through an overlapping pipeline module (ITW) before being sent to the next stage.

[0029] The input end of the first overlapping pipelining module (ITW1) is connected to the output end of the polyphase structure filter HB1, and the output end is respectively connected to the input ends of two polyphase structure filters HB2; the input end of the second overlapping pipelining module (ITW2) is connected to the output ends of the two polyphase structure filters HB2, and the output end is connected to the input ends of four polyphase structure filters HB3; the input end of the third overlapping pipelining module (ITW3) is connected to the output ends of the four polyphase structure filters HB3, and the output end is connected to eight polyphase structure filters HB4; the eight polyphase structure filters HB4 output sixteen-fold interpolated data by sixteen-fold clock upsampling.

[0030] according to Figure 1 and 2 As shown, the first overlapping pipeline module uses a 12-bit register, the bits are r0, r1, ···, r10, r11 respectively, the two signals din0 and din1 output by the polyphase structure filter HB1 first enter r0, r1 (in cycle 0, din0 enters r1, din1 enters r0), after the storage is completed, in cycle 1, the current two signals slide from the current r0, r1 bits to r2, r3 bits (in cycle 1, din0 enters r3, din1 enters r2), the current two signals slide in turn, in cycle 5, until they slide to r10, r11 bits (in cycle 5, din0 enters r11, din1 enters r10), and then the shift storage of the current two signals din0 and din1 is completed, and then the first overlapping pipeline module inputs the data into the polyphase structure filter HB2 to obtain two-stage interpolation data;

[0031] The current two-way signal din0 and din1 slides from the current r0, r1 bit to the r2, r3 bit. At this time, the r0, r1 bit will be vacated, and the next two-way signal will enter the r0, r1 bit for the next two-way signal shift register. Another way to record it is: after the current two-way signal enters the r0, r1 bit to complete the shift register, the next two-way signal will enter the r0, r1 bit, and the current two-way signal din0 and din1 will be "squeezed" to the next r2, r3 bit for the next cycle of shift register.

[0032] Similarly:

[0033] like Figure 1 and 3 As shown, the second overlapping pipeline module (ITW2) uses an 8-bit register, the bits of which are r0, r1, ···, r7, r8 respectively. The four signals (din0, din1, din2 and din3) output by the polyphase structure filter HB2 first enter r0, r1, r2, r3 (in cycle 0, din0 enters r3, din1 enters r2, din2 enters r1 and din3 enters r0). After the registration is completed, the four signals slide from the current r0, r1, r2, r3 bits to r4, r5, r6, r7 bits (in cycle 1, din0 enters r7, din1 enters r6, din2 enters r5 and din3 enters r4). Then, the second overlapping pipeline module inputs the data into the polyphase structure filter HB3 to obtain three-level interpolation data;

[0034] The current four-way signal (din0, din1, din2 and din3) slides from the current r0, r1, r2, r3 bits to the r4, r5, r6, r7 bits. At this time, the r0, r1, r2, r3 bits will be vacated, and the next four-way signal will enter the r0, r1, r2, r3 bits for the next four-way signal shift register. Another way to record it is: after the current four-way signal enters the r0, r1, r2, r3 bits to complete the shift register, the next four-way signal will enter the r0, r1, r2, r3 bits, and the current four-way signal (din0, din1, din2 and din3) is "squeezed" to the next r4, r5, r6, r7 bits for the next cycle of shift register.

[0035] like Figure 1 and 4As shown, the third overlapping pipeline module (ITW3) uses a 16-bit register, the bits are r0, r1, ···, r14, r15 respectively, and the eight signals (din0, din1, din2, din3, din4, din5, din6 and din7) output by the polyphase structure filter HB3 first enter the bits r0, r1, r2, r3, r4, r5, r6, r7 (in cycle 0, din0 enters r7, din1 enters r6, din2 enters r5, din3 enters r4, din4 enters r3, din5 enters r2, din6 enters r1 and din7 enter r0), after the storage is completed, the eight-way signal slides from the current r0, r1, r2, r3, r4, r5, r6, r7 bit positions to r8, r9, r10, r11, r12, r13, r14, r15 bit positions (in cycle 1, din0 enters r15, din1 enters r14, din2 enters r13, din3 enters r12, din4 enters r11, din5 enters r10, din6 enters r9 and din7 enters r8), and then the third overlapping pipeline module inputs the data to the multi-phase structure filter HB4 to obtain four-level interpolation data.

[0036] The current eight signals (din0, din1, din2, din3, din4, din5, din6 and din7) slide from the current r0, r1, r2, r3, r4, r5, r6, r7 bits to r8, r9, r10, r11, r12, r13, r14, r15 bits. At this time, the r0, r1, r2, r3, r4, r5, r6, r7 bits will be vacated, and the next eight signals will enter the r0, r1, r2, r3, r4, r5, r6, r7 bits for shift registration of the next eight signals. To put it another way, after the current eight signals enter the r0, r1, r2, r3, r4, r5, r6, r7 bits and complete the shift register, the next eight signals will enter the r0, r1, r2, r3, r4, r5, r6, r7 bits and the current eight signals (din0, din1, din2, din3, din4, din5, din6 and din7) are "squeezed" to the next r8, r9, r10, r11, r12, r13, r14, r15 bits for the next cycle of shift register.

[0037] This embodiment only adds an overlapping pipeline module without changing the existing multi-phase structure filter. During multi-stage high-multiple interpolation, there is no need to increase the clock frequency step by step, and only one baseband clock is required. At the same time, the number of half-band filters in the high-speed high-multiple interpolation system decreases exponentially step by step, which greatly reduces the area, power consumption and implementation difficulty of the chip made of the interpolator.

[0038] The interposer of this embodiment is compared with the traditional architecture (based on TSMC28 process), corresponding to Table 1

[0039] Table 1 Parameter comparison between the architecture of this embodiment and the traditional architecture

[0040]

[0041] As shown in the above table, when the structure and performance of this embodiment are consistent with the traditional architecture, the interposer area of ​​this embodiment is 1 / 8 of that of the traditional architecture, the power consumption is 1 / 10 of that of the traditional architecture, and the number of clocks is 1 / 5 of that of the traditional architecture, making chipization and large-scale integration possible.

[0042] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A single-clock high-rate half-band interpolator based on overlapping pipelining, characterized in that: It includes a multi-phase structure filter and an overlapping pipeline module, wherein the overlapping pipeline module is passed between two adjacent stages of the multi-phase structure filters to output multi-channel high-multiple interpolation data; The overlapping pipeline module includes a shift register, the number of bits of the shift register is arranged in sequence, and the current polyphase structure filter outputs The signal is input to the initial bit array of the shift register connected to the output end of the current polyphase structure filter, with the initial bit array as the length. The signal slides on the sorted bits until it reaches the last bit, and the shift register outputs the current The signal corresponds to times interpolated data; The interpolated data is input to the next polyphase structure filter or through The number of bits in the initial bit array is equal to The signals correspond in sequence, represents the interpolation series; when When performing four-stage interpolation, the four-stage half-band interpolator specifically includes a polyphase structure filter HB1, a first overlapping pipeline module, a polyphase structure filter HB2, a second overlapping pipeline module, a polyphase structure filter HB3, a third overlapping pipeline module, and a polyphase structure filter HB4, two polyphase structure filters HB2 are arranged in parallel, four polyphase structure filters HB3 are arranged in parallel, and eight polyphase structure filters HB4 are arranged in parallel; The input end of the first overlapping pipeline module is connected to the output end of the multi-phase structure filter HB1, and the output end is respectively connected to the input ends of two multi-phase structure filters HB2; the input end of the second overlapping pipeline module is connected to the output ends of the two multi-phase structure filters HB2, and the output end is connected to the input end of four multi-phase structure filters HB3; the input end of the third overlapping pipeline module is connected to the output ends of the four multi-phase structure filters HB3, and the output end is connected to eight multi-phase structure filters HB4; the eight multi-phase structure filters HB4 output sixteen-fold interpolated data by sixteen-fold clock upsampling.

2. The single-clock high-rate half-band interpolator based on overlapped pipelining according to claim 1, characterized in that: current When a signal slides on the number of bits in the shift register, the number of data bits that slide will be used for the next A signal slide.

3. The single-clock high-rate half-band interpolator based on overlapped pipelining according to claim 1, characterized in that: The number of bits of the shift register in each overlapping pipeline module is selected independently.

4. The single-clock high-rate half-band interpolator based on overlapped pipelining according to claim 1, characterized in that: The first overlapping pipeline module uses a 12-bit register, the bits are r0, r1, ···, r10, r11 respectively, and the two signals output by the polyphase structure filter HB1 first enter r0, r1. After the storage is completed, the two signals slide from the current r0, r1 bits to r2, r3 bits, and the two signals slide in turn until they slide to r10, r11 bits. Then, the first overlapping pipeline module inputs the data to the polyphase structure filter HB2 to obtain two-stage interpolation data; The second overlapping pipeline module uses an 8-bit register, the number of which is r0, r1, ···, r7, r8 respectively. The four-way signal output by the polyphase structure filter HB2 first enters r0, r1, r2, r3. After the storage is completed, the four-way signal slides from the current r0, r1, r2, r3 to the r4, r5, r6, r7. Then, the second overlapping pipeline module inputs the data into the polyphase structure filter HB3 to obtain three-level interpolation data; The third overlapping pipeline module uses a 16-bit register, with the bit numbers r0, r1, ···, r14, r15 respectively. The eight-way signals output by the polyphase structure filter HB3 first enter r0, r1, r2, r3, r4, r5, r6, r7. After the storage is completed, the eight-way signals slide from the current r0, r1, r2, r3, r4, r5, r6, r7 bit numbers to r8, r9, r10, r11, r12, r13, r14, r15 bit numbers, and then the third overlapping pipeline module inputs the data into the polyphase structure filter HB4 to obtain four-level interpolation data.

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