A low-dropout linear voltage regulator with enhanced transient response and ripple rejection ratio

Abstract

The application relates to a low-dropout linear voltage regulator with enhanced transient response and ripple rejection ratio, which is based on an error amplifier circuit, a summing stage circuit, a super source follower circuit and a current feedback loop circuit, and is built through a design scheme to realize three signal feedback loops of a voltage feedback main loop, a feedback enhancement loop and a current feedback loop, can have fast transient response and high ripple rejection ratio in application, can adaptively adjust the current size of a buffer stage according to the size of a load current, avoids waste of power consumption, reduces cost and design complexity, and reduces the size of power consumption on the basis of significantly improving transient response, and realizes fast transient response and ripple rejection ratio.

Description

TECHNICAL FIELD

[0001] The application relates to a low-dropout linear regulator with enhanced transient response and ripple rejection ratio, and belongs to the technical field of linear regulators. BACKGROUND

[0002] A low-dropout linear regulator (LDO) is an integrated circuit used for power management, and its main purpose is to provide a stable output voltage for a system on chip (SoC) when the input voltage is higher than the output voltage. This type of regulator is widely used in many electronic devices, such as mobile devices, communication devices, and various portable electronic products. These application scenarios often require very stable power supply voltage to power the chips therein, and the power supply generated by a general transformer usually has a lot of noise and uncertainty. If this unstable power supply is directly used to power the chip, it may cause abnormal output of the chip and contain a lot of noise, which is not conducive to the high-precision working state of the current precision chip. Therefore, it is necessary to use a low-dropout linear regulator to power the system on chip, and thus the research and design of the low-dropout linear regulator also have high research value.

[0003] The working ability of a low-dropout linear regulator is often reflected in its transient response, power supply ripple rejection ratio, power consumption, and area. The switching and changing of the working state of the powered circuit will cause the load current of the low-dropout linear regulator to change, thereby causing the output of the low-dropout linear regulator to produce overshoot and undershoot voltage. Good transient response means low overshoot and undershoot voltage. At the same time, the power supply for the low-dropout linear regulator often has noise and ripple, so the low-dropout linear regulator needs to have the ability to suppress the ripple to prevent the noise from being transmitted to the next stage of the load circuit. In addition, the power consumption of the low-dropout linear regulator is also worth attention, and a large power consumption can be exchanged for good transient response and ripple rejection ratio, but excessive power consumption obviously does not conform to the development direction of energy saving and low power consumption. At present, many low-dropout regulators usually rely on connecting large load capacitors through PCB pins to enhance the transient performance. However, this method not only reduces the circuit integration and increases the complexity of circuit integration, but also needs to design a load capacitor for each low-dropout regulator. In addition, due to the inclusion of a large number of capacitors in the output stage, the bandwidth of the circuit has undergone a significant reduction. Therefore, in order to reduce the dependence on external large load capacitors, it is necessary to develop new circuit structures to improve the transient response of the low-dropout regulator.

[0004] In the past, P-type transistors were often used as power tubes for low-dropout linear regulators because of their relatively simple structure. However, in recent years, a large number of research and design work consistently shows that low-dropout regulators based on N-type transistors are superior to their P-type transistor counterparts in performance. However, compared with P-type transistors, the design of N-type transistor low-dropout linear regulators faces some challenges. For example, in an N-type transistor low-dropout linear regulator, the gate voltage passing through the buffer needs to be higher than the output voltage of the low-dropout linear regulator by one gate-source voltage. In addition, because the source voltage is the output voltage rather than ground, the threshold voltage of the N-type transistor also increases accordingly. These factors undoubtedly impose significant restrictions on the amplitude of the output voltage. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a low-dropout linear regulator that can enhance transient response and ripple rejection ratio, has fast transient response and high ripple rejection ratio, can adaptively control current to reduce power consumption, and has no load capacitance, thereby reducing cost and design complexity.

[0006] The present application adopts the following technical solutions to solve the above technical problems: The present application designs a low-dropout linear regulator that can enhance transient response and ripple rejection ratio, comprising an NMOS transistor Mp, and an error amplifier circuit and a super source follower circuit, wherein the power supply end, the ground end, and the bias signal end of the error amplifier circuit and the super source follower circuit are respectively connected to a power supply V BAT , ground GND, and bias signal Idc; the drain of the NMOS transistor Mp constitutes the input end of the low-dropout linear regulator for receiving a signal to be stabilized; the output end of the error amplifier circuit is connected to the input end of the super source follower circuit, and the output end of the super source follower circuit is connected to the gate of the NMOS transistor Mp; the source of the NMOS transistor Mp constitutes the output end of the low-dropout linear regulator, and the source of the NMOS transistor Mp is connected to the feedback end of the error amplifier circuit.

[0007] As a preferred technical solution of the present application: further comprising a summing stage circuit, the power supply end and the ground end of the summing stage circuit are respectively connected to a power supply V BAT , ground GND, the output end of the error amplifier circuit is connected to the input end of the summing stage circuit, the output end of the summing stage circuit is connected to the input end of the super source follower circuit, and the source of the NMOS transistor Mp is connected to the feedback end of the summing stage circuit.

[0008] As a preferred technical scheme of the present application: the summing stage circuit comprises NMOS tube MN5, NMOS tube MN6 and NMOS tube MN7, wherein the gate of the NMOS tube MN5 constitutes the input end of the summing stage circuit, and the drain of the NMOS tube MN5 constitutes the power supply end of the summing stage circuit; the source of the NMOS tube MN5 is connected with the drain of the NMOS tube MN6, and the connection end constitutes the output end of the summing stage circuit; the gate of the NMOS tube MN6 is externally connected with a control signal Vbn2; the source of the NMOS tube MN6 is connected with the drain of the NMOS tube MN7, the gate of the NMOS tube MN7 constitutes the feedback end of the summing stage circuit, and the source of the NMOS tube MN7 constitutes the ground end of the summing stage circuit.

[0009] As a preferred technical scheme of the present application: the current feedback loop circuit further comprises a power supply end and a ground end, wherein the power supply end and the ground end are connected with a power supply V BAT and a ground GND respectively, the output end of the super source follower circuit is connected with the input end of the current feedback loop circuit, the output end of the current feedback loop circuit is connected with the gate of the NMOS tube Mp, and the source of the NMOS tube Mp is connected with the feedback end of the current feedback loop circuit.

[0010] As a preferred technical scheme of the present application: the current feedback loop circuit comprises PMOS tube MP10, PMOS tube MP11, NMOS tube MN10, NMOS tube MN11, NMOS tube MN12, NMOS tube MN13 and NMOS tube MN14, wherein the source of the PMOS tube MP10 and the source of the PMOS tube MP11 constitute the power supply end of the current feedback loop circuit, the gate of the PMOS tube MP10, the gate of the PMOS tube MP11, the drain of the PMOS tube MP11 and the drain of the NMOS tube MN11 are connected; the drain of the PMOS tube MP10 is connected with the drain of the NMOS tube MN10, one end of the connection position constitutes the input end of the current feedback loop circuit, the other end of the connection position is connected with the gate of the NMOS tube MN14, and the other end of the connection position constitutes the output end of the current feedback loop circuit; the gate of the NMOS tube MN10, the gate of the NMOS tube MN11, the source of the NMOS tube MN14, the drain of the NMOS tube MN12, the gate of the NMOS tube MN12 and the gate of the NMOS tube MN13 are connected; the drain of the NMOS tube MN13 constitutes the feedback end of the current feedback loop circuit; the source of the NMOS tube MN10, the source of the NMOS tube MN11, the source of the NMOS tube MN12 and the source of the NMOS tube MN13 all constitute the ground end of the current feedback loop circuit.

[0011] As a preferred technical scheme of the present application: the error amplifier circuit comprises PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, NMOS tubes MN1, MN2, MN3, MN4, and a capacitor Cc; wherein the source of the PMOS tube MP1, the source of the PMOS tube MP4, and the source of the PMOS tube MP7 all constitute the power supply end of the error amplifier circuit; the gate of the PMOS tube MP1 constitutes the bias signal end of the error amplifier circuit; the drain of the PMOS tube MP1, the source of the PMOS tube MP2, and the source of the PMOS tube MP3 are connected; the gate of the PMOS tube MP2 is externally connected with a preset reference voltage V REF ; the drain of the PMOS tube MP2, the drain of the NMOS tube MN2, and the source of the NMOS tube MN1 are connected; the source of the NMOS tube MN2 and the source of the NMOS tube MN3 both constitute the ground end of the error amplifier circuit; the gate of the NMOS tube MN2 and the gate of the NMOS tube MN3 are connected, and the connection position is externally connected with a control signal Vbn1; the drain of the PMOS tube MP3, the drain of the NMOS tube MN3, and the source of the NMOS tube MN4 are connected, the gate of the NMOS tube MN1 and the gate of the NMOS tube MN4 are connected, and the connection position is externally connected with a control signal Vbn2; the gate of the PMOS tube MP3 constitutes the feedback end of the error amplifier circuit; the drain of the PMOS tube MP4 is connected with the source of the PMOS tube MP5; the gate of the PMOS tube MP5 is connected with the gate of the PMOS tube MP6, and the connection position is externally connected with a control signal Vbn1; the drain of the PMOS tube MP5, the drain of the NMOS tube MN1, the gate of the PMOS tube MP4, and the gate of the PMOS tube MP7 are connected; the drain of the PMOS tube MP7 is connected with the source of the PMOS tube MP6, the drain of the PMOS tube MP6, the drain of the NMOS tube MN4, and one end of the capacitor Cc are connected, and the connection end constitutes the output end of the error amplifier circuit; the other end of the capacitor Cc constitutes the ground end of the error amplifier circuit.

[0012] As a preferred technical scheme of the present application: the super source follower circuit comprises a PMOS tube MP8, a PMOS tube MP9, an NMOS tube MN8 and an NMOS tube MN9, wherein the source of the PMOS tube MP8 constitutes a power supply end of the super source follower circuit; the gate of the PMOS tube MP8 constitutes a bias signal end of the super source follower circuit; the drain of the PMOS tube MP8, the source of the PMOS tube MP9 and the drain of the NMOS tube MN9 are connected, and the connected end constitutes an output end of the super source follower circuit; the gate of the PMOS tube MP9 constitutes an input end of the super source follower circuit; the drain of the PMOS tube MP9, the gate of the NMOS tube MN9 and the drain of the NMOS tube MN8 are connected; the gate of the NMOS tube MN8 is externally connected with a control signal Vbn1; the source of the NMOS tube MN8 and the source of the NMOS tube MN9 constitute a ground end of the super source follower circuit.

[0013] Compared with the prior art, the low-dropout linear voltage regulator capable of enhancing transient response and ripple rejection ratio has the following technical effects:

[0014] (1) The low-dropout linear voltage regulator capable of enhancing transient response and ripple rejection ratio is designed based on an error amplifier circuit, a summing stage circuit, a super source follower circuit and a current feedback loop circuit, and three signal feedback loops, i.e., a voltage feedback main loop, a feedback enhancement loop and a current feedback loop, are realized through a design scheme, so that in application, the low-dropout linear voltage regulator has fast transient response and high ripple rejection ratio, can adaptively adjust the current size of the buffer stage according to the size of the load current, avoids waste of power consumption, reduces cost and design complexity, and on the basis of significantly improving transient response, reduces the size of power consumption, and realizes fast transient response and ripple rejection ratio. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a schematic diagram of the low-dropout linear voltage regulator capable of enhancing transient response and ripple rejection ratio designed by the present application;

[0016] Figure 2 is a working mechanism schematic diagram of the current feedback loop in the design of the present application;

[0017] Figure 3 is a small signal model analysis schematic diagram of the design of the present application;

[0018] Figure 4a is a transient response simulation result graph of the application of the step current set to -95mA in the design of the present application;

[0019] Figure 4b is a transient response simulation result graph of the application of the step current set to 100mA in the design of the present application;

[0020] Figure 5 This is a simulation result of the ripple suppression ratio in the design and application of this invention. Detailed Implementation

[0021] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0022] The low-dropout linear regulator designed in this invention can enhance transient response and ripple rejection ratio. In practical applications, such as... Figure 1 As shown, the specific design includes an NMOS transistor Mp, an error amplifier circuit, a summing stage circuit, a super source follower circuit, and a current feedback loop circuit. The power supply, ground, and bias signal terminals of the error amplifier circuit and the super source follower circuit are respectively connected to power supply V. BAT The ground (GND), bias signal (Idc), summing stage circuit, and current feedback loop circuit are connected to the power supply (V) and ground respectively. BAT Ground (GND); the output of the error amplifier circuit is connected to the input of the summing stage circuit, the output of the summing stage circuit is connected to the input of the super source follower circuit, the output of the super source follower circuit is connected to the input of the current feedback loop circuit, and the output of the current feedback loop circuit is connected to the gate of the NMOS transistor Mp.

[0023] like Figure 1 As shown, the drain of NMOS transistor Mp forms the input terminal of the low-dropout linear regulator, used to receive the signal to be regulated; the source of NMOS transistor Mp forms the output terminal of the low-dropout linear regulator, and the source of NMOS transistor Mp is connected to the feedback terminal of the error amplifier circuit, the feedback terminal of the summing stage circuit, and the feedback terminal of the current feedback loop circuit.

[0024] Regarding the low-dropout linear regulator designed above, in practical applications, further specific structural designs are needed for each circuit, such as... Figure 1 As shown, the error amplifier circuit specifically includes PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, and MP7, NMOS transistors MN1, MN2, MN3, and MN4, and capacitor Cc. The sources of PMOS transistors MP1, MP4, and MP7 constitute the power supply terminals of the error amplifier circuit. The gate of PMOS transistor MP1 constitutes the bias signal terminal of the error amplifier circuit. The drains of PMOS transistor MP1, the sources of PMOS transistor MP2 and MP3 are connected together. The gate of PMOS transistor MP2 is externally connected to a preset reference voltage V. REFThe drain of the PMOS tube MP2, the drain of the NMOS tube MN2 and the source of the NMOS tube MN1 are connected; the source of the NMOS tube MN2 and the source of the NMOS tube MN3 both constitute the ground terminal of the error amplifier circuit; the gate of the NMOS tube MN2 and the gate of the NMOS tube MN3 are connected, and the connection position is externally connected with the control signal Vbn1; the drain of the PMOS tube MP3, the drain of the NMOS tube MN3 and the source of the NMOS tube MN4 are connected, the gate of the NMOS tube MN1 and the gate of the NMOS tube MN4 are connected, and the connection position is externally connected with the control signal Vbn2; the gate of the PMOS tube MP3 constitutes the feedback terminal of the error amplifier circuit; the drain of the PMOS tube MP4 is connected with the source of the PMOS tube MP5; the gate of the PMOS tube MP5 is connected with the gate of the PMOS tube MP6, and the connection position is externally connected with the control signal Vbn1; the drain of the PMOS tube MP5, the drain of the NMOS tube MN1, the gate of the PMOS tube MP4 and the gate of the PMOS tube MP7 are connected; the drain of the PMOS tube MP7 is connected with the source of the PMOS tube MP6, the drain of the PMOS tube MP6, the drain of the NMOS tube MN4 and one end of the capacitor Cc are connected, and the connection terminal constitutes the output terminal of the error amplifier circuit, and the other end of the capacitor Cc constitutes the ground terminal of the error amplifier circuit.

[0025] The summing stage circuit is shown as Figure 1 The specific design includes the NMOS tube MN5, the NMOS tube MN6 and the NMOS tube MN7, wherein the gate of the NMOS tube MN5 constitutes the input terminal of the summing stage circuit, and the drain of the NMOS tube MN5 constitutes the power supply terminal of the summing stage circuit; the source of the NMOS tube MN5 and the drain of the NMOS tube MN6 are connected, and the connection terminal constitutes the output terminal of the summing stage circuit; the gate of the NMOS tube MN6 is externally connected with the control signal Vbn2; the source of the NMOS tube MN6 is connected with the drain of the NMOS tube MN7, the gate of the NMOS tube MN7 constitutes the feedback terminal of the summing stage circuit, and the source of the NMOS tube MN7 constitutes the ground terminal of the summing stage circuit.

[0026] The super source follower circuit is shown as Figure 1As shown, the specific design includes PMOS MP8, PMOS MP9, NMOS MN8, NMOS MN9, wherein the source of PMOS MP8 constitutes the power supply end of the super source follower circuit; the gate of PMOS MP8 constitutes the bias signal end of the super source follower circuit; the drain of PMOS MP8, the source of PMOS MP9, and the drain of NMOS MN9 are connected, and the connected end constitutes the output end of the super source follower circuit; the gate of PMOS MP9 constitutes the input end of the super source follower circuit; the drain of PMOS MP9, the gate of NMOS MN9, and the drain of NMOS MN8 are connected; the gate of NMOS MN8 is externally connected with the control signal Vbn1; the source of NMOS MN8 and the source of NMOS MN9 constitute the ground end of the super source follower circuit.

[0027] The current feedback loop circuit is as shown in Figure 1 As shown, the specific design includes PMOS MP10, PMOS MP11, NMOS MN10, NMOS MN11, NMOS MN12, NMOS MN13, and NMOS MN14, wherein the source of PMOS MP10 and the source of PMOS MP11 constitute the power supply end of the current feedback loop circuit, and the gate of PMOS MP10, the gate of PMOS MP11, the drain of PMOS MP11, and the drain of NMOS MN11 are connected; the drain of PMOS MP10 and the drain of NMOS MN10 are connected, one end of the connected position constitutes the input end of the current feedback loop circuit, the other end of the connected position is connected with the gate of NMOS MN14, and the other end of the connected position constitutes the output end of the current feedback loop circuit, the gate of NMOS MN10, the gate of NMOS MN11, the source of NMOS MN14, the drain of NMOS MN12, the gate of NMOS MN12, and the gate of NMOS MN13 are connected; the drain of NMOS MN13 constitutes the feedback end of the current feedback loop circuit; the source of NMOS MN10, the source of NMOS MN11, the source of NMOS MN12, and the source of NMOS MN13 all constitute the ground end of the current feedback loop circuit.

[0028] In actual application, according to Figure 1 As shown, the output voltage V OUT The voltage feedback loop through path one is in the error amplifier circuit with the preset reference voltage V REFThe comparison is made, and the error is amplified and output to the subsequent circuit to provide input to the subsequent circuit; the summing stage circuit superimposes the output of the error amplifier circuit and the output of the path two feedback enhancement loop to generate a stronger feedback signal into the super source follower circuit, which can provide stronger charging and discharging current for the gate capacitance of the power tube, thereby greatly improving the transient response of the low dropout linear regulator; the path three current feedback loop senses the load current and adaptively provides stronger charging and discharging efficiency for the super source follower circuit, thereby further enhancing the speed of the transient response, and the NMOS tube Mp provides voltage and current for the subsequent circuit.

[0029] Specifically, in the path one voltage feedback loop, the error amplifier circuit, the summing stage circuit, the super source follower circuit, and the NMOS tube Mp are adopted, and a folded cascade operational amplifier with high gain and high slew rate is used to achieve high loop gain and load regulation rate. In addition, the super source follower circuit acts as a buffer to accelerate the rapid charging and discharging of the gate capacitance of the power transistor, while isolating the main and secondary poles. This configuration improves the transient response and enhances the stability of the circuit.

[0030] In the path two feedback enhancement loop, the summing stage circuit, the super source follower circuit, and the NMOS tube Mp are connected in this order, and the output voltage is introduced into the main loop through the summing stage, thereby enhancing the feedback of the entire system and helping to achieve fast transient response and high power supply rejection ratio.

[0031] In the path three current feedback loop, the current sensing module can detect the amplitude of the load current to adaptively control the current of the power transistor gate. For example, when the load current suddenly increases, the current sensing module can provide additional current to quickly charge the gate capacitance of the power transistor. This operation reduces the overshoot voltage and recovery time, significantly enhancing the transient response. The working mechanism of the current feedback loop is shown in Figure 2 In this feedback loop, the NMOS tube MN14 senses the size of the load current without requiring a large amount of current. Therefore, to reduce power consumption, the ratio between the width and length of the NMOS tube Mp and the NMOS tube MN14 is set to 1600:1. This ratio does not need to be very accurate. It only needs to reflect the trend of the change in load current while ensuring that the NMOS tube MN14 can remain on. The sensed current is then transmitted to the current mirror composed of the NMOS tube MN11 and the NMOS tube MN12. This current is further transmitted to the current mirror composed of the PMOS tube MP10 and the PMOS tube MP11 to charge the gate of the power transistor, effectively acting as a slew rate enhancement circuit to enhance the transient response of the low dropout linear regulator designed in this patent. When the load current is low, the current in this module is small, reducing the standby current without affecting the operating performance.

[0032] The buffer that the super source follower circuit acts as provides only a fixed source current. When a load transient occurs, NMOS transistor MN14 senses the change in gate voltage of NMOS transistor Mp caused by path one and path two, thereby providing a dynamic source current for the buffer. This dynamic adjustment passes through the entire current feedback loop, allowing greater current to charge the gate capacitance of the power transistor, thereby enabling improved transient response.

[0033] The main control loop of the low dropout linear regulator designed in this invention has four poles in total, as shown in Figure 3 where Vo1 acts as the dominant pole and Vo4 acts as the secondary pole. These poles can be expressed as equations (1) and (2) below:

[0034]

[0035] In (1), R O1 represents the output resistance of the folded cascode operational amplifier, which is designed to be a very large value in order to achieve higher gain. Therefore, for V O1 , the resistance to ground of this node can be approximated as the output resistance of the operational amplifier. C C is a 6pF capacitor connected to ground, while the output capacitance of the operational amplifier can be neglected. Therefore, the capacitance C O1 can be approximated as C C . C L represents the load capacitance, which also includes the gate-source capacitance of the power transistor, and its value is usually very large. Therefore, the pole associated with node V O4 can be approximated as shown in equation (2).

[0036] Therefore, for these two nodes, it is clear that they have very large capacitances or resistances to ground. However, for V O2 and V O3 , the associated parasitic capacitance to ground is significantly smaller compared to V O1 and V O4 . Therefore, poles p2 and p3 can be considered as high frequency poles, and their effect on the stability of the circuit can be neglected. The only nodes that have a significant effect on the stability of the circuit are pi and p4. In order to solve this stability problem, a capacitance to ground is introduced in the design of this invention, which is connected to the output node of the operational amplifier, thereby reducing pi. This involves a trade-off between bandwidth and more stable operating conditions.

[0037] As shown in Figure 4a and Figure 4bAs shown, the transient responses of the load current of 100mA are respectively depicted, in which the step current sizes are -95mA and 100mA respectively. It can be obviously seen from the simulation results that when the step current is -95mA, the overshoot voltage is 29mV and the undershoot voltage is 23mV. When the step current is 100mA, the overshoot voltage is 8mV and the undershoot voltage is 7mV. As shown in Figure 5 As shown, the output voltage of the low-dropout linear regulator designed by the application is shown to change with the load current, and it can be obviously seen that the load current range of the low-dropout linear regulator is from 1mA to 200mA. According to the simulation results, the load regulation of the low-dropout linear regulator is 0.895μV / mA.

[0038] The simulation of the low-dropout linear regulator designed by the application is performed at the load current of 100mA, which is exactly at the midpoint of the load current range. It can be seen that the low-dropout linear regulator can work normally when the input voltage is greater than 720mV. By analyzing the output change from this point to the input voltage of 1.8V, it can be obviously seen that the linear regulation of the low-dropout linear regulator is only 0.017mV / V.

[0039] The low-dropout linear regulator designed by the above technical solution can enhance the transient response and ripple rejection ratio. Based on the error amplifier circuit, the summing stage circuit, the super source follower circuit and the current feedback loop circuit, the circuit is built by the design scheme, and three signal feedback loops of the voltage feedback main loop, the feedback enhancement loop and the current feedback loop are realized. In application, the low-dropout linear regulator has fast transient response and high ripple rejection ratio, can adaptively adjust the current size of the buffer stage according to the size of the load current, avoids the waste of power consumption, reduces the cost and design complexity, and on the basis of significantly improving the transient response, reduces the size of the power consumption, realizes the fast transient response and the ripple rejection ratio.

[0040] The embodiments of the application are described in detail above in combination with the drawings, but the application is not limited to the above embodiments. Within the knowledge of those skilled in the art, various changes can be made without departing from the purpose of the application.

Claims

1. A low-dropout linear regulator that enhances transient response and ripple rejection ratio, used to achieve linear voltage regulation for the signal to be regulated, characterized in that: This includes an NMOS transistor Mp, an error amplifier circuit, a super source follower circuit, a summing stage circuit, and a current feedback loop circuit. The power supply, ground, and bias signal terminals of the error amplifier circuit and the super source follower circuit are respectively connected to power supply V. BAT Ground GND, bias signal Idc; the drain of NMOS transistor Mp forms the input terminal of the low dropout linear regulator, used to receive the signal to be regulated; the source of NMOS transistor Mp forms the output terminal of the low dropout linear regulator, and the source of NMOS transistor Mp is connected to the feedback terminal of the error amplifier circuit. The power supply terminal and ground terminal of the summing stage circuit are respectively connected to the power supply V. BAT Ground GND, the output terminal of the error amplifier circuit is connected to the input terminal of the summing stage circuit, the output terminal of the summing stage circuit is connected to the input terminal of the super source follower circuit, and the source of the NMOS transistor Mp is connected to the feedback terminal of the summing stage circuit. The current feedback loop circuit includes PMOS transistors MP10, MP11, NMOS transistors MN10, MN11, MN12, MN13, and MN14. The source of PMOS transistor MP10, the source of PMOS transistor MP11, and the drain of NMOS transistor MN14 constitute the power supply terminal of the current feedback loop circuit. The gates of PMOS transistors MP10, MP11, MP11, and MN11 are connected together. The drain of PMOS transistor MP10, NMOS transistor MN14... The drain of MOSFET MN10 and the gate of NMOS transistor MN14 are connected together. The gates of NMOS transistor MN10, MN11, MN14, MN12, MN12, and MN13 are connected together. The drain of NMOS transistor MN13 forms the feedback terminal of the current feedback loop circuit. The sources of NMOS transistors MN10, MN11, MN12, and MN13 all form the ground terminals of the current feedback loop circuit. The power supply terminal and ground terminal of the current feedback loop circuit are respectively connected to the power supply V. BAT The super source follower circuit's output terminal, the gate of NMOS transistor MN14, and the gate of NMOS transistor Mp are connected together. The source of NMOS transistor Mp is connected to the feedback terminal of the current feedback loop circuit.

2. The low-dropout linear regulator according to claim 1, characterized in that: The summing stage circuit includes NMOS transistors MN5, MN6, and MN7. The gate of NMOS transistor MN5 forms the input terminal of the summing stage circuit, and the drain of NMOS transistor MN5 forms the power supply terminal of the summing stage circuit. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN6, and this connection terminal forms the output terminal of the summing stage circuit. The gate of NMOS transistor MN6 is externally connected to the control signal Vbn2. The source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 forms the feedback terminal of the summing stage circuit, and the source of NMOS transistor MN7 forms the ground terminal of the summing stage circuit.

3. The low-dropout linear regulator according to claim 1, characterized in that: The error amplifier circuit includes PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, and MP7, NMOS transistors MN1, MN2, MN3, and MN4, and capacitor Cc. The sources of PMOS transistors MP1, MP4, and MP7 constitute the power supply terminals of the error amplifier circuit. The gate of PMOS transistor MP1 constitutes the bias signal terminal of the error amplifier circuit. The drains of PMOS transistor MP1, the sources of PMOS transistor MP2 and MP3 are connected together. The gate of PMOS transistor MP2 is externally connected to a preset reference voltage V. REF The drains of PMOS transistor MP2, NMOS transistor MN2, and NMOS transistor MN1 are connected together; the sources of NMOS transistors MN2 and MN3 both form the ground terminals of the error amplifier circuit; the gates of NMOS transistors MN2 and MN3 are connected, and an external control signal Vbn1 is connected to this connection point; the drains of PMOS transistor MP3, NMOS transistor MN3, and NMOS transistor MN4 are connected together; the gates of NMOS transistors MN1 and MN4 are connected, and an external control signal Vbn2 is connected to this connection point; the gate of PMOS transistor MP3 forms the error amplifier circuit. The feedback terminal; the drain of PMOS transistor MP4 is connected to the source of PMOS transistor MP5; the gate of PMOS transistor MP5 is connected to the gate of PMOS transistor MP6, and the control signal Vbp1 is externally connected to this connection position; the drain of PMOS transistor MP5, the drain of NMOS transistor MN1, the gate of PMOS transistor MP4, and the gate of PMOS transistor MP7 are connected together; the drain of PMOS transistor MP7 is connected to the source of PMOS transistor MP6, the drain of PMOS transistor MP6, the drain of NMOS transistor MN4, and one end of capacitor Cc are connected together, and this connection position constitutes the output terminal of the error amplifier circuit, and the other end of capacitor Cc constitutes the ground terminal of the error amplifier circuit.

4. The low-dropout linear regulator according to claim 1, characterized in that: The super source follower circuit includes PMOS transistors MP8, MP9, MN8, and MN9. The source of PMOS transistor MP8 forms the power supply terminal of the super source follower circuit; the gate of PMOS transistor MP8 forms the bias signal terminal of the super source follower circuit; the drains of PMOS transistor MP8, MP9, and MN9 are connected, and this connection forms the output terminal of the super source follower circuit; the gate of PMOS transistor MP9 forms the input terminal of the super source follower circuit; the drains of PMOS transistor MP9, MN9, and MN8 are connected; the gate of NMOS transistor MN8 is externally connected to a control signal Vbn1; and the sources of NMOS transistors MN8 and MN9 form the ground terminal of the super source follower circuit.

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