A hardware acceleration system for matrix SVD decomposition based on AXI bus

Abstract

The invention discloses a hardware acceleration system for realizing matrix SVD decomposition based on AXI bus. The system comprises a hardware math accelerator, DMA, RAM, register, FIFO and AXI bus module, and covers a driver for software and hardware to work in coordination. The principle is to write instructions through an external driver, use the system to execute sub-functions of SVD calculation, perform data read and write operations in registers and RAM, and realize internal and external data exchange with an external system through the AXI bus. The hardware math accelerator has four trigonometric function modules, which can be mobilized to perform parallel calculation when SVD performs iterative calculation, thereby shortening the calculation clock cycle. The invention adopts 64 64-bit registers and 4 32KB RAMs, which can meet the storage requirements of large-scale high-order matrices and support single-precision and double-precision calculations. The function of the internal hardware acceleration system is configured by writing instructions, which improves the flexibility and configurability of the system and can meet different application requirements.

Description

Technical Field

[0001] The invention relates to the field of digital chip design and signal processing, and in particular to a hardware acceleration system for realizing matrix SVD decomposition based on an AXI bus. Background Art

[0002] SVD is a matrix decomposition technique called singular value decomposition. For a matrix A, SVD decomposes it into the product of three matrices: A = UΣ(V^T), where U and V are called the left and right singular matrices respectively, Σ is a diagonal matrix, and the elements on its diagonal are called singular values. SVD decomposition is widely used in radar, GPS navigation, data dimensionality reduction and many other fields. Its principle can be understood as: a relatively complex large-scale matrix is ​​represented by multiplying three smaller and simpler sub-matrices. These three small matrices describe the important characteristics of the large matrix. Singular values ​​are the most important part of SVD. They describe the importance or weight of the matrix in each feature direction. The larger the singular value, the more important the feature space described by the corresponding singular vector. Such matrix decomposition technology can make the data set easier to use, reduce the computational overhead of the algorithm, and make the results easy to understand.

[0003] The AXI bus is a high-performance, high-bandwidth, low-latency, and scalable on-chip bus interface standard that is widely used in various system-level interconnections within the chip. It plays an important role in connecting various functional modules, achieving high-performance data transmission and communication, supporting complex system interconnection structures, and providing flow control and error handling. It is one of the key technologies in the design of modern SoC and MCU chips. It is a bus based on a master-slave architecture that provides a high degree of scalability and flexibility. The AXI bus includes several key signals and channels, such as address channels, data channels, write transfers, read transfers, etc. The design of the AXI bus takes into account performance, reliability, and scalability, so that different hardware modules can communicate through this standardized interface.

[0004] At present, there are many problems in the implementation of SVD decomposition. The computing performance of SVD decomposition basically determines the overall performance of a system. As a typical matrix operation, the demand for supporting high-performance and high-order matrix decomposition is gradually emerging. First, as a computationally and memory-intensive operation, SVD decomposition contains a large number of iterative operations. As the size of the matrix increases, the computational complexity and time-space complexity of matrix SVD decomposition will increase significantly, and the data iteration operation will take longer. Secondly, since the original matrix, left singular matrix, singular values, right singular matrix and intermediate data need to be stored during decomposition, a large amount of memory will be occupied, especially for large-scale high-order matrices, which requires a lot of storage. In addition, the iterative calculation process of SVD is dependent and interlocking, so it is difficult to completely decompose the calculation task into independent subtasks for parallel calculation, which greatly limits the parallel performance of the calculation. At the same time, due to the huge amount of calculation of SVD decomposition, the error accumulation is greater and the accuracy is seriously degraded during the iterative operation. In summary, considering the above situations, the performance of matrix SVD decomposition in real-time calculation by software is very poor and time-consuming. If it is implemented in hardware, the accuracy and memory access issues must be considered. These problems are the urgent problems to be solved in the current SVD decomposition in the field of chip design. The pursuit of large-scale, fast, and high-precision calculations is also the key point that the current SVD calculation urgently needs to break through.

[0005] Many scholars in this field have proposed a variety of improved methods for the hardware implementation of SVD decomposition. First, in terms of SVD parallel computing, researchers have proposed a Hestenes-Jacobi-based method for parallel acceleration of SVD calculations in a scalable FPGA engine. This method proposes a new MDS data sorting method, which can provide higher parallelism for the Jacobi algorithm and maximize the reuse of on-chip data. However, this sorting method is too complex and inconvenient to implement in digital chips using hardware Verilog code. In addition, FPGAs mainly rely on lookup tables for calculations, which have a very fine granularity and a large amount of resources are used for configurable on-chip routing and wiring, which leads to low utilization of computing resources. At the same time, implementing SVD decomposition on FPGAs is accompanied by a series of disadvantages, including high power consumption, high cost, limited clock frequency, and low integration. Therefore, implementing SVD calculations of matrices on FPGAs is still not the best choice. In addition, since it is necessary to consider the running speed of the chip and the real-time application of chip data, some researchers have comprehensively analyzed the commonly used algorithms for calculating SVD and proposed an implementation method combining the Jacobi algorithm and the CORDIC algorithm. The Jacobi algorithm requires the values ​​of the trigonometric functions of sine, cosine, square root and inverse tangent in each iteration, and the basic trigonometric functions can be easily calculated based on the CORDIC algorithm. Therefore, the researchers proposed a new scheme combining the Jacobi algorithm with the CORDIC algorithm to perform SVD decomposition. This new algorithm scheme has greatly improved the calculation speed. From the implementation method point of view, this method is the most effective way to realize SVD calculation, but this method is based on FPGA to realize SVD calculation. Although it is relatively scalable, its flexibility is still poor and the application scenario is single. If you want to adjust the model of SVD calculation, you need to redesign the calculation module. Although FPGA is programmable, its logic resources and clock resources are limited, and it cannot reach the performance level of ASIC. If this design method is applied to customized chips such as ASIC, it will lead to performance bottlenecks. Therefore, there are still too many limitations in pure hardware to realize SVD decomposition.

[0006] For intensive operations on large-scale high-order matrices such as SVD decomposition, in order to improve the calculation speed, many scholars have proposed methods for hardware acceleration. In the invention of "A hardware acceleration system for inverting arbitrary-order matrices based on cholesky decomposition using loop iteration", the author uses a loop iteration method to replace the traditional multiplication and accumulation calculation, which solves the result of cholesky decomposition and the inverse matrix of the triangular matrix, and optimizes the addressing complexity when reading and writing data; at the same time, this method uses a new matrix multiplication algorithm suitable for triangular matrices, which shortens the calculation time of matrix multiplication, and supports the inversion operation of complex matrices of arbitrary order from 4 to 256, ultimately achieving the characteristics of low hardware complexity and high storage resource utilization. However, in actual engineering applications, especially in the calculation of matrix SVD decomposition, the matrix elements that need to be calculated can be not only complex matrices but also real matrices, and the type of matrix is ​​not limited to triangular matrix calculations. In this invention, a matrix inversion operation is decomposed into three modules: Cholesky decomposition, triangular matrix inversion, and triangular matrix multiplication. The SVD decomposition operation itself is relatively large. If a matrix inversion is to be split into multiple modules, it will inevitably lead to an increase in system operation instructions. At the same time, SVD decomposition also requires multiplication operations of non-triangular matrices. This is because when SVD calculations are applied in radar and vehicle-mounted GPS navigation, actual needs must be taken into consideration, and the dimension of the matrix The number and accuracy are jointly determined by factors such as the number of visible satellites, measurement errors, solution algorithms and system dynamics. Therefore, whether the matrix is ​​a triangular matrix or a non-triangular matrix, a square matrix or a non-square matrix, these are constantly changing according to the actual application. Therefore, for the multiplication operation of non-triangular matrices, a separate multiplication module must be designed, which will inevitably lead to more modules inside the accelerator, greater design difficulty, and a larger chip area and higher cost. The invention does have a great improvement in the single complex matrix inversion function, but it cannot adapt to large-scale, general-purpose matrix operations such as SVD decomposition. Therefore, it is necessary to avoid limitations in functions and data types and achieve higher compatibility in order to reduce the design modules as much as possible. In addition, in the invention of "A Super-Speed ​​Matrix Operation Coprocessor System", the author also proposed a fast calculation method for matrix addition and multiplication. The invention is theoretically accelerated by n*n times compared with the traditional matrix multiplication method, and has the advantages of simple structure, high calculation efficiency and strong application targeting.However, the invention has limitations in data types. The data bus of the coprocessor system is 32 bits, so it cannot support 64-bit data transmission, so the system has limitations in data accuracy; at the same time, the four magic cube DRAM storage arrays are all 8*8*32-bit data, and the supported matrix dimension is 8*8, so there are great limitations on the matrix dimension, and the DRAM storage is not large enough, each DRAM has only 2048 bits, that is, 0.25KB; the invention does have a fast calculation speed for this single operation of matrix multiplication and addition, but it is only for low-order matrices. However, compared with the application of SVD decomposition in actual engineering, it is completely insufficient in terms of data bit width and matrix dimension. SVD decomposition is an iterative intensive operation. If a higher data bit width cannot be guaranteed, the final result will have a large error. At the same time, in order to ensure the representativeness of the SVD decomposition result, a larger matrix dimension is required to support it. Therefore, in the calculation of SVD decomposition, it is necessary to support high-order and high data bit width matrix calculations to ensure that the final result is accurate, effective and representative.

[0007] In summary, the current research on the implementation of matrix operations on hardware is far from enough, and the hardware implementation of SVD decomposition is even rarer. Although a single function of matrix operations is implemented, there are still great limitations in practical applications. These limitations have a great impact on SVD decomposition, a large-scale operation that brings together matrix operations, trigonometric functions, four arithmetic operations and other operations. The lower matrix dimension, less data bit width, single data type, and the calculation process that cannot change according to demand will cause the final result of SVD decomposition to be inaccurate or even wrong. In practical applications, in order to solve the various problems existing in the above-mentioned SVD decomposition calculation and meet the versatility of the calculation function, it is necessary to continue to optimize and solve the relevant methods for implementing matrix operations and other operations. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the above prior art, analyze the research status of the above SVD decomposition calculation and intensive matrix operation, the current SVD calculation, if completely relying on software implementation, the performance of the calculation will become very low, and it does not have the value of real-time application; if the SVD decomposition is realized by pure hardware, it is usually a fixed hardware circuit structure, the function and performance are relatively fixed, and it is not easy to modify and improve in the later stage. After the chip is taped out, the steps and implementation methods of the SVD calculation cannot be adjusted, and the application is very limited; and the pure hardware implementation of SVD decomposition requires an in-depth understanding of the functional design and verification of the chip, and the development and debugging cycle will increase exponentially. In order to further improve the optimization of SVD decomposition calculation in digital chips, the present invention discloses a hardware acceleration system for realizing matrix SVD decomposition based on AXI bus, designs a mathematical hardware acceleration system with general functions and integrates it into an MCU chip, communicates and exchanges data with other functional modules by means of AXI bus, and uses instructions to realize the complete function of SVD decomposition calculation while ensuring the calculation accuracy and speed. It is suitable for common hardware platforms such as FPGA or ASIC, and has better performance, lower power consumption and cost in customized integrated circuits such as ASIC. This method is very valuable in the current MCU chip design field and is convenient for extended application in various scenarios.

[0009] The present invention adopts the following technical solutions to realize the hardware acceleration system:

[0010] In the first aspect, the hardware mathematical acceleration and optimized parallel computing of general functions, the present invention uses a dedicated hardware mathematical accelerator module to accelerate the calculation of each sub-function required for SVD decomposition calculation, and makes full use of the parallelism of the hardware to improve the execution efficiency of the calculation. By realizing the calculation of the key step functions of SVD decomposition at the hardware level, the processing time of the decomposition calculation can be significantly reduced. The specific hardware mathematical accelerator module is as follows:

[0011] Module M1: FUNC function module. This module is designed based on the CORDIC algorithm. In terms of functions, it mainly includes the calculation functions of Sin, Cos, Arctan2, Sqrt and various trigonometric functions, which can meet all the requirements of SVD decomposition for trigonometric function calculations. In terms of accuracy, this module can support the calculation of 32-bit or 64-bit single and double-precision data under the IEEE754 standard, which can meet different numerical calculation accuracy requirements. At the same time, this module has 4 FUNC function modules, namely FUNC0, FUNC1, FUNC2, and FUNC3, which can meet the parallel calculation of multiple trigonometric functions, and can perform multiple functions simultaneously and multiple times to improve the calculation speed, and greatly reduce the calculation clock cycle, which meets the large-scale iterative calculation requirements during SVD decomposition calculations.

[0012] Module M2: MAT function module. In terms of functions, it mainly includes the calculation of various functions such as matrix transposition, matrix replication, matrix multiplication, matrix addition, matrix initialization, matrix autocorrelation and matrix row and column transformation; in terms of calculation accuracy, this module can also support single-precision 32-bit and double-precision 64-bit calculations under the IEEE754 standard; in terms of data type, the MAT module can support the calculation of both complex and real data types; in terms of matrix dimension, the MAT function module can also specify the dimension of the matrix. In the case of commonly used double-precision and real number calculations, the maximum matrix dimension can support 64*64, which can support not only square matrix calculations, but also non-square matrix calculations, triangular matrix or non-triangular matrix operations, and vector calculations.

[0013] If the operand is single-precision data under the IEEE754 standard, only the lower 32 bits of the register are used, thereby reducing the read and write operations of the register; if it is double-precision data, all 64 bits are used; this design method can flexibly adapt to different operand sizes, making the CPU more flexible and efficient when processing data of different precisions, while also saving hardware resources and reducing actual power consumption.

[0014] Module M3: Queue function module, the role of this module is to perform related operations on the instructions in the FIFO, and take out the instructions in the FIFO for the execution of the internal hardware math accelerator function. This module also includes single clock cycle function calculations, mainly including conditional inversion of values, conditional absolute value, conditional interrupt instructions and other related operations, and also supports single and double precision calculations. These functions can be completed within one clock cycle, so the registers can be operated directly without being executed in a complex state machine, which can avoid time waste and reduce the complexity of calculations.

[0015] The second aspect is flexibility and configuration options. The present invention provides a software driver that can configure the options of the hardware math acceleration system, including calculation accuracy, data format, matrix dimension, matrix type, function function, number of iterations, and selection of registers and RAM numbers used, so as to adapt to SVD decomposition calculations for matrices of different orders and data types. This can ensure that the present invention can be flexibly applied in a variety of application scenarios, and the relevant algorithm flow can be customized according to specific needs, so it has high flexibility.

[0016] There are 4 RAMs, namely RAM_A, RAM_B, RAM_C, and RAM_D, each of which is 32KB, i.e., 256*1024 bits, for storing matrix data; the RAMs used in the SVD calculation process can be randomly assigned numbers according to the order of the matrix and the calculation requirements, so that the intermediate results and final results of the high-order matrix SVD calculation can be accessed in parallel in the RAM without conflict; when performing matrix calculations, the input matrix is ​​written to the RAM in advance, and the four types of data storage formats of the matrix in the RAM are as follows:

[0017] Single-precision real numbers, bits 0-31 store the (0, 0) element, bits 32-63 store the (0, 1) element, bits 64-95 store the (0, 2) element, and so on;

[0018] Double-precision real numbers, 0-63 bits store the (0, 0) element, 64-127 bits store the (0, 1) element, 128-191 bits store the (0, 2) element, and so on;

[0019] Single-precision complex numbers, bits 0-31 store the real part of the element (0, 0), bits 32-63 store the imaginary part of the element (0, 0), bits 64-95 store the real part of the element (0, 1), bits 96-127 store the imaginary part of the element (0, 1), and so on;

[0020] Double-precision complex numbers, bits 0-63 store the real part of the element (0, 0), bits 64-127 store the imaginary part of the element (0, 0), bits 128-191 store the real part of the element (0, 1), bits 192-255 store the imaginary part of the element (0, 1), and so on;

[0021] The above (0, 0), (0, 1), and (0, 2) all represent the row and column coordinates of the matrix. A RAM address can access 1024 bits of data. If an address exceeds 1024 bits or the data of the next row of the matrix needs to start from a new RAM address. Based on this storage mode, the matrix module can easily read the real and imaginary parts of multiple elements at a time and process them simultaneously.

[0022] The third aspect is to optimize resource utilization efficiency. The present invention optimizes the hardware design to ensure that the utilization efficiency and speed of system resources are maximized when processing large-scale matrices. The hardware acts as a coprocessor, responsible for calculating and returning processing results. The use of hardware can share CPU computing resources and reduce computing delays. This involves the intelligent allocation and management of hardware resources to avoid unnecessary waste and improve computing efficiency.

[0023] Fourth aspect: AXI bus interface standardization. The present invention adopts the AXI bus standard in hardware implementation to seamlessly integrate the hardware acceleration system that implements the SVD decomposition sub-function with other system components. With the help of the AXI bus, DMA can control the efficient exchange of data between the internal hardware acceleration system and the external storage system.

[0024] The implementation method of the SVD decomposition calculation based on the AXI bus comprises the following steps:

[0025] Step S1: Write driver instructions externally according to the C model of the SVD algorithm, determine the specific matrix address, register and RAM number and the specific function number to be calculated according to the requirements, execute the relevant operation instructions in sequence, and realize the complete calculation process of SVD;

[0026] Step S2: Write the input value of the driver to an internal 64-bit FIFO. When the internal hardware math accelerator detects that there is an instruction in the FIFO, it takes out the instruction and executes the relevant calculation operation on the input value.

[0027] Step S3: During the calculation process, the hardware acceleration system uses 64 internal 64-bit registers, which can be read and written by the internal module. In addition, there are 4 RAMs, each of which is 32KB bytes. The CPU and internal control logic can access these four RAMs to store and read matrix data.

[0028] Step S4: Execute all instructions and write the calculated single value or matrix data into the register or RAM with the specified number.

[0029] Step S5: DMA takes the internal data from the register and RAM to the external storage system through the AXI bus interface, completing the overall hardware acceleration of SVD decomposition.

[0030] Furthermore, the instructions for the system to perform SVD calculations need to be flexibly configured according to the following format, which is written as follows:

[0031] FIFO_WR_EN = 1;

[0032] FIFO[31:0] = (cmd_idx<<0) + (idx_r0<<8) + (idx_r1<<14) +

[0033] (idx_r2<<20) + (complex_fmt<<26) + (precision<<27) + (gen_intr<<31);

[0034] FIFO[63:32] = (Row_size<<8) + (Col_size<<16) + (inter_num<<24);

[0035] Among them, FIFO_WR_EN is 1 to enable the 64-bit FIFO for write instructions, cmd_idx is the function number used; idx_r0, idx_r1, idx_r2, respectively represent two numerical input ports and one result output port; complex_fmt is the data type, 1 represents complex number, 0 represents real number; precision is the precision type, 1 is single precision, 0 is double precision; inter_num is the number of iterations; gen_intr indicates the interrupt operation at the end of the command; Row_size and Col_size represent the rows and columns of the input matrix respectively;

[0036] The instruction format, including the bit value of the instruction left shift, the function number, the matrix dimension, the data precision and type and other operations, can be reasonably adjusted according to the sub-function modules designed inside the hardware acceleration system, and the instruction format can be configured according to the function type called, so as to start a specific function to perform the SVD calculation.

[0037] The principle implemented in the present invention is:

[0038] The various sub-functions required in the SVD decomposition calculation are first split into different sub-modules and implemented through hardware, which simplifies the complexity of the SVD decomposition calculation and facilitates the design and verification of the module. In the SVD decomposition calculation, multiple trigonometric functions, matrix operations, and some addition, subtraction, multiplication and division operations are used, so these detailed functions are implemented one by one in the hardware acceleration system, and then the hardware acceleration system is integrated into the entire MCU chip. After the chip is taped out, the driver instructions are written outside the chip, and a series of hardware functions are configured with the instructions. The AXI bus is used to realize the communication between the external storage system and the internal hardware acceleration system and the internal and external data exchange, and the corresponding SVD decomposition complete function calculation is realized, thereby realizing the configurability, scalability and fast calculation requirements of SVD, and ensuring the universality of the function. At the same time, the SVD decomposition instructions can be adjusted as needed in real life scenarios to achieve the best performance.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The hardware acceleration system for realizing matrix SVD decomposition based on AXI bus provided by the present invention is more flexible than SVD decomposition directly realized by hardware. By utilizing the AXI bus standard, the hardware acceleration system can be easily integrated with other hardware modules and work seamlessly with other hardware components, and can support the collaborative work of software and hardware. The method can flexibly optimize the implementation mode of SVD decomposition and expand the calculation function, and also facilitate the efficient transmission of data of the internal hardware acceleration system and the external storage system.

[0041] 2. The present invention provides a hardware acceleration system to accelerate and optimize the performance of SVD decomposition calculation. The system includes 4 parallel FUNC modules, MAT and Queue function modules, which can be used for parallel calculation and pipeline operation of multiple functions at the same time, shorten the calculation clock cycle, and improve the execution speed of SVD calculation. At the same time, the hardware acceleration system acts as a coprocessor, releasing the burden of the main processor CPU, so that it can focus more on other tasks.

[0042] 3. The present invention provides configuration options for SVD decomposition calculation, allowing adjustment according to different application scenarios and functional requirements, such as matrix dimension, data precision, function type, data type, number of iterations, data storage address and other configuration options. This makes the present invention suitable for a variety of application environments, thereby providing greater selectivity and configurability in applications.

[0043] 4. The present invention provides a hardware acceleration system for implementing matrix SVD decomposition based on an AXI bus. In the hardware acceleration system, 64 64-bit registers, namely Reg0-Reg63, and 4 32KB RAMs, namely RAM_A, RAM_B, RAM_C, and RAM_D, are provided, which can meet the needs of storing and reading the results of large-scale matrix decomposition and intermediate values, and effectively avoid insufficient data storage space or data access conflicts.

[0044] 5. The hardware acceleration system for realizing matrix SVD decomposition based on AXI bus provided by the present invention has universal functions in the internal hardware math accelerator; in terms of matrix type, it can support not only square matrix calculations, but also non-square matrix calculations, triangular matrix or non-triangular matrix calculations, and vector calculations; in terms of data type, it can support 32-bit and 64-bit single and double-precision operations under the IEEE754 standard, meeting the calculation requirements of various complex situations. Therefore, the invention has relatively low functional limitations, and the use of functions can be determined according to needs, and has good universality.

[0045] 6. The present invention provides a hardware acceleration system for realizing matrix SVD decomposition based on AXI bus. The acceleration system can be applied to FPGA design or ASIC design. Due to its comprehensive functions and strong versatility, it can provide high customization, excellent performance and low power consumption in ASIC design. Compared with general processors or FPGAs, ASIC design can achieve higher operating speed, lower energy consumption, smaller chip area, higher integration and lower cost, and is suitable for application scenarios requiring high efficiency and high performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a system architecture diagram of the hardware acceleration system for realizing matrix SVD decomposition based on AXI bus proposed by the present invention;

[0047] Figure 2 This is an internal structure diagram of a mathematical hardware accelerator in a hardware acceleration system for realizing matrix SVD decomposition based on an AXI bus proposed by the present invention;

[0048] Figure 3 This is an example simulation waveform diagram of implementing multiple parallel calculations of multiple trigonometric functions based on the AXI bus proposed in the first embodiment;

[0049] Figure 4 This is a waveform diagram of register allocation for implementing multiple parallel calculations of multiple trigonometric functions based on the AXI bus proposed in Example 1;

[0050] Figure 5 This is an example simulation waveform diagram of realizing matrix transposition calculation based on AXI bus proposed in Example 2;

[0051] Figure 6 A waveform diagram for specifying different RAM allocations for input and output data of the matrix transposition calculation based on the AXI bus proposed in the second embodiment;

[0052] Figure 7 This is a flow chart of realizing matrix SVD decomposition based on AXI bus proposed by the present invention;

[0053] Figure 8 The three decomposition matrix result simulation waveforms of the matrix SVD decomposition based on the AXI bus proposed in the third embodiment;

[0054] Fig. 9 This is a calculation error analysis diagram of the final singular value result of the matrix SVD decomposition based on the AXI bus proposed in Example 3. DETAILED DESCRIPTION

[0055] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the accompanying drawings, and the words "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0056] Those skilled in the art will appreciate that one or more hardware modules in the relevant functional implementation steps, measures, and solutions mentioned in the present invention can be specially designed and manufactured for the desired purpose.

[0057] Embodiment 1: Implementing multiple parallel calculations of multiple trigonometric functions based on AXI bus

[0058] Figure 1 At the same time, the system architecture diagram of the hardware acceleration system based on AXI bus to realize matrix SVD decomposition is given. Based on this, multiple parallel calculations of multiple trigonometric functions are realized based on AXI bus and internal hardware acceleration system. The implementation method is to write operation instructions in the driver Hardware_Svd to realize multiple parallel calculations of multiple trigonometric functions. In the Hardware_Svd driver, the function numbers of trigonometric functions such as COS, SIN, TAN, LN, LOG, SQRT are given as 32, 33, 34, 45, 46, and 47 respectively. The calculation times of trigonometric functions such as COS, SIN, TAN, LN, LOG, and SQRT are 3 times except for LOG function which is calculated 10 times. The calculation precision is specified as 64-bit double precision type and the data type is real number. There is a 64-bit FIFO between the hardware acceleration system and the driver Hardware_Svd. The driver writes the instructions for realizing multiple parallel calculations of multiple trigonometric functions into the FIFO. When the hardware math accelerator in the hardware acceleration system detects that there are instructions in the FIFO, it takes out the instructions to execute related functions. The internal hardware math accelerator module that needs to perform calculations mainly includes four math library functions, namely FUNC0, FUNC1, FUNC2, and FUNC3. Figure 2 The figure shows the internal structure of the hardware math accelerator, which is used to perform parallel operations when calculating multiple trigonometric functions and multiple operations, thereby shortening the calculation clock cycle. Figure 3The simulation waveform diagram of the trigonometric function parallel calculation based on the AXI bus of this embodiment is shown. It can be seen that for multiple calculations, multiple FUNC modules can be triggered to reduce the clock cycle of the calculation. From the waveform diagram, it can be seen that new_func0_code_valid and new_func1_code_valid are set to high level multiple times, ensuring that multiple FUNC modules can be calculated in parallel when the amount of calculation is large. When large-scale iterative calculations are required, new_func0_code_valid, new_func1_code_valid, new_func2_code_valid, and new_func3_code_valid can all be set to high level, so that the four FUNC modules can be calculated in parallel to speed up the iteration speed.

[0059] In addition to the four FUNC modules in the hardware math accelerator, there is also a Queue module that can not only execute instructions in the FIFO, but also execute some single-cycle functions. In this embodiment, the driver performs the calculation of the two functions of data inversion and data absolute value, the corresponding function numbers are 1 and 2, the number of calculations is 1, the data type is real number, and the calculation accuracy is also 64-bit double precision type.

[0060] In addition, there are 64 64-bit registers in the hardware, which are respectively. In this embodiment, the final trigonometric function calculation results are specified to be stored in different registers to avoid conflicts and overwriting between data input and output results. The COS function is calculated three times, and the input values ​​are stored in registers Reg0, Reg2, and Reg4, and the output results are stored in registers Reg1, Reg3, and Reg5; the SIN function is calculated three times, and the input values ​​are stored in registers Reg6, Reg8, and Reg10, and the output results are stored in registers Reg7, Reg9, and Reg11; the TAN function is calculated three times, and the input values ​​are stored in registers Reg12, Reg14, and Reg16, and the output results are stored in registers Reg13, Reg15, and Reg17; the LN function is calculated three times, and the input values ​​are stored in registers Reg18, Reg20, and Reg22, and the output results are stored in registers Reg19, Reg21, and Reg23; the LOG function is calculated 10 times. Since the LOG function has two inputs and one output, and the inputs are input1 and input2 respectively, 30 registers are needed to store the data, so the data of input1 is stored in register Re g24, Reg27, Reg30, Reg33, Reg36, Reg39, Reg42, Reg45, Reg48, Reg51, store the data of input2 in registers Reg25, Reg28, Reg31, Reg34, Reg37, Reg40, Reg43, Reg46, Reg49, Reg52, and store the calculation results in registers Reg26, Reg29, Reg32, Reg35, Reg38, Reg41, Reg44, Reg47, Reg50, Reg53; the SQRT function is calculated three times, the input data is stored in Reg54, Reg56, Reg58, and the output results are stored in Reg55, Reg57, Reg59; the data negation function is calculated once, the input data is stored in Reg60, and the output data is stored in Reg61; the final data absolute value function stores the input data in Reg62 and the output data in Reg63. Figure 4 The waveform diagram of register allocation for realizing multiple parallel calculations of multiple trigonometric functions in this embodiment is shown. In the waveform, op_r0-op_r63, i.e., Reg0-Reg63, correspond to registers to realize on-demand allocation of registers for calculation data, and fully mobilize the 64 64-bit registers in the hardware module, while ensuring that there is no conflict or overlap between input and output data during large-scale data operations.

[0061] The implementation method of the embodiment specifically includes the following steps:

[0062] Step S1: externally write instruction drive, in the driver program, determine the specific function function, number of calculations, input and output register numbers and data precision.

[0063] Step S2: The input values ​​and operation instructions of the external driver are compiled by gcc and put into an internal 64-bit FIFO. When the internal math accelerator of the hardware acceleration system detects that there are instructions in the FIFO, it takes out the instruction execution state machine, performs relevant calculation operations on the input values, and executes the relevant functions of the instructions in sequence.

[0064] Step S3: After the trigonometric function instruction is executed, the internal state machine writes the input value and the calculated value into 64 64-bit registers with designated numbers.

[0065] Step S4: DMA takes the data in the internal hardware acceleration system from the register to the external storage system through the AXI bus interface, thereby completing multiple parallel calculations of multiple trigonometric functions.

[0066] In this embodiment, the registers configurable by the software driver are Reg0-Reg63, and the driver can call any number of the 64 64-bit configuration registers in the hardware acceleration system through instructions to perform the calculation of this embodiment. If the data is single precision, only the lower 32 bits of the register are used; if it is double precision, all 64 bits of registers Reg0-Reg63 are used. However, it should be understood by those skilled in the art that the number and size of the configuration registers can be determined according to the functions implemented, and the configuration registers can be a random one or any number of Reg0-Reg63, and the size of the stored data can be 32 bits or 64 bits, which is not limited in this application. Those skilled in the art can adjust the required number and size of registers to appropriate values ​​according to the actual needs of their own functions, and can also select the required specific register number according to the calculation requirements to store input and output data and temporary intermediate data.

[0067] Embodiment 2: Calculation of multi-dimensional matrix transposition based on AXI bus

[0068] by Figure 1Based on the system architecture of the hardware acceleration system for realizing matrix SVD decomposition based on AXI bus, the operation of matrix transposition based on AXI bus is realized. Similarly, instructions are written in the software driver Hardware_Svd to realize the operation of matrix transposition. The given data precision is a double precision type of 64 bits, the given data type is a complex number, and the matrix dimension is a square matrix of 8*8. Since the matrix data is batch data, it is necessary to set the starting address of the matrix input and output; in this embodiment, the starting data address of the matrix input data is 0x80000000, and the starting address of the output data is 0x81000000. Only the starting address needs to be given, and the system can load all data according to the relevant data type and precision type configuration and store it in the specified RAM of the hardware acceleration system. Figure 5 The simulation waveform of this embodiment is shown, the input matrix data is stored in RAM_A, and the matrix output data after transposition is stored in RAM_C. Figure 5 From the data shown in the global diagram, we can see that a_ram_rd_data indicates that the input matrix data is being read from RAM_A, and c_ram_wr_data indicates that the transposed matrix is ​​being written to RAM_C. Figure 5 As can be seen from the partial figure in the middle, since the complex number consists of a real part and an imaginary part and is double-precision, each matrix element occupies 128 bits, which is 32 numbers in hexadecimal.

[0069] In this embodiment, the allocation of RAM can also be specified, and the input data and output data can be stored in the specified RAM. In order to reflect this function, this embodiment is changed to store the input original matrix in RAM_B, read the matrix input data from RAM_B, and store the data result after the matrix transposition in RAM_D. Figure 6 It can be seen that as the clock cycle changes, there is data reading in b_ram_rd_data and data writing in d_ram_wr_data, while the other matrices a_ram_wr_data and c_ram_wr_data are both 0, which means that there is no data movement in RAM_A and RAM_C; through such flexible allocation, there will be no data conflict and overwriting in the RAM storing matrix data, which can meet the access of multiple matrices in complex calculations.

[0070] In the present embodiment, the configurable RAMs of the software driver Hardware_Svd are RAM_A, RAM_B, RAM_C, and RAM_D, respectively, and the driver can call any number of RAMs in the 4 32KB RAMs in the hardware acceleration system to perform the calculation of the present embodiment. However, it should be understood by those skilled in the art that the number and size of the configured RAMs can be determined according to the functions implemented and the complexity of the calculations, and the RAMs can be random one or any number of RAM_A, RAM_B, RAM_C, and RAM_D, and the size of the single element of the storage matrix can be determined according to the data type and the precision type, and can be 32 bits, 64 bits, or 128 bits, which is not limited in this application. Those skilled in the art can adjust the required RAM quantity and data storage size to suitable values ​​according to the actual needs of their own functions, and can also select the required specific RAM number to store the matrix data of input and output according to the calculation requirements.

[0071] Embodiment 3: Realizing matrix SVD decomposition based on AXI bus and internal hardware acceleration system

[0072] In this embodiment, the SVD decomposition input matrix is ​​a 4*4 matrix, and the execution process of the SVD decomposition is as follows: Figure 7 As shown in the figure, the calculation precision is 64-bit double precision type, and the data type is real number. In order to achieve higher precision, the number of iterations of the decomposition calculation is 15. The final calculation results are the left singular matrix, singular values, and right singular matrix. The results calculated by the hardware acceleration system are Figure 8 As shown in the figure, from top to bottom, the values ​​of c_ram_wr_data are represented as the 4 singular values ​​in the singular value matrix Σ, the left singular matrix U, and the transpose V^T of the right singular matrix. It can be seen from the figure that the 4 singular values ​​are distributed on the main diagonal and the other elements are 0.

[0073] In order to demonstrate the accuracy of the calculation results of the hardware acceleration system, this embodiment calculates matrices of various dimensions, various data sources, and different precisions, and compares the singular values ​​calculated by the hardware with the singular value results calculated by the software. Fig. 9It can be seen that the calculation results are accurate. In double-precision mode, if the source data is small, the accuracy can reach 1e-7 and above, and if the source data is large, the accuracy can still reach 1e-6; in single-precision mode, if the source data is small, the accuracy can reach 1e-5 and above, and if the source data is large, the accuracy can still reach 1e-4. Therefore, the performance of hardware-implemented SVD decomposition meets the pre-set goals and is sufficient to meet actual application requirements. Those skilled in the art can select the required specific RAM number to store the input and output matrices according to the actual needs of their own functions, and can also adjust the dimensions of the input matrix to a suitable value. Considering the actual needs, the accuracy can also be adjusted. In this embodiment, since the hardware simulation test platform used by me is Verdi, it is limited in simulation performance and is not convenient for simulating large-scale high-order matrices, but it is functionally consistent with the above description.

[0074] The embodiments of the present invention described above can effectively solve some problems existing in the prior art, and optimize the problems of high computational complexity, large memory consumption, slow computational speed, poor versatility, unsuitability for real-time applications, inflexible configuration, and non-scalability of SVD decomposition in the prior art. The present invention proposes a hardware acceleration system for realizing matrix SVD decomposition based on AXI bus, which realizes the sub-functions required for SVD calculation through hardware, and improves the calculation speed of SVD by realizing SVD decomposition through a driver combined with AXI bus. At the same time, it has multiple, large-scale storage system RAM and registers, which can be applicable to the decomposition requirements of large-scale matrices and solve the problem of data access conflict. The functional module is transferred to the hardware level for implementation, and the overall function of SVD is realized by driving, which can improve the performance of the entire system, and has the characteristics of simplicity, efficiency, versatility, and flexibility. This method based on AXI bus can realize functions for different application scenarios, and can continuously optimize the implementation scheme of SVD calculation according to needs.

[0075] The technical means disclosed in the scheme of the present invention are not limited to the technical means disclosed in the above-mentioned implementation mode, but also include technical schemes composed of any combination of the above technical features.

Claims

1. A hardware acceleration system for matrix SVD decomposition based on AXI bus, characterized in that : Through the AXI bus, the internal hardware acceleration system and the external system can work together and exchange data. The complete process of SVD decomposition is executed according to the instructions. The sub-functions of SVD calculation are realized through the hardware acceleration system. At the same time, the instructions can be freely configured to match different calculation requirements, and finally the calculation of left and right singular matrices and singular value matrices is realized; the hardware acceleration system includes hardware math accelerator, DMA, RAM, register, FIFO and AXI bus module, among which the hardware math accelerator includes 4 FUNC function modules, MAT function module and Queue function module; when this system performs matrix SVD decomposition calculation, the execution process of each module is as follows: first, the overall function of SVD decomposition is stored in the driver Hardware_Svd in the form of instructions, and the instructions are compiled by the gcc compiler and compiled into the FIFO of the hardware acceleration system; then the hardware math accelerator in the hardware acceleration system detects that there are instructions in the FIFO, and then takes out the instructions The corresponding function module in the hardware math accelerator is executed, and the corresponding sub-functions in the idle FUNC, MAT and Queue modules are called for calculation according to the corresponding configuration instructions; finally, the intermediate results or final results calculated in the hardware math accelerator are stored in the specified registers and RAM for external system reading; the system has a total of 64 64-bit registers, Reg0-Reg63, and the registers used by SVD in the iterative calculation process are numbered according to the order of the matrix and the calculation requirements, so as to achieve parallel and conflict-free access to memory of a large number of values; there are 4 RAMs, namely RAM_A, RAM_B, RAM_C, and RAM_D, each with a size of 32KB, i.e., 256*1024 bits, for storing matrix data; the RAM used in the SVD calculation process is randomly numbered according to the order of the matrix and the calculation requirements, so as to achieve parallel and conflict-free access to memory in RAM for the intermediate results and final results of the high-order matrix SVD calculation; When performing matrix calculations, the input matrix is ​​written into RAM in advance. The four types of matrix data storage formats in RAM are as follows: Single-precision real numbers, bits 0-31 store the (0, 0) element, bits 32-63 store the (0, 1) element, bits 64-95 store the (0, 2) element, and so on; Double-precision real numbers, 0-63 bits store the (0, 0) element, 64-127 bits store the (0, 1) element, 128-191 bits store the (0, 2) element, and so on; Single-precision complex numbers, bits 0-31 store the real part of the element (0, 0), bits 32-63 store the imaginary part of the element (0, 0), bits 64-95 store the real part of the element (0, 1), bits 96-127 store the imaginary part of the element (0, 1), and so on; Double-precision complex numbers, bits 0-63 store the real part of the element (0, 0), bits 64-127 store the imaginary part of the element (0, 0), bits 128-191 store the real part of the element (0, 1), bits 192-255 store the imaginary part of the element (0, 1), and so on; The above (0, 0), (0, 1), and (0, 2) all represent the row and column coordinates of the matrix. One RAM address accesses 1024 bits of data. If an address exceeds 1024 bits or the data of the next row of the matrix needs to start from a new RAM address. Based on the four types of data storage formats of the matrix in RAM, the matrix module facilitates reading the real and imaginary parts of multiple elements at a time and processing them simultaneously.

2. According to claim 1, a hardware acceleration system for implementing matrix SVD decomposition based on AXI bus is characterized in that: The data of the FUNC and Queue modules in the hardware math accelerator of this system supports single- and double-precision real number calculations under the IEEE754 standard, and the data of the MAT module supports single- and double-precision real and complex number calculations. The data type and precision can be configured as needed.

3. The hardware acceleration system for implementing matrix SVD decomposition based on AXI bus according to claim 2, characterized in that: If the operand is single-precision data under the IEEE754 standard, only the lower 32 bits of the register are used, thereby reducing the read and write operations of the register; if it is double-precision data, all 64 bits are used.

4. The hardware acceleration system for implementing matrix SVD decomposition based on AXI bus according to claim 1, characterized in that: The hardware math accelerator of this system has four parallel modules, FUNC0, FUNC1, FUNC2, and FUNC3. When the system performs iterative operations on SVD, if FUNC0 is busy, FUNC1 is called. If FUNC1 is not idle, FUNC2 and FUNC3 are called in sequence. This allows for parallel operations on large-scale data during iterative operations on high-order matrices, ensuring that the iterative process of the SVD operation will not be in a waiting state, thereby speeding up the SVD decomposition process.

5. The hardware acceleration system for implementing matrix SVD decomposition based on AXI bus according to claim 1, characterized in that: The matrix calculation dimensions supported by the MAT module in the hardware math accelerator are 2*2, 12*16, 32*32 and any number of matrices of different dimensions. For commonly used double-precision, real number type matrix calculations, the maximum dimension can support 64*64, and the matrix type can be square or non-square, triangular or non-triangular or vector operations.

6. The hardware acceleration system for implementing matrix SVD decomposition based on AXI bus according to claim 1, characterized in that: The hardware math accelerator in this system supports a variety of trigonometric functions, matrices and vectors, addition, subtraction, multiplication and division of floating-point numbers and other types of calculations, and all sub-functions are numbered separately. After execution, the sub-function instructions can be interrupted to proceed to the next sub-function calculation. It is convenient to write instructions in the driver program to continuously call different functions to perform SVD calculations. There is no functional conflict, which avoids the problem of instructions being overwritten or unable to be executed. In addition, each sub-function is universal and is not limited to special circumstances.

7. A method for realizing hardware acceleration of matrix SVD decomposition based on AXI bus, characterized in that: The implementation method comprises the following steps: Step S1: Write a driver instruction stream externally according to the principle of SVD calculation, determine the data address, register and RAM number and the specific function number to be calculated according to the requirements, and realize the complete calculation process of SVD decomposition by writing relevant operation instructions; Step S2: compile the instruction stream of the driver program through gcc, and the CPU operates the instructions into an internal 64-bit FIFO. The internal hardware math accelerator detects that there are instructions in the FIFO, then takes out the instructions and executes them in sequence; Step S3: The internal hardware math accelerator calls the corresponding sub-functions in the four parallel FUNC, MAT, and Queue modules according to the instructions to perform relevant calculation operations on the input values, including matrix initialization, calculation of two input matrices A*(A^T) and (A^T)*A, Jacobi iterative calculation, and finally singular value square root calculation; Step S4: During the calculation process, the hardware acceleration system uses 64 internal 64-bit registers, and the internal module reads and writes these registers; in addition, the internal system also includes 4 RAMs, each of which is 32KB. The CPU and the internal control logic access these four RAMs to store and read the matrix; Step S5: After all instructions are executed, the calculated intermediate values, singular values, left singular matrix and right singular matrix are written into the registers or RAM with the specified numbers; Step S6: The DMA control module takes the internal data from the designated registers and RAM to the external storage system through the AXI bus interface, completing the overall hardware acceleration of SVD decomposition.

8. The method for realizing hardware acceleration of matrix SVD decomposition based on AXI bus according to claim 7, characterized in that: The instructions for the system to perform SVD calculations need to be flexibly configured according to the following format, which is written as follows: FIFO_WR_EN = 1; FIFO[31:0] = (cmd_idx<<0) + (idx_r0<<8) + (idx_r1<<14) + (idx_r2<<20) + (complex_fmt<<26) + (precision<<27) + (gen_intr<<31); FIFO[63:32] = (Row_size<<8) + (Col_size <<16) + (inter_num<<24); Among them, FIFO_WR_EN is 1 to enable the 64-bit FIFO for write instructions, cmd_idx is the function number used; idx_r0, idx_r1, idx_r2, respectively represent two numerical input ports and one result output port; complex_fmt is the data type, 1 represents complex number, 0 represents real number; precision is the precision type, 1 is single precision, 0 is double precision; inter_num is the number of iterations; gen_intr indicates the interrupt operation at the end of the command; Row_size and Col_size represent the rows and columns of the input matrix respectively; The instruction format, including the bit value of the instruction left shift, the function number, the matrix dimension, the data precision and type and other operations, is reasonably adjusted according to the sub-function modules designed inside the hardware acceleration system, and the instruction format is configured according to the function type called, so as to start the function to perform the SVD calculation.

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