Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device and a semiconductor device, the method for manufacturing a semiconductor device comprising: preparing a substrate of a first conductivity type; setting a gate groove on the substrate of the first conductivity type, wherein the gate groove extends from the first main surface in a first direction toward a side close to the second main surface; setting a carrier accumulation layer of the first conductivity type and a base layer of the second conductivity type in the substrate, the gate groove penetrates the base layer and the carrier accumulation layer, the depth of the base layer in the first direction is H1, and H1 satisfies the relationship: H1>1um. Therefore, by setting a carrier accumulation layer in the substrate and ensuring that the depth of the base layer in the first direction exceeds 1um, not only the conduction voltage drop and conduction loss of the semiconductor device can be reduced, but also the switching performance of the semiconductor device can be guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In the development of insulated gate bipolar transistor devices, in order to reduce power loss in power modules, the insulated gate bipolar transistor is required to have low on-off loss and on-voltage. In order to reduce the on-loss of the insulated gate bipolar transistor device, a carrier accumulation layer can be designed under the P-type base region. The carrier accumulation layer is N-type and has a higher doping concentration than the N-drift region, which increases the hole barrier and prevents holes from entering the P-type base region from the N-drift region. Holes accumulate in the N-drift region, thereby enhancing the conductivity modulation effect and reducing the on-voltage drop.

[0003] In the prior art, when an N-type carrier accumulation layer is introduced, if the process of the N-type carrier accumulation layer does not match the process of the P-type base region well, it will affect the channel length of the insulated gate bipolar transistor, which will lead to uncontrollable switching speed of the device. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a method for manufacturing a semiconductor device, which can ensure switching performance.

[0005] Another object of the present invention is to provide a semiconductor device.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: preparing a substrate of a first conductive type, wherein the substrate has a first main surface and a second main surface on the opposite side of the first main surface, and the first main surface and the second main surface are spaced apart in a first direction; arranging a gate trench on the substrate of the first conductive type, wherein the gate trench extends from the first main surface in a first direction toward a side close to the second main surface; arranging a carrier accumulation layer of a first conductive type and a base layer of a second conductive type in the substrate, wherein the base layer is closer to the first main surface than the carrier accumulation layer, the gate trench penetrates the base layer and the carrier accumulation layer, and the depth of the base layer in the first direction is H1, and H1 satisfies the relationship: H1>1um.

[0007] Therefore, by providing a carrier accumulation layer in the substrate and ensuring that the depth of the base layer in the first direction exceeds 1 um, not only the on-state voltage drop and on-state loss of the semiconductor device can be reduced, but also the switching performance of the semiconductor device can be ensured.

[0008] In some examples of the present invention, a carrier accumulation layer of a first conductivity type and a base layer of a second conductivity type are arranged in the substrate, wherein the base layer is closer to the first main surface than the carrier accumulation layer, the gate trench penetrates the base layer and the carrier accumulation layer, the depth of the base layer in the first direction is H1, and H1 satisfies the relationship: H1>1um. The step also includes: injecting a first conductivity type of substance into the substrate to form the carrier accumulation layer; injecting a second conductivity type of substance into the substrate to form the base layer, and pushing the carrier accumulation layer and the base layer.

[0009] In some examples of the present invention, the material injection dose of the carrier accumulation layer is IPM1, the material injection dose of the base layer is IPM2, and IPM1 and IPM2 satisfy the relationship: 0.05IPM1=IPM2.

[0010] In some examples of the present invention, the substance concentration in the carrier accumulation layer is inversely proportional to the depth of the base layer in the first direction.

[0011] In some examples of the present invention, the material injection energy of the carrier accumulation layer is at the order of mega-electron-volts, and the material injection energy of the base layer is at the order of kilo-electron-volts.

[0012] According to some other examples of the present invention, a carrier accumulation layer of a first conductivity type and a base layer of a second conductivity type are arranged in the substrate, wherein, compared with the carrier accumulation layer, the base layer is closer to the first main surface, the gate trench penetrates the base layer and the carrier accumulation layer, the depth of the base layer in the first direction is H1, and H1 satisfies the relationship: H1>1um. The steps also include: injecting a second conductivity type of substance into the substrate to form the base layer; performing a well-pushing process on the base layer; injecting a first conductivity type of substance into the substrate to form the carrier accumulation layer, and no longer performing a well-pushing process on the carrier accumulation layer.

[0013] In some examples of the present invention, the material injection dose of the carrier accumulation layer is IPM1, the material injection dose of the base layer is IPM2, and IPM1 and IPM2 satisfy the relationship: IPM1≤IPM2.

[0014] In some examples of the present invention, the carrier accumulation layer injection energy is at the level of mega-electron-volts, and the base layer injection energy is at the level of kilo-electron-volts.

[0015] In some examples of the present invention, the depth of the gate trench in the first direction is H2, and H2 satisfies the relationship: 4um≤H2≤6um.

[0016] The semiconductor device according to the present invention is suitable for the above-mentioned method for manufacturing the semiconductor device.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2 is a partial flow chart of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3 is a partial flow chart of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 4 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0023] Figure 5 is a partial flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] Reference numerals:

[0025] 100. Semiconductor devices;

[0026] 1. substrate; 101. first main surface; 102. second main surface; 103. gate trench;

[0027] 2. Carrier accumulation layer; 3. Base layer; 4. Emitter metal; 5. Dielectric layer; 6. Emitter region; 7. Field stop layer; 8. Collector layer; 9. Collector metal; 10. Drift layer. DETAILED DESCRIPTION

[0028] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0029] Reference below Figure 1-Figure 5 A method for manufacturing a semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 is suitable for the method for manufacturing the semiconductor device 100. The semiconductor device 100 is, for example, an insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description.

[0030] Combination Figure 2-Figure 4 As shown, the manufacturing method of the semiconductor device 100 according to the present invention may mainly include:

[0031] S1, preparing a substrate 1 of a first conductive type, wherein the substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction;

[0032] S2, providing a gate trench 103 on the substrate 1 of the first conductivity type, wherein the gate trench 103 extends from the first main surface 101 in the first direction toward a side close to the second main surface 102;

[0033] S3. A carrier accumulation layer 2 of a first conductivity type and a base layer 3 of a second conductivity type are arranged in the substrate 1, wherein the base layer 3 is closer to the first main surface 101 than the carrier accumulation layer 2, and the gate trench 103 penetrates the base layer 3 and the carrier accumulation layer 2, and the depth of the base layer 3 in the first direction is H1, and H1 satisfies the relationship: H1>1um.

[0034] Specifically, the semiconductor device 100 is manufactured by first providing a substrate 1 as a manufacturing basis. In the embodiment of the present invention, the substrate 1 is a first conductive type drift layer 10. The first conductive type drift layer 10 includes a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101. The first main surface 101 and the second main surface 102 are spaced apart in the first direction to ensure that the size of the first conductive type drift layer 10 in the first direction meets the manufacturing requirements and performance requirements of the insulated gate bipolar transistor.

[0035] Furthermore, the first conductive type drift layer 10 is used as the substrate 1, and a gate trench 103 is provided on the substrate 1 to form a cell region of the insulated gate bipolar transistor. The gate trench 103 can provide a stable and reliable setting position for the gate in the insulated gate bipolar transistor to complete the forward conduction of the insulated gate bipolar transistor. The gate trench 103 is extended from the first main surface 101 in the first direction toward the side close to the second main surface 102, and the gate trench 103 can be extended to the drift layer 10 to increase the control of the electric field of the gate on the electron drift in the insulated gate bipolar transistor, which is conducive to the formation of the flow channel.

[0036] Further, after the gate trench 103 is formed, a carrier accumulation layer 2 and a base layer 3 begin to form in the substrate 1, wherein the carrier accumulation layer 2 is of the first conductivity type and the base layer 3 is of the second conductivity type. In the insulated gate bipolar transistor, a carrier accumulation layer 2 is added, and the doping concentration of the carrier accumulation layer 2 is higher than that of the drift layer 10 of the first conductivity type, so that the hole barrier can be increased, and holes can be prevented from entering the base layer 3 of the second conductivity type from the drift layer 10 of the first conductivity type, so that holes accumulate in the drift layer 10 of the first conductivity type, thereby enhancing the conductivity modulation effect of the insulated gate bipolar transistor, reducing the on-state voltage drop of the insulated gate bipolar transistor, and reducing the loss of the insulated gate bipolar transistor.

[0037] In an embodiment of the present invention, Figure 3 As shown, compared with the carrier accumulation layer 2, the base layer 3 is closer to the first main surface 101, which can prevent the holes in the first conductive parallel drift layer 10 from entering the second conductive type base layer 3. The gate trench 103 runs through the base layer 3 and the carrier accumulation layer 2, so that the gate voltage of the insulated gate bipolar transistor can control the electrons in the first conductive type drift layer 10.

[0038] Furthermore, combined with Figure 3 As shown, the depth of the base layer 3 in the first direction is set to H1, and H1 satisfies the relationship: H1>1um. Specifically, after the carrier accumulation layer 2 is set in the insulated gate bipolar transistor, if the depth of the base layer 3 in the first direction is set to not exceed 1um, this will cause the trench depth of the insulated gate bipolar transistor to be too small, which will cause the switching speed of the insulated gate bipolar transistor to be uncontrollable, thereby affecting the switching performance of the insulated gate bipolar transistor. Setting the depth of the base layer 3 in the first direction to exceed 1um can ensure that the trench depth of the insulated gate bipolar transistor meets the requirements, can ensure that the switching speed of the insulated gate bipolar transistor is possible, and can further ensure that the switching performance of the insulated gate bipolar transistor is stable.

[0039] According to some embodiments of the present invention, Figure 5 As shown, step S3 also includes:

[0040] S3-1, injecting a material of the first conductivity type into the substrate 1 to form a carrier accumulation layer 2;

[0041] S3-2, injecting a second conductive type of material into the substrate 1 to form a base layer 3, and performing push-trap on the carrier accumulation layer 2 and the base layer 3.

[0042] Specifically, after forming the gate trench 103 on the substrate 1 of the first conductivity type, the first conductivity type of material is firstly injected into the substrate 1 to form the carrier accumulation layer 2 on the substrate 1 of the first conductivity type, and then the second conductivity type of material is injected into the substrate 1 of the first conductivity type to form the base layer 3 on the substrate 1. Finally, the injected first conductivity type of material and the second conductivity type of material are subjected to a well-push process to increase the temperature of the first conductivity type of material and the second conductivity type of material to the first preset temperature after the first preset time, so that the first conductivity type of carrier accumulation layer 2 and the second conductivity type of base layer 3 are formed on the insulated gate bipolar transistor.

[0043] Such an arrangement allows the first conductive type carrier accumulation layer 2 and the second conductive type base layer 3 to share the well-pushing process, which not only simplifies the manufacturing convenience of the semiconductor device 100 and improves the manufacturing efficiency of the semiconductor device 100, but also controls the depth of the second conductive type base layer 3 in the first direction, thereby ensuring that the trench depth of the insulated gate bipolar transistor meets the manufacturing requirements of the insulated gate bipolar transistor, thereby solving the problem of the manufacturing process of the carrier accumulation layer 2 and the manufacturing process of the base layer 3 affecting the trench depth, and reducing the on-state voltage drop and conduction loss of the insulated gate bipolar transistor while ensuring the switching performance of the insulated gate bipolar transistor.

[0044] In an embodiment of the present invention, the material injection dose of the carrier accumulation layer 2 is IPM1, and the material injection dose of the base layer 3 is IPM2. IPM1 and IPM2 satisfy the relationship: 0.05IPM1=IPM2. Specifically, when the carrier accumulation layer 2 and the base layer 3 are manufactured by adopting step S3-1 and step S3-2, it is necessary to control the injection dose of the first conductive type carrier accumulation layer 2 to be one level lower than the injection dose of the second conductive type base layer 3, so as to ensure that the depth of the second conductive type base layer 3 in the second direction exceeds 1um. In an embodiment of the present invention, the injection dose of the first conductive type carrier accumulation layer 2 is 0.05 times the injection dose of the second conductive type base layer 3.

[0045] In an embodiment of the present invention, the concentration of the substance in the carrier accumulation layer 2 is inversely proportional to the depth of the base layer 3 in the first direction. Specifically, in the manufacturing method of the first conductivity type carrier accumulation layer 2 and the second conductivity type base layer 3 sharing the well-pushing process, when the concentration of the substance in the carrier accumulation layer 2 is high, the depth of the base layer 3 in the first direction is reduced, which will cause the setting of the carrier accumulation layer 2 to affect the trench depth of the insulated gate bipolar transistor, thereby affecting the switching performance of the insulated gate bipolar transistor. Therefore, in the embodiment of the present invention, it is necessary to set the injection dose of the first conductivity type carrier accumulation layer 2 to 0.05 times the injection dose of the second conductivity type base layer 3 to ensure that the trench depth of the insulated gate bipolar transistor exceeds 1um, thereby ensuring the switching performance of the insulated gate bipolar transistor.

[0046] In an embodiment of the present invention, the material injection energy of the carrier accumulation layer 2 is at the level of mega-electron volts, and the material injection energy of the base layer 3 is at the level of kilo-electron volts. This arrangement can ensure that the function of the carrier accumulation layer 2 in the embodiment of the present invention to block holes from entering the base layer 3 and the function of the base layer 3 to control the transmission of carriers in the semiconductor device 100 are normal, thereby ensuring the reliability of the carrier accumulation layer 2 in reducing the on-state voltage drop and conduction loss of the insulated gate bipolar transistor.

[0047] According to other embodiments of the present invention, Figure 5 As shown, step S3 also includes:

[0048] S3-3, injecting a second conductive type of material into the substrate 1 to form a base layer 3;

[0049] S3-4, performing a well-pushing process on the base layer 3;

[0050] S3-5, injecting a material of the first conductive type into the substrate 1 to form a carrier accumulation layer 2, and no longer performing well-pushing on the carrier accumulation layer 2.

[0051] Specifically, after forming the gate trench 103 on the substrate 1 of the first conductivity type, a substance of the second conductivity type is firstly injected into the substrate 1 of the first conductivity type, and then a push-well process is performed on the substance of the second conductivity type, so that the temperature of the substance of the second conductivity type is increased to a second preset temperature after a second preset time to form a base layer 3, and then the substance of the first conductivity type is injected into the substrate 1 of the first conductivity type to form a carrier accumulation layer 2. In the embodiment of the present invention, the second preset temperature is higher than the first preset temperature, so there is no need to push-well the injected carrier accumulation layer 2 of the first conductivity type, and thus, a carrier accumulation layer 2 of the first conductivity type and a base layer 3 of the second conductivity type are formed on the insulated gate bipolar transistor.

[0052] In an embodiment of the present invention, the material injection dose of the carrier accumulation layer 2 is IPM1, the material injection dose of the base layer 3 is IPM2, and IPM1 and IPM2 satisfy the relationship: IPM1≤IPM2. Specifically, when the carrier accumulation layer 2 and the base layer 3 are manufactured by adopting steps S3-3, S3-4 and S3-5, the highest material injection dose of the carrier accumulation layer 2 can be of the same order of magnitude as the material injection dose of the base layer 3, and can be the same as the material injection dose of the base layer 3 at most.

[0053] In an embodiment of the present invention, the injection energy of the carrier accumulation layer 2 is at the level of mega-electron-volts, and the injection energy of the base layer 3 is at the level of kilo-electron-volts. This arrangement can ensure that the function of the carrier accumulation layer 2 in the embodiment of the present invention to block holes from entering the base layer 3 and the function of the base layer 3 to control the transmission of carriers in the semiconductor device 100 are normal, thereby ensuring the reliability of the carrier accumulation layer 2 in reducing the on-state voltage drop and on-state loss of the insulated gate bipolar transistor.

[0054] According to some embodiments of the present invention, Figure 2 and Figure 3 As shown, the depth of the gate trench 103 in the first direction is H2, and H2 satisfies the relationship: 4um≤H2≤6um. Specifically, in the manufacturing method of the semiconductor device 100 of the present invention, the depth of the trench formed on the substrate 1 of the first conductivity type is between 4um and 6um, so that the gate trench 103 can be ensured to penetrate the base layer 3 and the carrier accumulation layer 2 and extend into the drift layer 10 while ensuring that the trench depth of the insulated gate bipolar transistor exceeds 1um, thereby ensuring the reliability of the control of the gate voltage of the insulated gate bipolar transistor on the electrons in the drift layer 10 of the first conductivity type.

[0055] According to an embodiment of the present invention, Figure 1 As shown, the semiconductor device 100 also includes an emitter metal 4, a dielectric layer 5, an emitter region 6 of the first conductivity type, a field stop layer 7, a collector layer 8, a collector metal 9 and an insulating layer. The semiconductor device 100 including a carrier accumulation layer 2 of the first conductivity type, a base layer 3 of the second conductivity type, a drift layer 10 of the first conductivity type, an emitter metal 4, a dielectric layer 5, an emitter region 6 of the first conductivity type, a field stop layer 7, a collector layer 8, a collector metal 9 and an insulating layer is suitable for a method for manufacturing the semiconductor device 100.

[0056] Combination Figure 4 As shown, after step S3, it also includes:

[0057] S4, forming an active layer of the first conductivity type on the substrate 1 as an emitter region 6 of the insulated gate bipolar transistor;

[0058] S5 , depositing emitter metal 4 and a passivation layer, thinning the substrate 1 and performing processes on the second main surface 102 to form a field stop layer 7 , a collector layer 8 and a collector metal 9 .

[0059] At this point, the preparation of the insulated gate bipolar transistor is completed. The semiconductor device 100 manufactured by the manufacturing method of the semiconductor device 100 of the present invention can not only add a carrier accumulation layer 2 in the insulated gate bipolar transistor to reduce the on-state voltage drop and conduction loss of the insulated gate bipolar transistor, but also ensure that the trench depth of the insulated gate bipolar transistor meets the requirements, and can ensure that the switching speed of the insulated gate bipolar transistor is controllable, thereby ensuring the switching performance of the insulated gate bipolar transistor.

[0060] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0061] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0062] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that include: Preparing a substrate (1) of a first conductive type, wherein the substrate (1) has a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), and the first main surface (101) and the second main surface (102) are arranged at intervals in a first direction; A gate trench (103) is provided on a substrate (1) of a first conductivity type, wherein the gate trench (103) is extended from the first main surface (101) in a first direction toward a side close to the second main surface (102); Injecting a material of a first conductivity type into the substrate (1) to form a carrier accumulation layer (2); Injecting a second conductive type of material into the substrate (1) to form a base layer (3), and performing well-pushing on the carrier accumulation layer (2) and the base layer (3); Compared with the carrier accumulation layer (2), the base layer (3) is closer to the first main surface (101), the gate groove (103) penetrates the base layer (3) and the carrier accumulation layer (2), the depth of the base layer (3) in the first direction is H1, H1 satisfies the relationship: H1>1um, the material injection dose of the carrier accumulation layer (2) is IPM1, the material injection dose of the base layer (3) is IPM2, IPM1 and IPM2 satisfy the relationship: 0.05IPM1=IPM2, and the material concentration in the carrier accumulation layer (2) is inversely proportional to the depth of the base layer (3) in the first direction.

2. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The material injection energy of the carrier accumulation layer (2) is at the level of mega-electron volts, and the material injection energy of the base layer (3) is at the level of kilo-electron volts.

3. A method for manufacturing a semiconductor device, It is characterized in that include: Preparing a substrate (1) of a first conductive type, wherein the substrate (1) has a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), and the first main surface (101) and the second main surface (102) are arranged at intervals in a first direction; A gate trench (103) is provided on a substrate (1) of a first conductivity type, wherein the gate trench (103) is extended from the first main surface (101) in a first direction toward a side close to the second main surface (102); Injecting a second conductive type of material into the substrate (1) to form a base layer (3); Performing a well-pushing process on the base layer (3); A material of a first conductive type is injected into the substrate (1) to form a carrier accumulation layer (2), and the carrier accumulation layer (2) is no longer pushed into a well, wherein the base layer (3) is closer to the first main surface (101) than the carrier accumulation layer (2), the gate trench (103) penetrates the base layer (3) and the carrier accumulation layer (2), and the depth of the base layer (3) in the first direction is H1, and H1 satisfies the relationship: H1>1um.

4. The method for manufacturing a semiconductor device according to claim 3, It is characterized in that The material injection dose of the carrier accumulation layer (2) is IPM1, the material injection dose of the base layer (3) is IPM2, and IPM1 and IPM2 satisfy the relationship: IPM1≤IPM2.

5. The method for manufacturing a semiconductor device according to claim 4, It is characterized in that The injection energy of the carrier accumulation layer (2) is at the level of mega-electron-volts, and the injection energy of the base layer (3) is at the level of kilo-electron-volts.

6. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The depth of the gate trench (103) in the first direction is H2, and H2 satisfies the relationship: 4um≤H2≤6um.

7. A semiconductor device, Features: The method for manufacturing a semiconductor device according to any one of claims 1 to 2 or the method for manufacturing a semiconductor device according to any one of claims 3 to 6.

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