IGBT device preparation method and IGBT device

Abstract

The present invention discloses an IGBT device preparation method and an IGBT device. The IGBT device preparation method comprises: providing an N-type substrate; the N-type substrate has a relatively low resistivity; depositing at least one N-type drift region with a resistivity higher than that of the N-type substrate on the front of the N-type substrate; performing ion implantation on the back of the N-type substrate to form an N-type buffer layer; wherein the resistivity of the N-type buffer layer is less than that of the N-type substrate; performing ion implantation on the back of the N-type buffer layer to form a P-type collector; forming an IGBT functional structure on the side of the N-type drift region away from the N-type substrate; wherein the IGBT functional structure comprises at least one trench gate structure, and the bottom of the trench gate structure is embedded in the N-type drift region. The technical solution of the embodiment of the present invention is conducive to reducing the switching loss of the FS‑IGBT power device, improving the switching speed of the FS‑IGBT power device, and reducing the switching oscillation of the device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an IGBT device preparation method and an IGBT device. Background Art

[0002] As a power semiconductor device, the Insulate-Gate Bipolar Transistor (IGBT) is widely used in rail transportation, smart grid, industrial energy saving, electric vehicles and new energy equipment, etc. It has the characteristics of energy saving, easy installation, easy maintenance and stable heat dissipation.

[0003] According to the device structure classification, IGBT has developed from punch-through (PT) IGBT to non-punch-through (NPT) IGBT, and currently to field stop (FS) IGBT. Among them, FS-IGBT reduces the saturation voltage drop and switching loss compared to PT-IGBT and NPT-IGBT. However, when the traditional FS-IGBT power device uses a semiconductor substrate as the drift layer of the power device, depending on the different doping concentrations of the semiconductor substrate, the electric field variation amplitude of the drift layer and the buffer layer may be too large, resulting in switching oscillation problems; or, although the electric field variation amplitude of the drift layer and the buffer layer is small, which can reduce switching oscillation, there will be problems of slow switching speed and high switching loss. Summary of the invention

[0004] The present invention provides an IGBT device preparation method and an IGBT device, so as to improve the switching speed of a FS-IGBT power device and reduce switching loss and switching oscillation.

[0005] According to one aspect of the present invention, a method for preparing an IGBT device is provided, comprising:

[0006] Providing an N-type substrate; the N-type substrate has a relatively low resistivity;

[0007] Depositing at least one layer of N-type drift region having a resistivity higher than that of the N-type substrate on the front side of the N-type substrate;

[0008] Performing ion implantation on the back side of the N-type substrate to form an N-type buffer layer; wherein the resistivity of the N-type buffer layer is less than the resistivity of the N-type substrate;

[0009] Performing ion implantation on the back side of the N-type buffer layer to form a P-type collector;

[0010] An IGBT functional structure is formed on a side of the N-type drift region away from the N-type substrate; wherein the IGBT functional structure includes at least one trench gate structure, and the bottom of the trench gate structure is embedded in the N-type drift region.

[0011] Optionally, the sum of the thicknesses of the N-type substrate and the N-type drift region is in the range of 50 to 130 μm, and the ratio of the thickness of the N-type drift region to the thickness of the N-type substrate is 2.

[0012] Optionally, the resistivity range of the N-type substrate is less than 30Ω·cm, and the resistivity range of the N-type drift region includes 70 to 150Ω·cm.

[0013] Optionally, depositing at least one layer of N-type drift region having a resistivity higher than that of the N-type substrate on the front side of the N-type substrate comprises:

[0014] Semiconductor materials with decreasing doping concentrations are sequentially deposited on the front surface of the N-type substrate to form at least two layers of the N-type drift region whose resistivity is higher than that of the N-type substrate and whose resistivity increases gradually.

[0015] Optionally, performing ion implantation on the back side of the N-type substrate to form an N-type buffer layer includes:

[0016] The back side of the N-type substrate is thinned, and N-type impurity ions are implanted from the back side of the N-type substrate to form the N-type buffer layer.

[0017] Optionally, a thickness range of the N-type buffer layer and a thickness range of the P-type collector both include 0.8-1.2 μm.

[0018] Optionally, forming an IGBT functional structure on a side of the N-type drift region away from the N-type substrate includes:

[0019] Etching from the front side of the N-type drift region to the inside to form at least one trench;

[0020] forming a gate oxide layer on the front surface of the N-type drift region and the inner wall of the trench;

[0021] Depositing a gate material in the trench to form a gate; wherein the gate fills the trench completely;

[0022] On a surface of the gate oxide layer away from the N-type drift region, ion implantation and diffusion are performed into the N-type drift region to form a P-type base region;

[0023] On a surface of the gate oxide layer away from the P-type base region, ion implantation and diffusion are performed into the P-type base region to form an N-type emitter region;

[0024] Forming an insulating layer and an emitter metal layer on a surface of the gate oxide layer away from the N-type emitter region;

[0025] Among them, the P-type base region includes at least one first through hole, the N-type emitter region includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate, and the second through hole is connected to the first through hole in a one-to-one correspondence; the second through holes and the trench gate structure are alternately arranged in the horizontal direction; at least two protrusions are arranged on the side of the emitter metal layer close to the N-type emitter region, and each of the protrusions is filled in the connected second through hole and the first through hole.

[0026] Optionally, the IGBT device manufacturing method further includes: depositing a metal material on a side of the P-type collector away from the N-type buffer layer to form a collector metal layer.

[0027] According to another aspect of the present invention, there is provided an IGBT device, which is manufactured by the IGBT device manufacturing method according to any embodiment of the first aspect;

[0028] The IGBT device comprises:

[0029] An N-type substrate having a relatively low resistivity;

[0030] At least one layer of N-type drift region is stacked on the front side of the N-type substrate; the resistivity of at least one layer of the N-type drift region is higher than the resistivity of the N-type substrate;

[0031] An N-type buffer layer is disposed on the back side of the N-type substrate; wherein the resistivity of the N-type buffer layer is less than the resistivity of the N-type substrate;

[0032] A P-type collector electrode disposed on the back side of the N-type buffer layer;

[0033] The IGBT functional structure is arranged on a side of the N-type drift region away from the N-type substrate; wherein the IGBT functional structure includes at least one trench gate structure, and the bottom of the trench gate structure is embedded in the N-type drift region.

[0034] Optionally, the trench gate structure comprises a trench, a gate and a gate oxide layer;

[0035] The gate fully fills the trench, and the gate oxide layer is arranged between the gate and the trench and on a surface of a side of the N-type drift region away from the N-type substrate;

[0036] The IGBT functional structure also includes a P-type base region, an N-type emitter region, an insulating layer and an emitter metal layer;

[0037] The P-type base region is arranged on a side of the N-type drift region away from the N-type substrate, and the N-type emitter region is arranged on a side of the P-type base region away from the N-type drift region; the trench gate structure penetrates the P-type base region and the N-type emitter region;

[0038] The P-type base region includes at least one first through hole, the N-type emitter region includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate, and the second through hole is connected to the first through hole in a one-to-one correspondence; the connected second through holes and the first through holes are alternately arranged with the trench gate structure in a horizontal direction;

[0039] At least two protrusions are provided on a side of the emitter metal layer close to the N-type emitter region, and each of the protrusions is filled in the second through hole and the first through hole that are connected;

[0040] The insulating layer is disposed between the trench gate structure and the emitter metal layer.

[0041] The technical solution of the embodiment of the present invention adopts a silicon wafer with an N-type conductivity type as a substrate, and the resistivity of the N-type substrate is relatively low. At least one layer of N-type drift region is formed on the front of the N-type substrate by a deposition method, and the resistivity of at least one layer of N-type drift region is higher than the resistivity of the N-type substrate, and the resistivity of the N-type substrate and the resistivity of at least one layer of N-type drift region show a trend of gradually increasing. Then, an N-type buffer layer is formed on the back of the N-type substrate by an ion implantation method, and the resistivity of the N-type buffer layer is made smaller than the resistivity of the N-type substrate. A P-type collector is formed by ion implantation on the back of the N-type buffer layer, and an IGBT functional structure including at least one trench gate structure is also formed on the side of the N-type drift region away from the N-type substrate. In this way, the FS-IGBT power device with a drift region whose resistivity changes sequentially using an N-type substrate is advantageous for improving the switching speed of the FS-IGBT power device and reducing the switching loss compared with the prior art that uses a semiconductor substrate with a single resistivity as the drift region. In addition, using an N-type substrate with a lower resistivity as the first buffer layer, and using an N-type buffer layer with a lower resistivity than the N-type substrate as the second buffer layer can reduce the variation of the generated electric field strength, thereby helping to reduce the switching oscillation of the FS-IGBT power device. When forming a P-type collector, the embodiment of the present invention adopts a method of ion implantation on the back of the N-type buffer layer. Compared with the method of using a P-type substrate and thinning the P-type substrate to obtain a P-type collector in the prior art, the P-type collector prepared by the embodiment of the present invention can achieve a smaller thickness, which is helpful to reduce the switching loss of the FS-IGBT power device.

[0042] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a schematic flow chart of a method for preparing an IGBT device according to an embodiment of the present invention;

[0045] Figure 2 It is a structural schematic diagram corresponding to each step in a method for preparing an IGBT device provided in an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of a specific flow chart of step S150 in a method for preparing an IGBT device according to an embodiment of the present invention;

[0047] Figure 4 It is a structural schematic diagram corresponding to specific steps of step S150 in a method for preparing an IGBT device provided according to an embodiment of the present invention;

[0048] Figure 5 is a schematic flow chart of another method for preparing an IGBT device according to an embodiment of the present invention;

[0049] Figure 6 It is a structural schematic diagram of each step in another method for preparing an IGBT device provided in an embodiment of the present invention;

[0050] Figure 7 is a schematic structural diagram of an IGBT device provided according to an embodiment of the present invention;

[0051] Figure 8 It is a schematic diagram of the structure of another IGBT device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0054] An embodiment of the present invention provides a method for preparing an IGBT device. Figure 1 A schematic diagram of a process for preparing an IGBT device provided by an embodiment of the present invention, Figure 2 1 is a schematic diagram of the structure corresponding to each step in a method for preparing an IGBT device provided by an embodiment of the present invention. Figure 1 and Figure 2 The IGBT device preparation method specifically comprises the following steps:

[0055] S110 , providing an N-type substrate 10 ; the N-type substrate 10 has a relatively low resistivity.

[0056] Exemplarily, an N-type conductive silicon substrate is used, so that the N-type substrate serves as the substrate of the FS-IGBT power device as a whole, and also has the functions of the second drift region and the first buffer layer of the power device. The doping concentration of the N-type substrate is higher, so the N-type substrate has a lower resistivity.

[0057] S120 , depositing at least one layer of N-type drift region 20 having a resistivity higher than that of the N-type substrate 10 on the front surface of the N-type substrate 10 .

[0058] Exemplarily, epitaxial growth is performed by a deposition method to form at least one layer of N-type drift region on one surface of the N-type substrate, that is, the front side of the N-type substrate. The at least one layer of N-type drift region serves as the first drift region of the FS-IGBT power device, and the doping concentration of the deposited at least one layer of N-type drift region is lower than that of the N-type substrate, so that the resistivity of the at least one layer of N-type drift region is higher than that of the N-type substrate, which is beneficial to improving the switching speed of the FS-IGBT power device and reducing the switching loss. Exemplarily, in an embodiment of the present invention, Figure 1 The structure of forming a layer of N-type drift region on the front side of the N-type substrate is shown. Since the FS-IGBT power device has a first drift region and a second drift region with varying doping concentrations, there is a transition between the electric fields generated by the drift region and the buffer layer, respectively, so that the electric field variation amplitude is small. Therefore, the use of an N-type substrate with a lower resistivity is beneficial to reducing the switching oscillation of the FS-IGBT power device. In addition, the related art generally adopts a method of hydrogen ion implantation on the back side of an N-type substrate with a lower doping concentration, and forms a substrate portion with a higher doping concentration on the back side of the N-type substrate, so that the substrate portion with a lower doping concentration is used as a drift region, and the substrate portion with a higher doping concentration is used as a first buffer layer. However, the cost of the hydrogen ion implantation method is relatively high. The embodiment of the present invention adopts a deposition method to form at least one layer of N-type drift region with a lower doping concentration on the front side of an N-type substrate with a higher doping concentration, so that the N-type substrate is used as the first buffer layer, which can effectively reduce the preparation cost of the FS-IGBT power device.

[0059] S130 , performing ion implantation on the back side of the N-type substrate 10 to form an N-type buffer layer 30 ; wherein the resistivity of the N-type buffer layer 30 is smaller than the resistivity of the N-type substrate 10 .

[0060] Exemplarily, on the surface of one side of the N-type substrate away from the N-type drift region, i.e., the back side, an ion implantation method is used to form an N-type buffer layer from the back side of the N-type substrate to the inside, i.e., the N-type buffer layer is formed by ion implantation of part of the N-type substrate. During the ion implantation process, by increasing the doping concentration on the back side of the N-type substrate, the resistivity of the formed N-type buffer layer is lower than the resistivity of the N-type substrate. In this way, the resistivity of the N-type buffer layer is the lowest, and the FS-IGBT power device structure with gradually increasing resistivity along the direction from the N-type buffer layer to the N-type drift region can be obtained. Therefore, due to the N-type drift region with a higher resistivity, it is beneficial to improve the switching speed of the FS-IGBT power device and reduce the switching loss. And from the N-type drift region to the N-type buffer layer, the resistivity gradually decreases, i.e., the variation amplitude of the generated electric field is small, wherein there is an N-type substrate with a lower resistivity, which is beneficial to reduce the switching oscillation of the FS-IGBT power device.

[0061] S140 , performing ion implantation on the back side of the N-type buffer layer 30 to form a P-type collector 40 .

[0062] Exemplarily, by ion implanting the surface of the N-type buffer layer away from the N-type substrate, that is, the back side of the N-type buffer layer, a P-type collector with a smaller thickness on one side can be formed on the back side of the N-type buffer layer. Compared with the related art, when a P-type collector is prepared on the back side of the P-type substrate using a P-type substrate, it is necessary to thin the back side of the P-type substrate to a certain extent to obtain the P-type collector. However, relying on the current thinning process, it is still impossible to achieve the high thinning accuracy required for use as a collector. Therefore, in the related art, the P-type substrate with a relatively large thickness after thinning is used as a P-type collector, which will result in a large switching loss of the FS-IGBT power device. In the embodiment of the present invention, an N-type substrate is used, and by ion implanting the N-type buffer layer on the back side of the N-type substrate, a P-type collector with a smaller thickness can be formed in the N-type buffer layer, thereby effectively reducing the saturation voltage drop and switching loss of the FS-IGBT power device.

[0063] S150 , forming an IGBT functional structure 50 on a side of the N-type drift region 20 away from the N-type substrate 10 ; wherein the IGBT functional structure 50 includes at least one trench gate structure 51 , and the bottom of the trench gate structure 51 is embedded in the N-type drift region 20 .

[0064] For example, in an embodiment of the present invention, a trench gate structure is provided as the gate of the FS-IGBT power device, thereby reducing the on-state loss of the FS-IGBT power device without affecting the tail current and the turn-off loss.

[0065] The technical solution of the embodiment of the present invention adopts a silicon wafer with an N-type conductivity type as a substrate, and the resistivity of the N-type substrate is relatively low. At least one layer of N-type drift region is formed on the front of the N-type substrate by a deposition method, and the resistivity of at least one layer of N-type drift region is higher than the resistivity of the N-type substrate, and the resistivity of the N-type substrate and the resistivity of at least one layer of N-type drift region show a trend of gradually increasing. Then, an N-type buffer layer is formed on the back of the N-type substrate by an ion implantation method, and the resistivity of the N-type buffer layer is made smaller than the resistivity of the N-type substrate. A P-type collector is formed by ion implantation on the back of the N-type buffer layer, and an IGBT functional structure including at least one trench gate structure is also formed on the side of the N-type drift region away from the N-type substrate. In this way, the FS-IGBT power device with a drift region whose resistivity changes sequentially using an N-type substrate is advantageous for improving the switching speed of the FS-IGBT power device and reducing the switching loss compared with the prior art that uses a semiconductor substrate with a single resistivity as the drift region. In addition, using an N-type substrate with a lower resistivity as the first buffer layer, and using an N-type buffer layer with a lower resistivity than the N-type substrate as the second buffer layer can reduce the variation of the generated electric field strength, thereby helping to reduce the switching oscillation of the FS-IGBT power device. When forming a P-type collector, the embodiment of the present invention adopts a method of ion implantation on the back of the N-type buffer layer. Compared with the method of using a P-type substrate and thinning the P-type substrate to obtain a P-type collector in the prior art, the P-type collector prepared by the embodiment of the present invention can achieve a smaller thickness, which is helpful to reduce the switching loss of the FS-IGBT power device.

[0066] Optionally, based on the above embodiment, the sum of the thicknesses of the N-type substrate 10 and the N-type drift region 20 ranges from 50 to 130 μm, and the ratio of the thickness of the N-type drift region 20 to the thickness of the N-type substrate 10 is 2.

[0067] Among them, for FS-IGBT power device products with different application voltages, there are certain differences in the thickness of the N-type substrate and the N-type drift region. Exemplarily, for FS-IGBT power device products with an application voltage of 650V, the sum of the thickness of the N-type substrate and the N-type drift region is in the range of 50 to 80μm. For FS-IGBT power device products with an application voltage of 1200V, the sum of the thickness of the N-type substrate and the N-type drift region is in the range of 100 to 130μm. And in the FS-IGBT power device structure, the thickness of the N-type drift region is twice the thickness of the N-type substrate. If two or more layers of N-type drift regions are formed on the front of the N-type substrate, the total thickness of the two or more layers of N-type drift regions is twice the thickness of the N-type substrate.

[0068] Optionally, based on the above embodiments, the resistivity range of the N-type substrate 10 is less than 30Ω·cm, and the resistivity range of the N-type drift region 20 includes 70 to 150Ω·cm.

[0069] Among them, for FS-IGBT power device products with different application voltages, the resistivity of the N-type substrate is the same, that is, an N-type silicon wafer with a resistivity range of less than 30Ω·cm can be used as the substrate of the FS-IGBT power device. However, for FS-IGBT power device products with different application voltages, there are certain differences in the resistivity of the N-type drift region. For example, for FS-IGBT power device products with an application voltage of 650V, the resistivity range of the N-type drift region can be set to 70~120Ω·cm; for FS-IGBT power device products with an application voltage of 1200V, the resistivity range of the N-type drift region can be set to 90~150Ω·cm.

[0070] Optionally, based on the above embodiments, depositing at least one layer of N-type drift region having a resistivity higher than that of the N-type substrate on the front surface of the N-type substrate in step S120 may include the following steps:

[0071] S121 , sequentially depositing semiconductor materials with decreasing doping concentrations on the front surface of the N-type substrate 10 to form at least two layers of N-type drift regions 20 with resistivity higher than that of the N-type substrate 10 and increasing resistivity.

[0072] For example, except Figure 1 In addition to the structure in which a layer of N-type drift region is formed on the front side of the N-type substrate as shown, two or more layers of N-type drift region may also be formed on the front side of the N-type substrate. For the FS-IGBT power device structure provided with two or more layers of N-type drift region, the resistivity of the two or more layers of N-type drift region and the resistivity of the N-type substrate need to show a gradually increasing trend, that is, the resistivity of the N-type substrate is relatively low, and the resistivity of each layer of N-type drift region increases in turn in the direction away from the N-type substrate, so that the N-type drift region with a higher resistivity is conducive to improving the switching speed of the FS-IGBT power device and reducing the switching loss.

[0073] Optionally, based on the above embodiments, the step S130 of performing ion implantation on the back side of the N-type substrate to form an N-type buffer layer specifically includes the following steps:

[0074] S131 , thinning the back side of the N-type substrate 10 , and injecting N-type impurity ions from the back side of the N-type substrate 10 to form an N-type buffer layer 30 .

[0075] For example, to achieve the goal of miniaturization of power devices, before forming an N-type buffer layer, the back side of the N-type substrate is thinned, and then N-type impurity ions are implanted into the back side of the N-type substrate to form an N-type buffer layer. By halving the back side of the N-type substrate, the overall thickness of the power device can be effectively reduced, thereby reducing the saturation voltage drop of the power device and increasing the switching speed.

[0076] Optionally, based on the above embodiments, the thickness range of the N-type buffer layer 30 and the thickness range of the P-type collector 40 both include 0.8-1.2 μm.

[0077] For example, in the embodiment of the present invention, an N-type buffer layer and a P-type collector are formed on the back of an N-type substrate by an ion implantation method, and the ion implantation depth can be precisely controlled with high precision. Therefore, an N-type buffer layer and a P-type collector with a small thickness can be formed, so that the emitter region is transparent, which is beneficial to reduce the saturation voltage drop of the power device.

[0078] Optionally, Figure 3 is a specific flow chart of step S150 in a method for preparing an IGBT device provided by an embodiment of the present invention, Figure 4 FIG. 1 is a schematic diagram of a structure corresponding to the specific steps of step S150 in a method for preparing an IGBT device provided in an embodiment of the present invention. Figure 3 and Figure 4 The step S150 of forming an IGBT functional structure on a side of the N-type drift region away from the N-type substrate specifically includes the following steps:

[0079] S151 , at least one trench 501 is formed by etching from the front side of the N-type drift region 20 toward the inside.

[0080] Exemplarily, at least one trench is formed inwardly from a surface of the N-type drift region away from the N-type substrate, ie, the front surface of the N-type drift region, by exposure and etching, and the at least one trench is arranged at intervals.

[0081] S152 , forming a gate oxide layer 502 on the front surface of the N-type drift region 20 and the inner wall of the trench 501 .

[0082] Exemplarily, a gate oxide layer is deposited on the front side of the N-type drift region, so that a layer of gate oxide layer is formed on the inner wall of the trench.

[0083] S153 , depositing a gate material in the trench 501 to form a gate 503 ; wherein the gate 503 completely fills the trench 501 .

[0084] Exemplarily, a gate material of polysilicon is deposited in each trench so that the gate material fills the trench, thereby forming a trench gate structure, wherein the gate and the trench are insulated by a gate oxide layer.

[0085] S154 , on the surface of the gate oxide layer 502 away from the N-type drift region 20 , ion implantation and diffusion are performed into the N-type drift region 20 to form a P-type base region 60 .

[0086] Exemplarily, an ion implantation and diffusion process is used to implant ions from the front side of the gate oxide layer into the inside of the N-type drift region and diffuse to a certain depth, thereby forming a P-type base region.

[0087] S155 , on the surface of the gate oxide layer 502 away from the P-type base region 60 , ion implantation and diffusion are performed into the P-type base region 60 to form an N-type emitter region 70 .

[0088] Exemplarily, an ion implantation and diffusion process is used to implant ions from the front of the gate oxide layer into the interior of the P-type base region and diffuse to a certain depth to form an N-type emitter region, and the diffusion depth of the N-type emitter region is less than the diffusion depth of the P-type base region.

[0089] S156. An insulating layer 80 and an emitter metal layer 81 are formed on the surface of the gate oxide layer 502 on one side away from the N-type emitter region 70; wherein the P-type base region 60 includes at least one first through hole, and the N-type emitter region 70 includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate 10, and the second through hole is connected to the first through hole in a one-to-one correspondence; the second through holes and the trench gate structure 51 are alternately arranged in the horizontal direction; at least two protrusions 82 are arranged on the side of the emitter metal layer 81 close to the N-type emitter region 70, and each protrusion 82 is filled in the connected second through hole and the first through hole.

[0090] Exemplarily, silicon dioxide is deposited on the front side of the gate oxide layer to form an insulating layer. The position on the insulating layer corresponding to the interval between each two adjacent trench gate structures is exposed and etched, at least one first through hole is formed in the P-type base region, at least one second through hole is formed in the N-type emitter region, and each first through hole is connected to each second through hole in a one-to-one correspondence, so that the protrusions arranged on the back side of the emitter metal layer can be filled in the first through hole and the second through hole, so that both the P-type base region and the N-type emitter region are in ohmic contact with the emitter metal layer.

[0091] Optionally, Figure 5 is a schematic flow chart of another method for preparing an IGBT device provided by an embodiment of the present invention, Figure 6 FIG. 1 is a schematic diagram of the structure of each step in another method for preparing an IGBT device provided by an embodiment of the present invention. Figure 5 and Figure 6 The IGBT device preparation method further comprises the following steps after step S150:

[0092] S160 , depositing a metal material on a side of the P-type collector 40 away from the N-type buffer layer 30 to form a collector metal layer 90 .

[0093] Exemplarily, a metal material is deposited on the back side of the P-type collector to form a collector metal layer, so that the P-type collector and the collector metal layer are in ohmic contact, thereby forming the collector of the FS-IGBT power device.

[0094] The IGBT device preparation method provided in this embodiment forms at least two layers of N-type drift regions with a higher resistivity than the N-type substrate on the front side of the N-type substrate, which is beneficial to improving the switching speed of the FS-IGBT power device and reducing the switching loss. The N-type substrate with a lower resistivity is beneficial to reducing the switching oscillation of the FS-IGBT power device. In addition, the N-type substrate is thinned on the back side and then N-type impurity ions are injected to form an N-type buffer layer with a lower resistivity than the N-type substrate, thereby further reducing the switching oscillation of the FS-IGBT power device.

[0095] The embodiment of the present invention further provides an IGBT device, which is prepared by using the IGBT device preparation method provided by any of the above embodiments. Figure 7 Schematic diagram of the structure of an IGBT device provided by an embodiment of the present invention. Figure 7 As shown, the IGBT device includes: an N-type substrate 10 , at least one N-type drift region 20 , an N-type buffer layer 30 , a P-type collector 40 and an IGBT functional structure 50 .

[0096] The N-type substrate 10 has a relatively low resistivity; at least one layer of N-type drift region 20 is stacked on the front side of the N-type substrate 10; the resistivity of at least one layer of N-type drift region 20 is higher than that of the N-type substrate 10; the N-type buffer layer 30 is disposed on the back side of the N-type substrate 10; wherein the resistivity of the N-type buffer layer 30 is lower than that of the N-type substrate 10; the P-type collector 40 is disposed on the back side of the N-type buffer layer 30; the IGBT functional structure 50 is disposed on the side of the N-type drift region 20 away from the N-type substrate 10; wherein the IGBT functional structure 50 includes at least one trench gate structure 51, and the bottom of the trench gate structure 51 is embedded in the N-type drift region 20.

[0097] Exemplarily, an N-type conductive silicon substrate is used as the substrate of the entire FS-IGBT power device, and at least one layer of N-type drift region 20 is set on the front of the N-type substrate 10, and the resistivity of at least one layer of N-type drift region 20 is higher than the resistivity of the N-type substrate 10. At least one layer of N-type drift region 20 is used as the first drift region of the FS-IGBT power device, and the N-type substrate 10 is used as the second drift region and the first buffer layer of the FS-IGBT power device. Due to the N-type drift region 20 with a higher resistivity of the FS-IGBT power device, it is beneficial to improve the switching speed of the FS-IGBT power device and reduce the switching loss. In addition, the power device has a first drift region and a second drift region with varying doping concentrations, so that there is a transition between the electric field strengths of the electric fields generated by the drift region and the buffer layer, respectively, which reduces the electric field variation amplitude. The use of the N-type substrate 10 with a lower resistivity is beneficial to reducing the switching oscillation of the FS-IGBT power device. An N-type buffer layer 30 is formed on the back of the N-type substrate 10 by ion implantation, and the resistivity of the N-type buffer layer 30 is lower than that of the N-type substrate 10, further reducing the amplitude of the electric field change, which can effectively reduce the switching oscillation of the FS-IGBT power device. A P-type collector 40 is formed on the back of the N-type buffer layer 30 by ion implantation, which can improve the thickness accuracy of the P-type collector 40 and obtain a P-type collector 40 with a smaller thickness, which is beneficial to reducing the saturation voltage drop and switching loss of the FS-IGBT power device.

[0098] The IGBT device provided by the embodiment of the present invention uses an N-type substrate 10 with a low resistivity as the substrate of the power device, and at least one N-type drift region 20 with a resistivity higher than that of the N-type substrate 10 is arranged on the front of the N-type substrate 10, and an N-type buffer layer 30 is arranged on the back of the N-type substrate 10 by ion implantation, and the resistivity of the N-type buffer layer 30 is lower than that of the N-type substrate 10. Since the FS-IGBT power device has an N-type drift region 20 with a high resistivity, it is beneficial to improve the switching speed of the FS-IGBT power device and reduce the switching loss. The power device has a first drift region, a second drift region and a buffer layer with varying doping concentrations, so that the electric field intensity of the electric field generated by the drift region and the buffer layer has a transition, which reduces the variation amplitude of the electric field. The N-type substrate 10 with a low resistivity is beneficial to reducing the switching oscillation of the FS-IGBT power device, and the N-type buffer layer 30 can further reduce the switching oscillation of the device.

[0099] Optionally, Figure 8 FIG. 1 is a schematic diagram of the structure of another IGBT device provided by an embodiment of the present invention. Figure 8As shown, the trench gate structure 51 includes a trench 501 , a gate 503 and a gate oxide layer 502 ; the gate 503 fills the trench 501 , and the gate oxide layer 502 is arranged between the gate 503 and the trench 501 and on a side surface of the N-type drift region 20 away from the N-type substrate 10 .

[0100] The IGBT functional structure 50 also includes a P-type base region 60, an N-type emitter region 70, an insulating layer 80 and an emitter metal layer 81; the P-type base region 60 is arranged on a side of the N-type drift region 20 away from the N-type substrate 10, and the N-type emitter region 70 is arranged on a side of the P-type base region 60 away from the N-type drift region 20; the trench gate structure 51 penetrates the P-type base region 60 and the N-type emitter region 70; the P-type base region 60 includes at least one first through hole, and the N-type emitter region 70 includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate 10, and the second through hole is connected to the first through hole in a one-to-one correspondence; the connected second through holes and the first through holes are alternately arranged with the trench gate structure 51 in the horizontal direction.

[0101] At least two protrusions 82 are disposed on one side of the emitter metal layer 81 close to the N-type emitter region 70 , and each protrusion 82 is filled in the connected second through hole and the first through hole; the insulating layer 80 is disposed between the trench gate structure 51 and the emitter metal layer 81 .

[0102] Exemplarily, a trench gate structure 51 is provided on the front side of the N-type drift region 20 as the gate 503 of the power device, and ion implantation and diffusion are performed on the front side of the N-type drift region 20 to form a P-type base region 60 and an N-type emitter region 70. An insulating layer 80 and an emitter metal layer 81 are provided on the front side of the gate oxide layer 502, and the emitter metal layer 81 is in ohmic contact with the P-type base region 60 and the N-type emitter region 70 through the protrusions 82, respectively.

[0103] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an IGBT device, characterized in that: include: Providing an N-type substrate; The N-type substrate has a relatively low resistivity; Depositing at least one layer of N-type drift region having a resistivity higher than that of the N-type substrate on the front surface of the N-type substrate; Performing ion implantation on the back side of the N-type substrate to form an N-type buffer layer; wherein the resistivity of the N-type buffer layer is less than the resistivity of the N-type substrate; Performing ion implantation on the back side of the N-type buffer layer to form a P-type collector; An IGBT functional structure is formed on a side of the N-type drift region away from the N-type substrate; wherein the IGBT functional structure includes at least one trench gate structure, and the bottom of the trench gate structure is embedded in the N-type drift region; The sum of the thicknesses of the N-type substrate and the N-type drift region is in the range of 50 to 130 μm, and the ratio of the thickness of the N-type drift region to the thickness of the N-type substrate is 2.

2. The method for preparing an IGBT device according to claim 1, characterized in that: The resistivity range of the N-type substrate is less than 30Ω·cm, and the resistivity range of the N-type drift region includes 70 to 150Ω·cm.

3. The method for preparing an IGBT device according to claim 2, characterized in that: The step of depositing at least one layer of N-type drift region having a resistivity higher than that of the N-type substrate on the front side of the N-type substrate comprises: Semiconductor materials with decreasing doping concentrations are sequentially deposited on the front surface of the N-type substrate to form at least two layers of the N-type drift region whose resistivity is higher than that of the N-type substrate and whose resistivity increases gradually.

4. The method for preparing an IGBT device according to claim 1, characterized in that: The step of performing ion implantation on the back side of the N-type substrate to form an N-type buffer layer comprises: The back side of the N-type substrate is thinned, and N-type impurity ions are implanted from the back side of the N-type substrate to form the N-type buffer layer.

5. The method for preparing an IGBT device according to claim 4, characterized in that: The thickness range of the N-type buffer layer and the thickness range of the P-type collector both include 0.8-1.2 μm.

6. The method for preparing an IGBT device according to claim 1, characterized in that: The forming of an IGBT functional structure on a side of the N-type drift region away from the N-type substrate comprises: Etching from the front side of the N-type drift region to the inside to form at least one trench; forming a gate oxide layer on the front surface of the N-type drift region and the inner wall of the trench; Depositing a gate material in the trench to form a gate; wherein the gate fills the trench completely; On a surface of the gate oxide layer away from the N-type drift region, ion implantation and diffusion are performed into the N-type drift region to form a P-type base region; On a surface of the gate oxide layer away from the P-type base region, ion implantation and diffusion are performed into the P-type base region to form an N-type emitter region; Forming an insulating layer and an emitter metal layer on a surface of the gate oxide layer away from the N-type emitter region; Among them, the P-type base region includes at least one first through hole, the N-type emitter region includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate, and the second through hole is connected to the first through hole in a one-to-one correspondence; the second through holes and the trench gate structure are alternately arranged in the horizontal direction; at least two protrusions are arranged on the side of the emitter metal layer close to the N-type emitter region, and each of the protrusions is filled in the connected second through hole and the first through hole.

7. The method for preparing an IGBT device according to claim 1, characterized in that: Also includes: A metal material is deposited on a side of the P-type collector away from the N-type buffer layer to form a collector metal layer.

8. An IGBT device, characterized in that: Prepared by the IGBT device preparation method according to any one of claims 1 to 7; The IGBT device comprises: An N-type substrate having a relatively low resistivity; At least one layer of N-type drift region is stacked on the front side of the N-type substrate; the resistivity of at least one layer of the N-type drift region is higher than the resistivity of the N-type substrate; An N-type buffer layer is disposed on the back side of the N-type substrate; wherein the resistivity of the N-type buffer layer is less than the resistivity of the N-type substrate; A P-type collector electrode disposed on the back side of the N-type buffer layer; The IGBT functional structure is arranged on a side of the N-type drift region away from the N-type substrate; wherein the IGBT functional structure includes at least one trench gate structure, and the bottom of the trench gate structure is embedded in the N-type drift region.

9. The IGBT device according to claim 8, characterized in that: The trench gate structure comprises a trench, a gate and a gate oxide layer; The gate fully fills the trench, and the gate oxide layer is arranged between the gate and the trench and on a surface of a side of the N-type drift region away from the N-type substrate; The IGBT functional structure also includes a P-type base region, an N-type emitter region, an insulating layer and an emitter metal layer; The P-type base region is arranged on a side of the N-type drift region away from the N-type substrate, and the N-type emitter region is arranged on a side of the P-type base region away from the N-type drift region; the trench gate structure penetrates the P-type base region and the N-type emitter region; The P-type base region includes at least one first through hole, the N-type emitter region includes at least one second through hole, the second through hole overlaps with the orthographic projection of the first through hole on the N-type substrate, and the second through hole is connected to the first through hole in a one-to-one correspondence; the connected second through holes and the first through holes are alternately arranged with the trench gate structure in a horizontal direction; At least two protrusions are provided on a side of the emitter metal layer close to the N-type emitter region, and each of the protrusions is filled in the second through hole and the first through hole that are connected; The insulating layer is disposed between the trench gate structure and the emitter metal layer.

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