A MOSFET with a trench gate structure on a GaN substrate and its fabrication method
By forming trench structures and depositing sidewalls and isolation dielectric layers on GaN substrates, the leakage current problem of MOSFETs in high-voltage applications is solved, achieving higher switching speeds and power densities, simplifying the process flow and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-29
- Publication Date
- 2026-04-03
AI Technical Summary
Existing trench MOSFETs have large leakage current in high-voltage applications, which affects their switching speed and power density.
By employing a GaN substrate, a double dielectric layer between the dual gate structure, and a sidewall structure between the gate and the source/drain, leakage current is reduced by forming a trench structure on the GaN epitaxial layer and depositing sidewalls and isolation dielectric layers on the inner wall.
It improves the switching speed and power density of MOSFETs, simplifies the process flow, reduces chip manufacturing costs, and increases production efficiency.
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Figure CN116469767B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics technology, and more particularly to a MOSFET with a trench gate structure on a GaN substrate and its fabrication method. Background Technology
[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a commonly used semiconductor device used for switching and amplification operations in electronic circuits. The basic structure of a MOSFET includes three electrodes: a source, a drain, and a gate. The gate and source are isolated and covered by a layer of oxide. When no voltage is applied to the gate, the oxide layer between the gate and source prevents electrons from flowing from the drain, thus the MOSFET is in the off state. At this time, no current flows between the drain and source.
[0003] When a positive voltage is applied to the gate, an electric field is formed in the oxide layer beneath the gate. This field attracts electrons from the drain towards the gate, creating a conduction channel. Once this channel is formed, electrons from the drain can flow through it to the source, turning the MOSFET on. The on-state of the MOSFET can be adjusted by the gate voltage; therefore, MOSFETs can be used for signal amplification. When the input signal voltage changes, the gate voltage also changes, thus adjusting the MOSFET's conduction level and achieving signal amplification.
[0004] To achieve higher voltage withstand capability and lower leakage current, the industry has developed trench MOSFETs. These MOSFETs employ a different structure than conventional MOSFETs, with one or more trenches between the source and drain electrodes, forming a floating trench structure. This allows for higher voltage withstand capability and lower leakage current. However, since trench MOSFETs are typically used in high-voltage applications, leakage current remains a concern. Summary of the Invention
[0005] The purpose of this invention is to provide a MOSFET with a trench gate structure on a GaN substrate and its fabrication method. By employing a GaN substrate, a double dielectric layer between the dual gate structure, and a sidewall structure between the gate and the source / drain, the leakage current of the MOSFET can be effectively reduced, thereby enabling the MOSFET with this structure to have higher switching speed and power density than conventional MOSFETs. The process steps are simple, especially in that it simultaneously forms the sidewall structure on the inner wall of the trench structure, the isolation dielectric layer on the second insulating dielectric layer, and the surface preparation layer of the GaN epitaxial layers on both sides of the trench structure, shortening the process cycle, reducing chip manufacturing costs, and improving production efficiency.
[0006] Therefore, in a first aspect, embodiments of the present invention provide a method for fabricating a MOSFET with a trench gate structure on a GaN substrate, comprising:
[0007] Prepare a GaN epitaxial layer on a GaN substrate;
[0008] Selective etching is performed on the GaN epitaxial layer to form a trench structure;
[0009] A first insulating dielectric layer is deposited; the first insulating dielectric layer is a composite dielectric layer.
[0010] A first metal gate is grown on a first insulating dielectric layer in the trench structure; the height of the first metal gate is less than the depth of the trench structure.
[0011] A second insulating dielectric layer is grown on the first metal gate; the total height of the first metal gate and the second insulating dielectric layer is less than the depth of the trench structure.
[0012] Selective etching is performed to remove the second insulating dielectric layer in the area excluding the area above the first metal gate and the first insulating dielectric layer in the area excluding the area around the first metal gate.
[0013] Silica deposition is performed to deposit a sidewall structure on the inner wall of the trench structure, while an isolation dielectric layer is deposited on the second insulating dielectric layer, and an ion implantation surface preparation layer is formed on the GaN epitaxial layers on both sides of the trench structure.
[0014] A second metal gate is grown on the isolation dielectric layer;
[0015] Source and drain regions are formed on the GaN epitaxial layers on both sides of the trench structure by ion implantation. The source and drain regions respectively include a first doped region and a second doped region, and the second doped region is formed on the first doped region. The doping type of the second doped region is different from that of the first doped region.
[0016] Contact electrodes are fabricated in the source and drain regions, and a gate electrode is fabricated to connect to the second metal gate.
[0017] A surface passivation layer is prepared, wherein the contact electrode and the gate electrode are exposed on the surface passivation layer.
[0018] Preferably, the first insulating dielectric layer comprises a silicon oxide layer and a silicon nitride layer.
[0019] More preferably, the structure of the first insulating dielectric layer is a silicon dioxide layer / silicon nitride layer / silicon dioxide layer.
[0020] Preferably, the selective etching method for forming the trench structure includes:
[0021] A high-frequency plasma etching machine is used, with photoresist as a mask for selective etching, sulfur hexafluoride and oxygen as process gases, and Ar gas as the plasma bombardment gas. The trench structure is etched under a high-frequency power of 100-200W and a radio frequency power of 5-10W, and a process pressure of 300-400mTorr.
[0022] Preferably, the horizontal position of the upper surface of the first metal gate is lower than the horizontal position of the lower surface of the first doped region.
[0023] Preferably, the horizontal position of the lower surface of the second metal gate is not higher than the horizontal position of the lower surface of the second doped region.
[0024] In a second aspect, embodiments of the present invention provide a MOSFET with a trench gate structure on a GaN substrate prepared by the method described in the first aspect above.
[0025] The MOSFET fabrication method with a trench gate structure on a GaN substrate provided in this invention effectively reduces the leakage current of the MOSFET by employing a GaN substrate, a double dielectric layer between the dual gate structure, and a sidewall structure between the gate and the source / drain. This results in a MOSFET with higher switching speed and power density than conventional MOSFETs. The process steps are simple, especially in that it simultaneously forms the sidewall structure on the inner wall of the trench structure, the isolation dielectric layer on the second insulating dielectric layer, and the surface preparation layer of the GaN epitaxial layers on both sides of the trench structure. This shortens the process cycle, reduces chip manufacturing costs, and improves production efficiency. Attached Figure Description
[0026] Figure 1 This is a flowchart of the MOSFET fabrication method with a trench gate structure on a GaN substrate proposed in this invention;
[0027] Figure 2 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 1 ;
[0028] Figure 3 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 2 ;
[0029] Figure 4 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 3 ;
[0030] Figure 5 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 4 ;
[0031] Figure 6 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 5 ;
[0032] Figure 7 This is a schematic diagram of the MOSFET fabrication process using the trench gate structure on a GaN substrate proposed in this invention. Figure 6 ;
[0033] Figure 8 This is a schematic diagram of the MOSFET with a trench gate structure on a GaN substrate proposed in this invention. Detailed Implementation
[0034] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0035] This invention provides a method for fabricating a MOSFET with a trench gate structure on a GaN substrate, the main steps of which are as follows: Figure 1 As shown, the structural schematic diagram during the preparation process is as follows: Figure 2-6 As shown in the accompanying drawings, the fabrication method of a MOSFET with a trench gate structure on a GaN substrate according to an embodiment of the present invention will be described below with reference to the accompanying drawings.
[0036] First, it should be noted that photolithography and etching may be involved in each of the following steps. For example, in step 104, the first metal gate is grown on the first insulating dielectric layer in the trench structure. The specific process involves growing Al metal on the entire wafer, and then removing the metal from locations other than the first insulating dielectric layer through photolithography and etching, thereby obtaining the first metal gate grown on the first insulating dielectric layer in the trench structure. This type of operation is a conventional process, and describing it in detail would be very cumbersome. Those skilled in the art can understand how to implement the process based on "growing the first metal gate on the first insulating dielectric layer in the trench structure" without any creative effort. Therefore, conventional processes will not be described in detail.
[0037] Step 101: Prepare a GaN epitaxial layer on a GaN substrate;
[0038] This invention employs an epitaxial layer of GaN material grown on a GaN substrate. By utilizing the high electron mobility and high breakdown field strength of the GaN crystal structure, the MOSFET on the GaN substrate exhibits better performance in high-frequency and high-power applications. At the same time, the thermal conductivity of GaN material is more than 3 times higher than that of silicon material, which gives the MOSFET on the GaN substrate better heat dissipation performance, allowing it to operate at higher temperatures and thus achieve higher power density.
[0039] In actual product design and fabrication, the doping type and concentration of epitaxial GaN depend on the specific device design and process requirements. P-type or n-type doping can be used to achieve the desired electrical properties. The doping concentration range for n-type GaN can be as low as 10⁻⁶. 16 / cm 3 Up to 10 19 / cm 3 Between these ranges, the doping concentration of p-type GaN can be in the range of 10. 17 / cm 3 Up to 10 20 / cm 3 The optimal doping concentration is between 0 and 1. Excessive doping concentration may degrade the conductivity of the GaN epitaxial layer, while insufficient doping concentration may lead to inadequate device performance. Therefore, when fabricating MOSFETs on GaN substrates, those skilled in the art need to select an appropriate doping concentration based on specific application requirements and device design specifications.
[0040] Step 102: Selective etching is performed on the GaN epitaxial layer to form a trench structure;
[0041] GaN etching can be mainly performed using two methods:
[0042] One method is dry etching, which introduces chemical vapors such as oxidants and fluorinators into the reaction chamber and excites plasma through electromagnetic radiation or high frequency, causing it to react with the GaN surface to achieve etching. The other method is wet etching, which is slower and has lower precision and repeatability. Therefore, the dry etching method is used in the actual implementation of this invention.
[0043] The following is a dry etching procedure that can be specifically used in the implementation of this invention:
[0044] A high-frequency plasma etching machine is employed, using photoresist as a mask for selective etching. Sulfur hexafluoride (SF6) and oxygen are used as process gases, while Ar gas is used as the plasma bombardment gas. Gas flow rates: SF6 flow rate is 30-50 SCCM, oxygen flow rate is 5-10 SCCM, and Ar flow rate is 50-100 SCCM. Initial pressure is 50-100 mTorr, and etching pressure is 300-400 mTorr. High-frequency power is 100-200 W, and RF power is 5-10 W. The etching time can be adjusted according to the actual etching depth required.
[0045] The resulting trench structure is as follows Figure 2 As shown.
[0046] Step 103: Deposit the first insulating dielectric layer;
[0047] The first insulating dielectric layer used in this invention is a composite dielectric layer, and its specific structure is a silicon dioxide layer / silicon nitride layer / silicon dioxide layer.
[0048] Using a silicon dioxide layer / silicon nitride layer / silicon dioxide layer as the insulating dielectric layer of the trench structure of a MOSFET with a trench gate structure has two advantages. First, silicon nitride has excellent insulation properties, which reduces the leakage current of the device and improves its performance and reliability. Second, silicon nitride has a high breakdown voltage, which can effectively improve the breakdown voltage of the MOSFET with a trench gate structure, thereby increasing the operating stability and reliability of the device.
[0049] Step 104: Grow a first metal gate on the first insulating dielectric layer in the trench structure;
[0050] The height of the first metal gate grown is less than the depth of the trench structure. Preferably, an Al gate is used.
[0051] After step 104 is completed, the resulting structure is as follows: Figure 3 As shown.
[0052] Step 105: Grow a second insulating dielectric layer on the first metal gate;
[0053] The second insulating dielectric layer can be made of silicon oxide, and more preferably, a composite structure of silicon nitride and silicon dioxide layers can be used. The total height of the first metal gate and the second insulating dielectric layer is less than the depth of the trench structure. For example... Figure 4 As shown.
[0054] The thickness of the second insulating dielectric layer can be determined according to the process and device performance requirements.
[0055] In a dual-gate MOSFET, this insulating layer effectively isolates the charge between the two gates, preventing mutual interference. It also serves as a control channel, enabling the regulation and optimization of the MOSFET's electrical performance. By appropriately setting the thickness of the insulating layer, gate capacitance can be effectively reduced, thereby improving the MOSFET's operating speed and power.
[0056] The specific process steps adopted in this invention are as follows:
[0057] The silicon nitride layer was deposited using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method, depositing a silicon nitride thin film with a thickness of about 20 nm on the GaN surface to protect the GaN surface.
[0058] The silicon dioxide layer was also deposited using the PECVD method, where a silicon oxide (SiO2) insulating layer with a thickness of about 100 nm was deposited on the silicon nitride surface to isolate the charge between the two Al gates.
[0059] The oxide layer is then subjected to annealing, which involves heat treatment at a temperature of around 800°C for about 30 minutes. This process is used to improve the stability of the oxide and reduce its charge.
[0060] Step 106: Perform selective etching to remove the second insulating dielectric layer in the area excluding the area above the first metal gate and the first insulating dielectric layer in the area excluding the area around the first metal gate.
[0061] A masking layer is formed by photolithography. The areas of the first and second insulating dielectric layers not covered by the masking layer are etched away, leaving only the first insulating dielectric layer around the first metal gate within the trench and the second insulating dielectric layer above the first metal gate. For example... Figure 5 As shown.
[0062] Step 107: Perform silica deposition, deposit sidewall structures on the inner wall of the trench structure, deposit an isolation dielectric layer on the second insulating dielectric layer, and simultaneously form an ion implantation surface preparation layer on the GaN epitaxial layers on both sides of the trench structure.
[0063] In this step, silica deposition is performed, thereby solving three technical problems through this process.
[0064] First, a sidewall structure is deposited on the inner wall of the trench structure. This sidewall structure is used to fill the first insulating dielectric layer at the upper part of the trench structure that may be lost during the upper etching. The sidewall structure fills the insulating layer between the gate and the GaN epitaxial layer to prevent the subsequently fabricated second metal gate from short-circuiting with the epitaxial layer.
[0065] Secondly, an isolation dielectric layer is formed on the second insulating dielectric layer. This added thin isolation dielectric layer enables the MOSFET to be used better in high-voltage applications and reduces leakage current.
[0066] Finally, this process step also simultaneously forms an ion implantation surface preparation layer on the GaN epitaxial layers on both sides of the trench structure. During implantation, the high-speed bombardment of the chip surface by ions can cause damage, but the surface oxide layer can provide protection. Furthermore, the dosage of implanted ions needs to be strictly controlled, and the surface oxide layer can limit the penetration depth of the ions, thereby controlling the implantation dosage and ensuring the accuracy and repeatability of the implantation.
[0067] Step 108: Grow a second metal gate on the isolation dielectric layer;
[0068] Get as Figure 6 The structure shown.
[0069] Step 109: Source and drain regions are formed on the GaN epitaxial layers on both sides of the trench structure by ion implantation;
[0070] The source and drain regions each include a first doped region and a second doped region, with the second doped region formed on top of the first doped region. The second doped region and the first doped region have different doping types: one is n-type, and the other is p-type. For example... Figure 7 As shown.
[0071] Step 110: Prepare contact electrodes in the source and drain regions, and prepare a gate electrode to connect to the second metal gate.
[0072] Step 111: Prepare a surface passivation layer, exposing the contact electrode and the gate electrode on the surface passivation layer.
[0073] The final structure of the MOSFET with trench gate on the GaN substrate is as follows: Figure 8 As shown.
[0074] The MOSFET fabrication method with a trench gate structure on a GaN substrate provided in this invention effectively reduces the leakage current of the MOSFET by employing a GaN substrate, a double dielectric layer between the dual gate structure, and a sidewall structure between the gate and the source / drain. This results in a MOSFET with higher switching speed and power density than conventional MOSFETs. The process steps are simple, especially in that it simultaneously forms the sidewall structure on the inner wall of the trench structure, the isolation dielectric layer on the second insulating dielectric layer, and the surface preparation layer of the GaN epitaxial layers on both sides of the trench structure. This shortens the process cycle, reduces chip manufacturing costs, and improves production efficiency.
[0075] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for fabricating a MOSFET with a trench gate structure on a GaN substrate, characterized in that, The preparation method includes: Prepare a GaN epitaxial layer on a GaN substrate; Selective etching is performed on the GaN epitaxial layer to form a trench structure; A first insulating dielectric layer is deposited; the first insulating dielectric layer is a composite dielectric layer, including a silicon oxide layer and a silicon nitride layer; the structure of the first insulating dielectric layer is a silicon dioxide layer / silicon nitride layer / silicon dioxide layer; A first metal gate is grown on a first insulating dielectric layer in the trench structure; the height of the first metal gate is less than the depth of the trench structure. A second insulating dielectric layer is grown on the first metal gate; the total height of the first metal gate and the second insulating dielectric layer is less than the depth of the trench structure. Selective etching is performed to remove the second insulating dielectric layer in the area excluding the area above the first metal gate and the first insulating dielectric layer in the area excluding the area around the first metal gate. Silica deposition is performed to deposit a sidewall structure on the inner wall of the trench structure, while an isolation dielectric layer is deposited on the second insulating dielectric layer, and an ion implantation surface preparation layer is formed on the GaN epitaxial layers on both sides of the trench structure, thereby obtaining the above three structures simultaneously through a single deposition process step. A second metal gate is grown on the isolation dielectric layer; Source and drain regions are formed on the GaN epitaxial layers on both sides of the trench structure by ion implantation. The source and drain regions respectively include a first doped region and a second doped region, with the second doped region formed on top of the first doped region. The doping type of the second doped region is different from that of the first doped region. The horizontal position of the upper surface of the first metal gate is lower than the horizontal position of the lower surface of the first doped region. The horizontal position of the lower surface of the second metal gate is not higher than the horizontal position of the lower surface of the second doped region. Contact electrodes are fabricated in the source and drain regions, and a gate electrode is fabricated to connect to the second metal gate. A surface passivation layer is prepared, wherein the contact electrode and the gate electrode are exposed on the surface passivation layer.
2. The method for fabricating a MOSFET with a trench gate structure on a GaN substrate according to claim 1, characterized in that, The selective etching method for forming trench structures includes: A high-frequency plasma etching machine is used, with photoresist as a mask for selective etching, sulfur hexafluoride and oxygen as process gases, and Ar gas as the plasma bombardment gas. The trench structure is etched under a high-frequency power of 100-200W and a radio frequency power of 5-10W, and a process pressure of 300-400mTorr.
3. A MOSFET with a trench gate structure on a GaN substrate, prepared by the MOSFET preparation method according to claim 1 or 2.
Citation Information
Patent Citations
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