Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The active region is positioned in the substrate and extends along a first direction; the gate structure is located on the surface of the substrate and crosses the active region along a second direction, and the second direction is orthogonal to the first direction; the trench isolation structure is located in the substrate and surrounds the active region, grooves are formed in the edges of the two sides, making contact with the active region, of the trench isolation structure, and the grooves are located below the gate structure; the groove is filled with the wide bandgap semiconductor material layer, the wide bandgap semiconductor material layer is in contact with the edge of the active region, the top of the wide bandgap semiconductor material layer is in contact with the bottom of the gate structure, and the bandgap width of the wide bandgap semiconductor material layer is larger than that of the substrate. The performance of the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] With the rapid development of VLSI technology, the size of MOS (Metal Oxide Semiconductor) transistors is constantly decreasing. As semiconductor manufacturing processes enter the deep submicron stage, the size of CMOS transistors needs to be further reduced to achieve higher density and higher performance applications. Therefore, the isolation process between CMOS transistors is becoming increasingly important. Current semiconductor manufacturing processes use shallow trench isolation (STI) technology to isolate different CMOS transistors. Shallow trench isolation is used to define the active area (AA) of the CMOS.

[0003] As MOS transistors are miniaturized, more complex physical effects often become apparent. The reduction in channel length is called the "short channel effect," which includes DIBL (Drain Induced Barrier Lowering), source-drain punch-through, and so on. The same phenomenon exists in the channel width, which is generally called NWE (Narrow Width Effect).

[0004] When the channel width is large, the impact of the channel edge on overall performance is small and can be ignored. However, as channel lengths entered the submicron era, channel widths shortened considerably, making the NWE (Narrow Width Effect) significant. The main impact of NWE on devices is on the threshold voltage. Historically, in early devices based on LOCOS (Local Oxidation of Silicon) technology, NWE caused an increase in threshold voltage; however, after the advent of STI (Single Infrared Isolation) technology, NWE actually caused a decrease in threshold voltage. Because this effect is opposite to the previous one, it is also known as INWE (Inverse Narrow Width Effect). The mechanism and impact of INWE are as follows: Laterally restricted depletion region: When the channel width W is comparable to the depletion layer width xd, the expansion of the lateral depletion region is physically restricted, resulting in a reduction in total depletion charge; Three-dimensional electric field distribution: Under extremely narrow channels, the longitudinal component of the gate electric field is enhanced, and the strong gate control capability in the edge region reduces the voltage required to form the inversion layer; Quantum effects (minor factor): At the nanoscale, the transverse confinement of charge carriers leads to energy level quantization, which may slightly affect the threshold voltage, but the effect is usually small.

[0005] Therefore, the key is to solve the short-channel effect after miniaturization of MOS transistors in a low-cost and efficient manner. Summary of the Invention

[0006] In view of this, this application aims to provide a semiconductor device and its fabrication method to solve the short-channel effect after miniaturization of MOS transistors.

[0007] This application provides a semiconductor device, including: Substrate; The active region is located in the substrate and extends along a first direction; A gate structure is located on the surface of the substrate and spans the active region along a second direction, which is orthogonal to the first direction; A trench isolation structure is located in the substrate and surrounds the active region. The two sides of the trench isolation structure that are in contact with the active region are provided with grooves, and the grooves are located below the gate structure. A wide bandgap semiconductor material layer is filled in the groove and contacts the edge of the active region. The top of the wide bandgap semiconductor material layer contacts the bottom of the gate structure. The bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate.

[0008] Optionally, the wide bandgap semiconductor material layer includes gallium nitride or silicon carbide, and the substrate material includes silicon; And / or, the wide bandgap of the wide bandgap semiconductor material layer is greater than 3 eV.

[0009] Optionally, the distance between the farthest ends of the grooves on both sides of the active region along the second direction is less than the length of the gate structure along the second direction.

[0010] Optionally, the length of the groove along the first direction is less than or equal to the width of the gate structure along the first direction.

[0011] Optionally, the top wall of the wide bandgap semiconductor material layer is flush with the edge surface of the active region under the gate structure.

[0012] Optionally, the depth of the groove is less than the depth of the trench isolation structure.

[0013] Based on another aspect of this application, a method for fabricating a semiconductor device is also provided, comprising: A substrate is provided in which a trench isolation structure is formed, the trench isolation structure defining an active region extending along a first direction; A patterned mask layer is formed on the substrate, the patterned mask layer having a first opening that spans the active region along a second direction, exposing a portion of the active region and the corresponding trench isolation structures on both sides; The trench isolation structure is etched to form a groove in the trench isolation structure, the groove exposing a portion of the edge of the active region; Remove the patterned mask layer and fill the groove with a wide bandgap semiconductor material layer that contacts the edge of the active region. The bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate. A gate structure is formed on the substrate, the gate structure extending along the second direction and covering the wide bandgap semiconductor material layer, a portion of the active region and a portion of the trench isolation structure.

[0014] Optionally, the patterned mask layer is formed on the substrate using a gate photomask and a first type of photoresist layer, the patterned mask layer having a first critical dimension along the second direction.

[0015] Optionally, the gate structure is formed on the substrate using the gate photomask and a second type of photoresist layer, wherein the second critical dimension of the gate structure along the second direction is larger than the first critical dimension, and the second type of photoresist layer is of the opposite type to the first type of photoresist layer.

[0016] Optionally, the step of filling the groove with a wide bandgap semiconductor material layer further includes: A wide bandgap semiconductor material layer is formed by metal-organic chemical vapor deposition to cover the trench isolation structure and the surface of the active region, and to fill the trench. Using the surface of the trench isolation structure as a grinding stop layer, a grinding process is performed on the wide bandgap semiconductor material layer to expose the trench isolation structure and the surface of the active region.

[0017] In summary, the unexpected effect of this application is that by filling the groove at the edge of the channel region (active region under the gate structure) with a wide bandgap semiconductor material layer, and making the wide bandgap semiconductor material layer contact the edge of the channel region, the wide bandgap characteristics of the wide bandgap semiconductor material layer can be utilized to increase the ionization energy threshold and enhance the critical electric field strength, thereby reducing the leakage current at the edge of the channel region and increasing the breakdown electric field at the edge of the channel region, thus improving product reliability. Furthermore, by forming the wide bandgap semiconductor material layer before forming the gate structure, the gate structure can protect the contact edge between the wide bandgap semiconductor material layer and the channel region, preventing the channel region edge from becoming concave, thereby further reducing leakage current. In addition, the aforementioned groove and gate structure can be formed by patterning using a multiplexed gate photomask, allowing the fabrication of the aforementioned semiconductor device with superior performance without adding a photomask. Attached Figure Description

[0018] Figure 1 This is a top view of a transistor.

[0019] Figure 2 for Figure 1 3D simulation diagram of the transistor.

[0020] Figure 3 for Figure 2 Simulation diagram of cross-sectional current density along the red line.

[0021] Figure 4 This is a top view of a transistor.

[0022] Figure 5 for Figure 4 Simulation diagram of current density and potential distribution in the active region under the first rounded corner.

[0023] Figure 6 for Figure 4 Simulation diagram of current density and potential distribution in the active region under the second rounded corner.

[0024] Figure 7 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application.

[0025] Figure 8 This is a schematic diagram of forming isolation trenches in a substrate, provided as an embodiment of this application.

[0026] Figure 9 This is a schematic diagram of a trench isolation structure formed in a substrate, provided as an embodiment of this application.

[0027] Figure 10 This is a schematic diagram of forming a second patterned mask layer on a substrate, provided as an embodiment of this application.

[0028] Figure 11This is a schematic diagram of a groove formed in a trench isolation structure according to an embodiment of this application.

[0029] Figure 12 This is a schematic diagram illustrating the formation of a wide bandgap semiconductor material layer, provided in an embodiment of this application.

[0030] Figure 13 A comparison of some indicators of gallium nitride and silicon provided in the embodiments of this application.

[0031] Figure 14 A schematic diagram of grinding to retain a wide bandgap semiconductor material layer in a groove, provided for an embodiment of this application.

[0032] Figure 15 This is a schematic diagram of forming a gate dielectric material and a gate conductive material on a substrate, as provided in an embodiment of this application.

[0033] Figure 16 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application.

[0034] Figure 17 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application.

[0035] The attached figures are labeled as follows: 100 - Substrate; 110 - First patterned mask layer; 120 - Isolation trench; 130 - Active region; 140 - Trench isolation structure; 210 - Second patterned mask layer; 211 - First opening; 220 - Groove; 230 - Wide bandgap semiconductor material layer; 310 - Gate dielectric material; 320 - Gate conductive material; 300 - Gate structure; CD1 - First critical dimension; CD2 - Second critical dimension; X - First direction; Y - Second direction. Detailed Implementation

[0036] Figure 1 This is a top view of a transistor. Figure 2 for Figure 1 3D simulation diagram of the transistor in the image. Figure 3 for Figure 2 Simulation diagram of current density at the cross-section along the red line (Cut line). Figure 2 and Figure 3 In this context, Abs (Total Current Density) represents the absolute value of the current density. Figure 3 The horizontal axis represents the width, and the vertical axis represents the depth. For example... Figures 1-3 As shown, Figure 1 One red line is located at the edge of the active region (AA) (the boundary between AA and STI), and the other red line is located in the middle of the active region (the center of AA). For example... Figures 1-3As shown, the electric field is concentrated at the edge of the narrow channel, which weakens the gate control capability and significantly increases the leakage current at the edge. Under high electric field, the charge carriers obtain enough energy to inject into the gate oxide layer, resulting in device threshold drift or decreased reliability. This phenomenon is more obvious in the NMOS region. In order to maintain device performance, the threshold voltage needs to be reduced to compensate for leakage current.

[0037] Figure 4 This is a top view of a transistor. Figure 5 for Figure 4 Simulation diagram of current density and potential distribution in the active region under the first fillet. Figure 5 and Figure 6 In the figure, Abs (Total Current Density) is the absolute value of the current density, the horizontal axis is the width, and the vertical axis is the depth. Figure 6 for Figure 4 Simulation diagram of current density and potential distribution in the active region under the second rounded corner. In actual manufacturing processes, the edges of the active region are rounded to reduce the electric field strength at the edges, thereby reducing leakage current. Figures 5-6 As shown, Figure 5 The first fillet ratio in Figure 6 The second rounded corner is larger (smoother), making Figure 5 Ioff relative to the middle transistor Figure 6 The Ioff of the transistor is smaller under the same conditions. However, as device size becomes smaller, there are significant limitations to the methods of rounding the edges of the active region. Excessive rounding can lead to a decrease in CD, which affects device performance.

[0038] In view of this, embodiments of this application provide a semiconductor device and a method for fabricating the same. The semiconductor device includes: a substrate; an active region located in the substrate and extending along a first direction; a gate structure located on the surface of the substrate and spanning the active region along a second direction, the second direction being orthogonal to the first direction; a trench isolation structure located in the substrate and surrounding the active region, wherein grooves are provided on both sides of the trench isolation structure that contact the active region, the grooves being located below the gate structure; and a wide bandgap semiconductor material layer filling the grooves and contacting the edge of the active region, wherein the top of the wide bandgap semiconductor material layer contacts the bottom of the gate structure, and the bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate. An unexpected effect of this application is that by filling the groove at the edge of the channel region (active region under the gate structure) with a wide bandgap semiconductor material layer, making the wide bandgap semiconductor material layer contact the edge of the channel region, the wide bandgap characteristics of the wide bandgap semiconductor material layer can be utilized to increase the ionization energy threshold and enhance the critical electric field strength, thereby reducing the leakage current at the edge of the channel region and increasing the breakdown electric field at the edge of the channel region, thus improving product reliability. Furthermore, by forming the wide bandgap semiconductor material layer before forming the gate structure, the gate structure can protect the contact edge between the wide bandgap semiconductor material layer and the channel region, preventing the channel region edge from becoming concave, thereby further reducing leakage current. In addition, the aforementioned groove and gate structure can be formed separately by patterning using a multiplexed gate photomask, allowing the fabrication of the aforementioned semiconductor device with superior performance without adding a photomask.

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] Figure 7 A flowchart of a method for manufacturing a semiconductor device provided in the embodiments of this application is shown below. Figure 7 As shown, the method for manufacturing a semiconductor device includes: S100: Provide a substrate in which a trench isolation structure is formed, the trench isolation structure defining an active region extending along a first direction; S200: A first patterned mask layer is formed on the substrate. The first patterned mask layer has a first opening that spans the active region along a second direction, exposing a portion of the active region and the corresponding trench isolation structures on both sides. S300: Etch the trench isolation structure to form a groove in the trench isolation structure, the groove exposing a portion of the edge of the active region; S400: Remove the patterned mask layer, fill the groove with a wide bandgap semiconductor material layer that contacts the edge of the active region, and the bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate; S500: A gate structure is formed on the substrate, the gate structure extending along the second direction and covering the wide bandgap semiconductor material layer, a portion of the active region and a portion of the trench isolation structure.

[0041] Figures 8-16 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 8-16 The method for fabricating the semiconductor device provided in this application shall be described in detail.

[0042] First, such as Figures 8-9 As shown, in step S100, a substrate 100 is provided, and a trench isolation structure 140 is formed in the substrate 100. The trench isolation structure 140 defines an active region 130 extending along a first direction X.

[0043] Specifically, the substrate 100 can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), or it can be an organic semiconductor material or other semiconductor materials known in the art.

[0044] like Figure 8 As shown, a first patterned mask layer 110 (e.g., a patterned photoresist layer) can be formed on the surface of the substrate 100, and a dry etching process can be performed to form an isolation trench 120 in the substrate 100. The longitudinal cross-sectional pattern of the isolation trench 120 can be rectangular or inverted trapezoidal (narrower at the top and wider at the bottom), that is, the sidewalls of the isolation trench 120 are at right angles or obtuse angles to the surface of the substrate 100, and the area of ​​the substrate 100 surrounded by the isolation trench 120 can be an active region 130.

[0045] like Figure 9As shown, the first patterned mask layer 110 is removed to form an insulating dielectric layer covering the surface of the substrate 100 and filling the isolation trench 120. The insulating dielectric layer is then planarized using the surface of the substrate 100 as a polishing stop layer, exposing the surface of the substrate 100. The remaining insulating dielectric layer in the isolation trench 120 forms a trench isolation structure 140, which extends from the surface of the substrate 100 into the substrate 100. The trench isolation structure 140 defines an active region 130 extending along a first direction X. In one example, the insulating dielectric layer may be made of silicon oxide and may be formed using a high aspect ratio vapor deposition (HARP) process.

[0046] Next, as Figure 10 As shown, in step S200, a second patterned mask layer 210 is formed on the substrate 100. The second patterned mask layer 210 has a first opening 211. The first opening 211 spans the active region 130 along the second direction Y, exposing a portion of the active region 130 and the corresponding trench isolation structures 140 on both sides.

[0047] A first opening 211 can be formed on the surface of the substrate 100 using a first photomask and a first type of photoresist layer, exposing a portion of the active region 130 and the corresponding trench isolation structures 140 on both sides. The first opening 211 has a rectangular cross-sectional shape. The portion of the active region 130 exposed by the first opening 211 can be the channel region of a transistor or a part of the channel region. The edge of the first opening 211 in the second direction Y (perpendicular to the channel extension direction, i.e., the first direction X) extends beyond the channel region (active region 130) and is located on the trench isolation structure 140, but this side... The edge does not extend beyond the gate structure coverage area of ​​the transistor. The edge of the first opening 211 in the first direction X (along the channel extension direction) is located on the active region 130 and the trench isolation structure 140. This side edge is aligned or substantially aligned with the corresponding edge of the channel region. In other words, the size of the first opening 211 in the second direction Y (the first critical size CD1) is greater than the size of the channel region in the second direction Y but smaller than the size of the gate structure in the second direction Y. The size of the first opening 211 in the first direction X is less than or equal to the size of the channel region in the first direction X.

[0048] In some examples of this application, the first photomask may be a photomask (i.e., a gate photomask) used to form the gate structure of the transistor. The first photomask may include a strip pattern whose size and position on the photomask correspond to (are similar to) the gate structure on the substrate 100. The first photomask and a photoresist layer (a negative photoresist layer) similar to the one used to form the gate structure may be used to form a pattern on the substrate 100 that is opposite to (complementary to) the pattern on the first photomask. That is, the second patterned mask layer 210 exposes part of the active region 130 and part of the trench isolation structure 140 covered by the gate structure. The critical dimension (first critical dimension CD1) of the second patterned mask layer 210 along the second direction Y can be reduced by adjusting one or more of the exposure process, development process and baking process (e.g., increasing the exposure dose, reducing the development time, reducing the baking time). That is, the dimension (first critical dimension CD1) of the first opening 211 along the second direction Y is smaller than the dimension of the gate structure in the second direction Y, but larger than the dimension of the channel region in the second direction Y. It is understandable that, in practice, the critical dimensions of the second patterned mask layer 210 along the first direction X may also be affected by the aforementioned reduction in size, making the size of the first opening 211 along the first direction X slightly smaller than the size of the gate structure in the first direction X.

[0049] Next, as Figure 11 As shown, in step S300, the trench isolation structure 140 is etched to form a groove 220 in the trench isolation structure 140, and the groove 220 exposes the edge of the active region 130.

[0050] Using the aforementioned second patterned mask layer 210, an etching process is performed on the trench isolation structure 140 to remove a portion of the trench isolation structure 140, thereby forming two grooves 220 in the trench isolation structure 140 on both sides of the active region 130. The grooves 220 expose the edge of the channel region (active region 130), i.e., the corner. Depending on the material difference between the trench isolation structure 140 and the active region 130, a wet etching process or a dry etching process with a higher etching selectivity for the active region 130 can be selected to etch the trench isolation structure 140. The etching depth can be less than the depth of the isolation trench 120, and the etching depth can be minimized to reduce or avoid the impact of the etching process on the channel region.

[0051] Next, as Figures 12-14 As shown, in step S400, the second patterned mask layer 210 is removed, and a wide bandgap semiconductor material layer 230 is filled in the groove 220, which is in contact with the edge of the active region 130. The bandgap width of the wide bandgap semiconductor material layer 230 is greater than the bandgap width of the substrate 100.

[0052] Specifically, such as Figure 12As shown, the second patterned mask layer 210 is removed to form a wide bandgap semiconductor material layer 230 covering the surface of the trench isolation structure 140 and the surface of the active region 130, and filling the groove 220. The wide bandgap semiconductor material layer 230 and the substrate 100 are both semiconductor materials that can serve as channels, but the bandgap width of the wide bandgap semiconductor material layer 230 is greater than that of the substrate 100 (substrate material). Utilizing the wide bandgap characteristic, by increasing the ionization energy threshold, enhancing the critical electric field strength, and combining with other related characteristics such as low dielectric constant and high carrier saturation velocity, its breakdown field strength is significantly higher than that of the substrate material. It should be understood that under a strong electric field, charge carriers (electrons or holes) are accelerated and gain kinetic energy. When the kinetic energy exceeds the ionization energy threshold of the material, they will generate new electron-hole pairs by colliding with lattice atoms, triggering avalanche breakdown. A wide bandgap means that electrons need higher energy to jump from the valence band to the conduction band, which means that charge carriers need a higher electric field to accumulate enough energy to trigger breakdown. In other words, a wide bandgap increases the ionization energy threshold and thus increases its breakdown field strength.

[0053] Figure 13 A comparison of some specifications of gallium nitride and silicon provided in embodiments of this application. In some examples, the substrate 100 may be made of silicon, and the wide bandgap semiconductor material layer 230 may include gallium nitride, and may be formed using a metal-organic chemical vapor deposition (MOCVD) process. Figure 13 As shown, gallium nitride (GaN) has a wider bandgap (3.4 eV) than silicon (1.1 eV), giving it advantages such as high voltage resistance, high temperature resistance, strong radiation resistance, and higher device junction temperature. GaN's critical breakdown electric field (3.3 MV / cm) is greater than silicon's (0.3 MV / cm), allowing it to have lower on-resistance due to its smaller size at the same breakdown voltage. GaN's electron saturation velocity (2.5 × 10⁻⁶) is also higher. 7 The electron saturation velocity (cm / s) is greater than that of silicon (1.0 × 10⁻⁶). 7 Gallium nitride (GaN) has a faster electron mobility (2000 cm² / V·s) than silicon (1400 cm² / V·s), which allows it to benefit from the two-dimensional electron gas of the heterojunction, resulting in lower on-resistance and faster switching speed. GaN's thermal conductivity (2.1 W / cm·K) is also greater than silicon's (1.5 W / cm·K), giving it superior heat dissipation for improved power density and reliability. Furthermore, GaN's Baliga factor of merit (BFOM) and Johnson factor of merit (JFM) are significantly better than those of silicon, resulting in superior high-frequency and high-voltage performance compared to silicon.

[0054] In other examples of this application, the substrate 100 may be made of silicon, and the material of the wide bandgap semiconductor material layer 230 is preferably a semiconductor material with a bandgap width greater than 3 eV, such as gallium nitride or silicon carbide. Of course, the material of the wide bandgap semiconductor material layer 230 may also be other III-V compound semiconductors or other semiconductor materials with a large bandgap, such as gallium arsenide (bandgap width of 1.42 eV), indium phosphide (bandgap width of 1.34 eV), aluminum nitride (bandgap width of 6.20 eV), etc. Of course, in practice, other factors such as cost and process difficulty should also be considered to select a suitable semiconductor material with a relatively wide bandgap.

[0055] like Figure 14 As shown, the surface of the trench isolation structure 140 is used as the grinding stop layer, and a grinding process is performed on the wide bandgap semiconductor material layer 230 to expose the surface of the trench isolation structure 140 and the active region 130, so that the remaining wide bandgap semiconductor material layer 230 fills the groove 220. At this time, the surface of the wide bandgap semiconductor material layer 230 can be flush with the surface of the active region 130 and contact the edge (corner) of the active region 130 for electrical connection.

[0056] Next, as Figures 15-16 As shown, in step S500, a gate structure 300 is formed on the substrate 100. The gate structure 300 extends along the second direction Y and covers a wide bandgap semiconductor material layer 230, a portion of the active region 130 and a portion of the trench isolation structure 140.

[0057] Specifically, such as Figure 15 As shown, a gate dielectric material 310 and a gate conductive material 320 are sequentially formed on a substrate 100. The gate dielectric material 310 covers the surface of the trench isolation structure 140, the active region 130, and the wide bandgap semiconductor material layer 230. The gate dielectric material 310 may include silicon oxide, silicon oxynitride, or a high dielectric constant dielectric layer. The gate conductive material 320 covers the surface of the gate dielectric material 310. The gate conductive material 320 may include polysilicon or other conductive materials (e.g., metal materials).

[0058] like Figure 16As shown, a gate structure 300 is formed by patterning the gate dielectric material 310 and the gate conductive material 320, so that the gate structure 300 covers part of the active region 130 (channel region), the wide bandgap semiconductor material layer 230 and part of the trench isolation structure 140 surface. In some examples of this application, similar to the foregoing, the first photomask can be a photomask used to form the gate structure of the transistor (i.e., a gate photomask). The first photomask has a strip pattern similar to the gate structure 300. A third patterned mask layer (e.g., a third patterned photoresist layer) can be formed on the gate conductive material 320 using the first photomask and a positive photoresist layer. The third patterned mask layer covers the gate conductive material 320 corresponding to the gate structure 300. The third patterned mask layer has a second critical dimension CD2, which is larger than the first critical dimension CD1. Then, an etching process is performed to remove the exposed gate conductive material 320 and gate dielectric material 310, and the third patterned mask layer is removed. The remaining gate conductive material 320 and gate dielectric material 310 serve as the gate structure 300, and the gate structure 300 covers the wide bandgap semiconductor material layer 230 on both sides of the channel region.

[0059] In other examples of this application, the photomask used to form the gate structure 300 (i.e., the gate photomask) may also be a second photomask, the pattern on the second photomask being opposite (complementary) to the pattern on the first photomask, and each patterned using a photoresist layer of the opposite type to form the groove 220 (e.g., using a positive photoresist layer) and the gate structure 300 (e.g., using a negative photoresist layer). In this application, by reusing the gate photomask to separately pattern the aforementioned groove 220 and gate structure 300, the aforementioned semiconductor device with superior performance can be manufactured without increasing the number of photomasks.

[0060] This application also provides a semiconductor device. Figure 16 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application. Figure 17 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. (See attached diagram.) Figure 16 and Figure 17 As shown, the semiconductor device provided in this application embodiment includes a substrate 100, an active region 130, a trench isolation structure 140, a gate structure 300, a groove 220, and a wide bandgap semiconductor material layer 230.

[0061] The substrate 100 can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), or it can be an organic semiconductor material or other semiconductor materials known in the art.

[0062] Please continue to refer to Figure 16 and Figure 17 Both the active region 130 and the trench isolation structure 140 are located in the substrate 100. The active region 130 can extend along the first direction X, and the trench isolation structure 140 extends from the surface of the substrate 100 into the substrate 100, and can be, for example, ring-shaped to define the active region 130, that is, the trench isolation structure 140 surrounds the active region 130. The gate structure 300 is located on the surface of the substrate 100 and may include a gate dielectric material 310 and a gate conductive material 320 stacked sequentially. The gate structure 300 extends along the second direction Y and crosses the active region 130, overlapping with the active region 130 to form a channel region in the active region 130. The gate structure 300 covers part of the active region 130 (channel region) and part of the surface of the trench isolation structure 140, that is, both ends of the gate structure 300 extend along the second direction Y to the trench isolation structures 140 on both sides.

[0063] Please continue to refer to Figure 16 and Figure 17The trench isolation structure 140 below the gate structure 300 has grooves 220 on both sides of its edge where it connects to the active region 130. A wide bandgap semiconductor material layer 230 is filled in the grooves 220. The sidewalls of the wide bandgap semiconductor material layer 230 are in contact (electrically connected) with the edge of the active region 130, and the top of the wide bandgap semiconductor material layer 230 is in contact with the bottom of the gate structure 300. The wide bandgap semiconductor material layer 230 and the substrate 100 are both semiconductor materials that can serve as channels, but the bandgap width of the wide bandgap semiconductor material layer 230 is greater than that of the substrate 100 (substrate material). Utilizing the wide bandgap characteristic, by increasing the ionization energy threshold, enhancing the critical electric field strength, and combining with other related characteristics such as low dielectric constant and high carrier saturation velocity, the breakdown field strength is significantly higher than that of the substrate 100 material. This reduces the leakage current at the edge of the active region and increases the breakdown electric field at the edge of the active region 130, thereby improving product reliability. In some examples, the substrate 100 may be made of silicon (with a bandgap of 1.1 eV), and the wide bandgap semiconductor material layer 230 may include gallium nitride (with a bandgap of 3.4 eV). In other examples, the substrate 100 may be made of silicon, and the wide bandgap semiconductor material layer 230 may also be other III-V compound semiconductors or other semiconductor materials with relatively wide bandgap, such as gallium arsenide (with a bandgap of 1.42 eV), indium phosphide (with a bandgap of 1.34 eV), aluminum nitride (with a bandgap of 6.20 eV), etc.

[0064] Please continue to refer to Figure 16 and Figure 17 The distance between the farthest ends of the grooves 220 on both sides of the active region 130 along the second direction Y (first critical dimension CD1) is less than the length of the gate structure 300 along the second direction Y (second critical dimension CD2). The length of the grooves 220 along the first direction X is less than or equal to the width of the gate structure 300 along the first direction X. This ensures that the wide bandgap semiconductor material layer 230 in the grooves 220 is located below the gate structure 300, making the top wall of the wide bandgap semiconductor material layer 230 flush with the edge surface of the active region 130 (i.e., the channel region) under the gate structure 300. This prevents damage to the wide bandgap semiconductor material layer 230 and the edge of the channel region, thus avoiding pitting and further reducing leakage current. Of course, even if damage occurs in subsequent processes such as ion implantation or wet processing, only the edge of the wide bandgap semiconductor material layer 230 away from the channel region will be damaged, while the portion of the wide bandgap semiconductor material layer 230 near the channel region and the edge of the channel region will remain intact.

[0065] In summary, this application provides a semiconductor device and a method for fabricating the same. The semiconductor device includes: a substrate; an active region located in the substrate and extending along a first direction; a gate structure located on the surface of the substrate and spanning the active region along a second direction, the second direction being orthogonal to the first direction; a trench isolation structure located in the substrate and surrounding the active region, wherein grooves are provided on both sides of the trench isolation structure that contact the active region, the grooves being located below the gate structure; and a wide bandgap semiconductor material layer filling the grooves and contacting the edge of the active region, wherein the top of the wide bandgap semiconductor material layer contacts the bottom of the gate structure, and the bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate. An unexpected effect of this application is that by filling the groove at the edge of the channel region (active region under the gate structure) with a wide bandgap semiconductor material layer, making the wide bandgap semiconductor material layer contact the edge of the channel region, the wide bandgap characteristics of the wide bandgap semiconductor material layer can be utilized to increase the ionization energy threshold and enhance the critical electric field strength, thereby reducing the leakage current at the edge of the channel region and increasing the breakdown electric field at the edge of the channel region, thus improving product reliability. Furthermore, by forming the wide bandgap semiconductor material layer before forming the gate structure, the gate structure can protect the contact edge between the wide bandgap semiconductor material layer and the channel region, preventing the channel region edge from becoming concave, thereby further reducing leakage current. In addition, the aforementioned groove and gate structure can be formed separately by patterning using a multiplexed gate photomask, allowing the fabrication of the aforementioned semiconductor device with superior performance without adding a photomask.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0067] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0068] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0069] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The active region is located in the substrate and extends along a first direction; A gate structure is located on the surface of the substrate and spans the active region along a second direction, which is orthogonal to the first direction; A trench isolation structure is located in the substrate and surrounds the active region. The two sides of the trench isolation structure that are in contact with the active region are provided with grooves, and the grooves are located below the gate structure. A wide bandgap semiconductor material layer is filled in the groove and contacts the edge of the active region. The top of the wide bandgap semiconductor material layer contacts the bottom of the gate structure. The bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate.

2. The semiconductor device according to claim 1, characterized in that, The wide bandgap semiconductor material layer includes gallium nitride or silicon carbide, and the substrate material includes silicon. And / or, the wide bandgap of the wide bandgap semiconductor material layer is greater than 3 eV.

3. The semiconductor device according to claim 1, characterized in that, The distance between the farthest ends of the grooves on both sides of the active region along the second direction is less than the length of the gate structure along the second direction.

4. The semiconductor device according to claim 3, characterized in that, The length of the groove along the first direction is less than or equal to the width of the gate structure along the first direction.

5. The semiconductor device according to claim 1, characterized in that, The top wall of the wide bandgap semiconductor material layer is flush with the edge surface of the active region under the gate structure.

6. The semiconductor device according to claim 1, characterized in that, The depth of the groove is less than the depth of the trench isolation structure.

7. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided in which a trench isolation structure is formed, the trench isolation structure defining an active region extending along a first direction; A patterned mask layer is formed on the substrate, the patterned mask layer having a first opening that spans the active region along a second direction, exposing a portion of the active region and the corresponding trench isolation structures on both sides; The trench isolation structure is etched to form a groove in the trench isolation structure, the groove exposing a portion of the edge of the active region; Remove the patterned mask layer and fill the groove with a wide bandgap semiconductor material layer that contacts the edge of the active region. The bandgap width of the wide bandgap semiconductor material layer is greater than the bandgap width of the substrate. A gate structure is formed on the substrate, the gate structure extending along the second direction and covering the wide bandgap semiconductor material layer, a portion of the active region and a portion of the trench isolation structure.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The patterned mask layer is formed on the substrate using a gate photomask and a first type of photoresist layer, the patterned mask layer having a first critical dimension along the second direction.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The gate structure is formed on the substrate using the gate photomask and a second type of photoresist layer, wherein the second critical dimension of the gate structure along the second direction is larger than the first critical dimension, and the second type of photoresist layer is of the opposite type to the first type of photoresist layer.

10. The method for fabricating a semiconductor device according to claim 7, characterized in that, The step of filling the groove with a wide bandgap semiconductor material layer further includes: A wide bandgap semiconductor material layer is formed by metal-organic chemical vapor deposition to cover the trench isolation structure and the surface of the active region, and to fill the trench. Using the surface of the trench isolation structure as a grinding stop layer, a grinding process is performed on the wide bandgap semiconductor material layer to expose the trench isolation structure and the surface of the active region.

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