Multilayer varistor and method of making same

Abstract

A multilayer varistor and a method of manufacturing the same are disclosed. The method of manufacturing the multilayer varistor includes providing an initial multilayer structure, sintering the initial multilayer structure to form a sintered multilayer structure, fabricating the sintered multilayer structure into a multilayer stack structure including an insulating carrier, a plurality of first inner conductive layers disposed in the insulating carrier, and a plurality of second inner conductive layers disposed in the insulating carrier, and the plurality of first inner conductive layers and the plurality of second inner conductive layers are alternately arranged, and forming an outer electrode structure to partially cover the multilayer stack structure, the outer electrode structure including a first outer electrode layer electrically contacting the plurality of first inner conductive layers and a second outer electrode layer electrically contacting the plurality of second inner conductive layers, and the first outer electrode layer and the second outer electrode layer cover a first side end portion and a second side end portion of the multilayer stack structure, respectively.

Description

Technical Field

[0001] This invention relates to a varistor and its manufacturing method, and particularly to a multilayer varistor and its manufacturing method. Background Technology

[0002] A varistor is an electronic component, also known as a voltage-dependent resistor (VDR), whose resistance changes with the applied voltage. It exhibits non-linear characteristics similar to a diode (non-ohmic current-voltage characteristic). However, unlike a diode, it has the same characteristics in both lateral current directions. Traditionally, varistors are constructed by connecting two rectifiers (e.g., copper oxide or germanium oxide rectifiers in anti-parallel configuration). At low voltages, varistors have high resistance, which decreases as the voltage increases. Modern varistors are primarily based on sintered ceramic metal oxide materials, which exhibit directionality only at the microscale. This type is commonly called a metal oxide varistor (MOV). Additionally, varistors can be used as control or compensation components in circuits to provide optimal operating conditions or prevent excessive transient voltages. When used as a protection device, varistors shunt the current generated by excessive voltage from the sensitive component upon triggering. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a multilayer varistor and its manufacturing method in view of the shortcomings of the prior art.

[0004] To address the aforementioned technical problems, one technical solution adopted by the present invention is to provide a method for fabricating a multilayer varistor, comprising: providing an initial multilayer structure; sintering the initial multilayer structure to form a sintered multilayer structure; fabricating the sintered multilayer structure into a multilayer stack structure, the multilayer stack structure including an insulating carrier, a plurality of first inner conductive layers disposed within the insulating carrier, and a plurality of second inner conductive layers disposed within the insulating carrier, wherein the plurality of first inner conductive layers and the plurality of second inner conductive layers are alternately arranged; and forming an external electrode structure to partially cover the multilayer stack structure, the external electrode structure including a first external electrode layer electrically contacting the plurality of first inner conductive layers and a second external electrode layer electrically contacting the plurality of second inner conductive layers, wherein the first external electrode layer and the second external electrode layer respectively cover a first side end and a second side end of the multilayer stack structure. The step of fabricating the sintered multilayer structure into a multilayer stack structure further includes step (A) or step (B). Step (A) includes: immersing the sintered multilayer structure in a first solution containing 0.1% to 4.9% alkali metal for a time between 30 and 120 seconds; removing the sintered multilayer structure from the first solution and then drying it to form a dried multilayer structure; and performing a metal ion diffusion step on the dried multilayer structure at a temperature of 600°C to 800°C. Step (B) includes: immersing the sintered multilayer structure in a second solution comprising a mixed resin containing 0.1% to 4.9% alkali metal ions; removing the sintered multilayer structure from the second solution and then drying it to form a dried multilayer structure; and performing a metal ion diffusion step on the dried multilayer structure at a temperature of 600°C to 800°C.

[0005] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a multilayer varistor, comprising: a multilayer stacked structure and an external electrode structure. The multilayer stacked structure includes an insulating carrier, a plurality of first inner conductive layers disposed within the insulating carrier, and a plurality of second inner conductive layers disposed within the insulating carrier, with the plurality of first inner conductive layers and the plurality of second inner conductive layers arranged alternately. The external electrode structure partially covers the multilayer stacked structure, and includes a first external electrode layer electrically contacting the plurality of first inner conductive layers and a second external electrode layer electrically contacting the plurality of second inner conductive layers, with the first external electrode layer and the second external electrode layer respectively covering a first side end and a second side end of the multilayer stacked structure. The insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover. The insulating body has a first outer surface, a second outer surface, a third outer surface, and a fourth outer surface around its perimeter, with the plurality of first inner conductive layers and the plurality of second inner conductive layers arranged alternately within the insulating body.

[0006] Furthermore, each first inner conductive layer has a first front exposed end exposed from the first outer surface of the insulating body, a first rear embedded end facing the second outer surface of the insulating body, a first left embedded end facing the third outer surface of the insulating body, and a first right embedded end facing the fourth outer surface of the insulating body. The first front exposed end is electrically in contact with the first outer electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered within the insulating body, the first left embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body, and the first right embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body. The second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body, a second left embedded end facing the fourth outer surface of the insulating body, and a second right embedded end facing the third outer surface of the insulating body. The second front exposed end is electrically in contact with the second outer electrode layer. The second rear embedded end corresponds to the second front exposed end and is enclosed in the insulating body. The second left embedded end is connected between the second front exposed end and the second rear embedded end and is enclosed in the insulating body. The second right embedded end is connected between the second front exposed end and the second rear embedded end and is enclosed in the insulating body.

[0007] Furthermore, the insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3 to 1.0, the ratio of G to T2 is 1:0.3 to 1.0, the ratio of D11 to G is 1:0.3 to 1.0, the ratio of D12 to G is 1:0.3 to 1.0, the ratio of D21 to G is 1:0.3 to 1.0, and the ratio of D22 to G is 1:0.3 to 1.0. Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the distance between the first left inner buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the distance between the first right inner buried end of the first inner conductive layer and the fourth outer surface of the insulating body, D21 is the distance between the second left inner buried end of the second inner conductive layer and the fourth outer surface of the insulating body, and D22 is the distance between the second right inner buried end of the second inner conductive layer and the third outer surface of the insulating body.

[0008] One of the beneficial effects of the present invention is that the method for manufacturing a multilayer varistor provided by the present invention can be achieved by "immersing a sintered multilayer structure in a first solution containing 0.1% to 4.9% alkali metal for a time between 30 and 120 seconds; removing the sintered multilayer structure from the first solution and then drying it to form a dried multilayer structure; and performing a metal ion diffusion step on the dried multilayer structure at a temperature of 600°C to 800°C" or "immersing a sintered multilayer structure in a first solution containing 0.1% to 4.9% alkali metal for a time between 30 and 120 seconds; removing the sintered multilayer structure from the first solution and then drying it to form a dried multilayer structure ... the sintered multilayer structure in a first solution containing 0.1% to 4.9% alkali metal for a time between 30 and 120 seconds" to form a dried multilayer structure. The technical solution involves immersing a multilayered structure in a second solution containing a mixed resin adhesive with a concentration of 0.1% to 4.9% alkali metal ions; removing the sintered multilayered structure from the second solution and then subjecting it to a drying step to form a dried multilayered structure; and then subjecting the dried multilayered structure to a metal ion diffusion step at a temperature of 600°C to 800°C. This approach aims to reduce leakage current and increase current carrying capacity (i.e., maximum peak current).

[0009] Another beneficial effect of the present invention is that the multilayer varistor provided by the present invention can reduce leakage current and increase current carrying capacity (i.e., maximum peak current) by means of the following technical solutions: "the ratio of G to T1 is 1:0.3 to 1.0", "the ratio of G to T2 is 1:0.3 to 1.0", "the ratio of D11 to G is 1:0.3 to 1.0", "the ratio of D12 to G is 1:0.3 to 1.0", "the ratio of D21 to G is 1:0.3 to 1.0" and "the ratio of D22 to G is 1:0.3 to 1.0".

[0010] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the fabrication method of the multilayer varistor provided in the first embodiment of the present invention.

[0012] Figure 2 This is a perspective view of one of the viewing angles of the multi-layer stacked structure provided in the second embodiment of the present invention.

[0013] Figure 3 This is a perspective view of the multi-layer stacked structure provided in the second embodiment of the present invention.

[0014] Figure 4 This is a cross-sectional schematic diagram of the multi-layer stack structure provided in the second embodiment of the present invention.

[0015] Figure 5 This is a three-dimensional schematic diagram of a multilayer varistor provided in the second embodiment of the present invention, viewed from one angle.

[0016] Figure 6 This is a three-dimensional schematic diagram from another viewing angle of the multilayer varistor provided in the second embodiment of the present invention.

[0017] Figure 7 This is a cross-sectional schematic diagram of the multilayer varistor provided in the second embodiment of the present invention. Detailed Implementation

[0018] The following specific embodiments illustrate the implementation of the "multilayer varistor and its manufacturing method" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, it should be stated in advance that the accompanying drawings of this invention are for simple illustration only and are not depictions based on actual dimensions. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0019] [First Embodiment]

[0020] See Figures 1 to 7As shown, the first embodiment of the present invention provides a method for manufacturing a multilayer varistor, which includes: firstly, as shown in the figure... Figure 1 As shown, an initial multi-layered structure is provided (step S100); then, as Figure 1 As shown, the initial multilayer structure is sintered to form a sintered multilayer structure (step S102); then, combined with... Figure 1 as well as Figures 2 to 4 As shown, the sintered multilayer structure is fabricated into a multilayer stack structure 1. The multilayer stack structure 1 includes an insulating carrier 10, a plurality of first inner conductive layers 11 disposed within the insulating carrier 10, and a plurality of second inner conductive layers 12 disposed within the insulating carrier 10 (step S104); Next, in conjunction with Figure 1 as well as Figures 5 to 7 As shown, an external electrode structure 2 is formed to partially cover the multilayer stacked structure 1. The external electrode structure 2 includes a first external electrode layer 21 that electrically contacts a plurality of first inner conductive layers 11 and a second external electrode layer 22 that electrically contacts a plurality of second inner conductive layers 12 (step S106). It is worth noting that the plurality of first inner conductive layers 11 and the plurality of second inner conductive layers 12 are arranged alternately (e.g., ...). Figures 2 to 4 As shown), and the first external electrode layer 21 and the second external electrode layer 22 respectively cover a first side end 1001 and a second side end 1002 of the multilayer stacked structure 1 (as shown). Figures 5 to 7 (As shown). For example, the initial multilayer structure can be a multilayer varistor blank, whose overall shape and internal structure will be similar to... Figures 2 to 4 The multi-layer stacked structure shown is similar to 1. Furthermore, the sintered multi-layer structure can be a multi-layer varistor blank, whose overall shape and internal structure will be similar to... Figures 2 to 4 The multi-layered stack structure shown is approximate. However, the present invention is not limited to the examples given above.

[0021] Furthermore, such as Figure 1As shown, step S104, which involves fabricating a multilayer stack structure 1 from a sintered multilayer structure, further includes either step (A) or step (B). Step (A) includes: first, immersing the sintered multilayer structure in a first solution (metal ion solution) containing "0.1% to 4.9% concentration of alkali metal (LiNO3)" for immersion time between 30 and 120 seconds (step S1040(A)); then, removing the sintered multilayer structure from the first solution and subjecting it to a drying step to form a dried multilayer structure (step S1042(A)); then, subjecting the dried multilayer structure to a metal ion diffusion step at a temperature of 600°C to 800°C (step S1044(A)). Additionally, step (B) includes: first, immersing the sintered multilayer structure in a second solution (metal ion solution) containing a "mixed resin adhesive with a concentration of 0.1% to 4.9% of alkali metal ions" (step S1040(B)); then, removing the sintered multilayer structure from the second solution and subjecting it to a drying step to form a dried multilayer structure (step S1042(B)); then, subjecting the dried multilayer structure to a metal ion diffusion step at a temperature of 600°C to 800°C (step S1044(B)).

[0022] For example, such as Figure 1 As shown, before step S102, which involves sintering the initial multilayer structure, the fabrication method further includes preheating the initial multilayer structure (step S101). Furthermore, in step S101, the initial multilayer structure is heated at a temperature of 400°C to 600°C. Additionally, in step S102, which involves sintering the initial multilayer structure, the initial multilayer structure is sintered at a temperature of 800°C to 1000°C. However, the present invention is not limited to the examples described above.

[0023] [Second Embodiment]

[0024] See Figures 2 to 7As shown, the second embodiment of the present invention provides a multilayer varistor V, which is manufactured using the fabrication method provided in the first embodiment. The multilayer varistor V includes a multilayer stack structure 1 and an external electrode structure 2. Further, the multilayer stack structure 1 includes an insulating carrier 10, a plurality of first inner conductive layers 11 disposed within the insulating carrier 10, and a plurality of second inner conductive layers 12 disposed within the insulating carrier 10, with the plurality of first inner conductive layers 11 and the plurality of second inner conductive layers 12 arranged alternately. Additionally, the external electrode structure 2 includes a first external electrode layer 21 electrically contacting the plurality of first inner conductive layers 11 and a second external electrode layer 22 electrically contacting the plurality of second inner conductive layers 12. The first external electrode layer 21 and the second external electrode layer 22 respectively cover a first side end 1001 and a second side end 1002 of the multilayer stack structure 1.

[0025] Furthermore, in coordination Figures 2 to 4 As shown, the insulating carrier 10 includes an insulating upper cover 101, an insulating lower cover 102, and an insulating body 103 connected between the insulating upper cover 101 and the insulating lower cover 102. Furthermore, the insulating body 103 has a first outer surface 1031, a second outer surface 1032, a third outer surface 1033, and a fourth outer surface 1034 around its perimeter, and a plurality of first inner conductive layers 11 and a plurality of second inner conductive layers 12 are alternately arranged within the insulating body 103.

[0026] Furthermore, in coordination Figure 2 and Figure 4 As shown, each first inner conductive layer 11 has a first front exposed end 110F exposed from the first outer surface 1031 of the insulating body 103, a first rear buried end 110B facing the second outer surface 1032 of the insulating body 103, a first left buried end 110L facing the third outer surface 1033 of the insulating body 103, and a first right buried end 110R facing the fourth outer surface 1034 of the insulating body 103. Furthermore, in conjunction with... Figure 2 , Figure 4 , Figure 5 and Figure 7 As shown, the first front exposed end 110F is electrically in contact with the first external electrode layer 21, the first rear embedded end 110B corresponds to the first front exposed end 110F and is covered within the insulating body 103, the first left embedded end 110L is connected between the first front exposed end 110F and the first rear embedded end 110B and is covered within the insulating body 103, and the first right embedded end 110R is connected between the first front exposed end 110F and the first rear embedded end 110B and is covered within the insulating body 103.

[0027] Furthermore, in coordination Figure 3 and Figure 4As shown, the second inner conductive layer 12 has a second front exposed end 120F exposed from the second outer surface 1032 of the insulating body 103, a second rear embedded end 120B facing the first outer surface 1031 of the insulating body 103, a second left embedded end 120L facing the fourth outer surface 1034 of the insulating body 103, and a second right embedded end 120R facing the third outer surface 1033 of the insulating body 103. Furthermore, in conjunction with... Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the second front exposed end 120F is electrically in contact with the second outer electrode layer 22, the second rear embedded end 120B corresponds to the second front exposed end 120F and is covered within the insulating body 103, the second left embedded end 120L is connected between the second front exposed end 120F and the second rear embedded end 120B and is covered within the insulating body 103, and the second right embedded end 120R is connected between the second front exposed end 120F and the second rear embedded end 120B and is covered within the insulating body 103.

[0028] It is worth noting that, in conjunction with Figures 2 to 4 As shown, the insulating carrier 10 meets the following conditions: the ratio of G to T1 is 1:0.3 to 1.0, the ratio of G to T2 is 1:0.3 to 1.0, the ratio of D11 to G is 1:0.3 to 1.0, the ratio of D12 to G is 1:0.3 to 1.0, the ratio of D21 to G is 1:0.3 to 1.0, and the ratio of D22 to G is 1:0.3 to 1.0. Wherein, as... Figure 4 As shown, T1 is the thickness of the insulating upper cover 101, T2 is the thickness of the insulating lower cover 102, and G is the spacing between adjacent first inner conductive layers 11 and second inner conductive layers 12. Figure 2 As shown, D11 is the distance between the first left inner buried end 110L of the first inner conductive layer 11 and the third outer surface 1033 of the insulating body 103, and D12 is the distance between the first right inner buried end 110R of the first inner conductive layer 11 and the fourth outer surface 1034 of the insulating body 103. Figure 3 As shown, D21 is the distance between the second left inner buried end 120L of the second inner conductive layer 12 and the fourth outer surface 1034 of the insulating body 103, and D22 is the distance between the second right inner buried end 120R of the second inner conductive layer 12 and the third outer surface 1033 of the insulating body 103.

[0029] Please refer to Table 1 below. The present invention uses an insulating carrier 10 with a predetermined length (2.2±0.2 mm), width (1.7±0.2 mm), and thickness (1.7±0.2 mm), and a total of 8 layers including multiple first inner conductive layers 11 and multiple second inner conductive layers 12, for experimental testing. The experimental results are shown below:

[0030] Table 1

[0031]

[0032] [Beneficial Effects of the Examples]

[0033] One of the beneficial effects of this invention is that the method for manufacturing a multilayer varistor provided by this invention can reduce leakage current by using either the following technical solutions: "immersing a sintered multilayer structure in a first solution containing 0.1% to 4.9% alkali metal for 30 to 120 seconds; removing the sintered multilayer structure from the first solution and then drying it to form a dried multilayer structure; and performing a metal ion diffusion step on the dried multilayer structure at a temperature of 600°C to 800°C" or "immersing the sintered multilayer structure in a second solution including a mixed resin adhesive containing 0.1% to 4.9% alkali metal ions; removing the sintered multilayer structure from the second solution and then drying it to form a dried multilayer structure; and performing a metal ion diffusion step on the dried multilayer structure at a temperature of 600°C to 800°C". (current) and increase the current capacity (i.e., the maximum peak current).

[0034] Another beneficial effect of the present invention is that the multilayer varistor provided by the present invention can reduce leakage current and increase current carrying capacity (i.e., maximum peak current) by means of the following technical solutions: "the ratio of G to T1 is 1:0.3 to 1.0", "the ratio of G to T2 is 1:0.3 to 1.0", "the ratio of D11 to G is 1:0.3 to 1.0", "the ratio of D12 to G is 1:0.3 to 1.0", "the ratio of D21 to G is 1:0.3 to 1.0" and "the ratio of D22 to G is 1:0.3 to 1.0".

[0035] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of protection of the claims of the present invention. Therefore, all equivalent technical changes made based on the content of the present invention specification and drawings are included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a multilayer varistor, characterized in that, The method for manufacturing the multilayer varistor includes: Provides an initial multi-layered structure; The initial multilayer structure is sintered to form a sintered multilayer structure; The sintered multilayer structure is fabricated into a multilayer stack structure, the multilayer stack structure including an insulating carrier, a plurality of first inner conductive layers disposed within the insulating carrier, and a plurality of second inner conductive layers disposed within the insulating carrier, wherein the plurality of first inner conductive layers and the plurality of second inner conductive layers are arranged alternately; and An external electrode structure is formed to partially cover the multilayer stacked structure. The external electrode structure includes a first external electrode layer that electrically contacts a plurality of first inner conductive layers and a second external electrode layer that electrically contacts a plurality of second inner conductive layers. The first external electrode layer and the second external electrode layer respectively cover a first side end and a second side end of the multilayer stacked structure. The step of fabricating the sintered multilayer structure into the multilayer stack structure further includes step A or step B. Step A includes: immersing the sintered multilayer structure in a first solution containing 0.1% to no more than 4.9% alkali metal for a time between 30 and 120 seconds; removing the sintered multilayer structure from the first solution and then drying it to form a dried multilayer structure; and subjecting the dried multilayer structure to metal ion diffusion at a temperature of 600°C to 800°C. Step B includes: immersing the sintered multilayer structure in a second solution comprising a mixed resin adhesive containing 0.1% to no more than 4.9% alkali metal ions; removing the sintered multilayer structure from the second solution and subjecting it to a drying step to form a dried multilayer structure; and subjecting the dried multilayer structure to a metal ion diffusion step at a temperature of 600°C to 800°C.

2. The method for manufacturing a multilayer varistor according to claim 1, characterized in that, Before the step of sintering the initial multilayer structure, the fabrication method further includes: preheating the initial multilayer structure; wherein, in the step of preheating the initial multilayer structure, the initial multilayer structure is heated at a temperature of 400°C to 600°C; wherein, in the step of sintering the initial multilayer structure, the initial multilayer structure is sintered at a temperature of 800°C to 1000°C.

3. A multilayer varistor, characterized in that, The multilayer varistor is manufactured by the manufacturing method according to claim 1, and the multilayer varistor includes the multilayer stack structure and the external electrode structure; The insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover. The insulating body has a first outer surface, a second outer surface, a third outer surface, and a fourth outer surface around it, and a plurality of first inner conductive layers and a plurality of second inner conductive layers are alternately arranged in the insulating body. Each of the first inner conductive layers has a first front exposed end exposed from the first outer surface of the insulating body, a first rear embedded end facing the second outer surface of the insulating body, a first left embedded end facing the third outer surface of the insulating body, and a first right embedded end facing the fourth outer surface of the insulating body. The first front exposed end is electrically in contact with the first outer electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered within the insulating body, the first left embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body, and the first right embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body. The second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body, a second left embedded end facing the fourth outer surface of the insulating body, and a second right embedded end facing the third outer surface of the insulating body. The second front exposed end is electrically in contact with the second outer electrode layer. The second rear embedded end corresponds to the second front exposed end and is covered within the insulating body. The second left embedded end is connected between the second front exposed end and the second rear embedded end and is covered within the insulating body. The second right embedded end is connected between the second front exposed end and the second rear embedded end and is covered within the insulating body.

4. The multilayer varistor according to claim 3, characterized in that, The insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, the ratio of D11 to G is 1:0.3~1.0, the ratio of D12 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0; Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the distance between the first left inner buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the distance between the first right inner buried end of the first inner conductive layer and the fourth outer surface of the insulating body, D21 is the distance between the second left inner buried end of the second inner conductive layer and the fourth outer surface of the insulating body, and D22 is the distance between the second right inner buried end of the second inner conductive layer and the third outer surface of the insulating body.

5. A method for manufacturing a multilayer varistor, characterized in that, The method for manufacturing the multilayer varistor includes: Provides an initial multi-layered structure; The initial multilayer structure is sintered to form a sintered multilayer structure; The sintered multilayer structure is fabricated into a multilayer stack structure, the multilayer stack structure including an insulating carrier, a plurality of first inner conductive layers disposed within the insulating carrier, and a plurality of second inner conductive layers disposed within the insulating carrier; and An external electrode structure is formed to partially cover the multilayer stacked structure. The external electrode structure includes a first external electrode layer that electrically contacts a plurality of first inner conductive layers and a second external electrode layer that electrically contacts a plurality of second inner conductive layers. The step of fabricating the sintered multilayer structure into the multilayer stack structure further includes: The sintered multilayer structure is immersed in a metal ion solution; The sintered multilayer structure is removed from the metal ion solution and then dried to form a dried multilayer structure; and The dried multilayer structure is subjected to a metal ion diffusion step at a temperature of 600℃~800℃. In the step of immersing the sintered multilayer structure in the metal ion solution, the metal ion solution is either a first solution or a second solution. The first solution contains 0.1% to no more than 4.9% alkali metal, and the second solution includes a mixed resin adhesive containing 0.1% to no more than 4.9% alkali metal ions.

6. The method for manufacturing a multilayer varistor according to claim 5, characterized in that, Before the step of sintering the initial multilayer structure, the fabrication method further includes: preheating the initial multilayer structure; wherein, in the step of preheating the initial multilayer structure, the initial multilayer structure is heated at a temperature of 400°C to 600°C; wherein, in the step of sintering the initial multilayer structure, the initial multilayer structure is sintered at a temperature of 800°C to 1000°C.

7. A multilayer varistor, characterized in that, The multilayer varistor is manufactured by the manufacturing method according to claim 5, and the multilayer varistor includes the multilayer stack structure and the external electrode structure; The insulating carrier includes an insulating upper cover, an insulating lower cover, and an insulating body connected between the insulating upper cover and the insulating lower cover. The insulating body has a first outer surface, a second outer surface, a third outer surface, and a fourth outer surface around it, and a plurality of first inner conductive layers and a plurality of second inner conductive layers are alternately arranged in the insulating body. Each of the first inner conductive layers has a first front exposed end exposed from the first outer surface of the insulating body, a first rear embedded end facing the second outer surface of the insulating body, a first left embedded end facing the third outer surface of the insulating body, and a first right embedded end facing the fourth outer surface of the insulating body. The first front exposed end is electrically in contact with the first outer electrode layer, the first rear embedded end corresponds to the first front exposed end and is covered within the insulating body, the first left embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body, and the first right embedded end is connected between the first front exposed end and the first rear embedded end and is covered within the insulating body. The second inner conductive layer has a second front exposed end exposed from the second outer surface of the insulating body, a second rear embedded end facing the first outer surface of the insulating body, a second left embedded end facing the fourth outer surface of the insulating body, and a second right embedded end facing the third outer surface of the insulating body. The second front exposed end is electrically in contact with the second outer electrode layer. The second rear embedded end corresponds to the second front exposed end and is covered within the insulating body. The second left embedded end is connected between the second front exposed end and the second rear embedded end and is covered within the insulating body. The second right embedded end is connected between the second front exposed end and the second rear embedded end and is covered within the insulating body.

8. The multilayer varistor according to claim 7, characterized in that, The insulating carrier meets the following conditions: the ratio of G to T1 is 1:0.3~1.0, the ratio of G to T2 is 1:0.3~1.0, the ratio of D11 to G is 1:0.3~1.0, the ratio of D12 to G is 1:0.3~1.0, the ratio of D21 to G is 1:0.3~1.0, and the ratio of D22 to G is 1:0.3~1.0; Wherein, T1 is the thickness of the insulating upper cover, T2 is the thickness of the insulating lower cover, G is the distance between the adjacent first inner conductive layer and the second inner conductive layer, D11 is the distance between the first left inner buried end of the first inner conductive layer and the third outer surface of the insulating body, D12 is the distance between the first right inner buried end of the first inner conductive layer and the fourth outer surface of the insulating body, D21 is the distance between the second left inner buried end of the second inner conductive layer and the fourth outer surface of the insulating body, and D22 is the distance between the second right inner buried end of the second inner conductive layer and the third outer surface of the insulating body.

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