Hemt epitaxial wafer and preparation method thereof, hemt
By employing a composite buffer structure of SiO2 grid layer, two-dimensional AlInN layer and superlattice layer in GaN-based HEMT devices, the lattice and thermal mismatch problems caused by silicon substrates were solved, resulting in higher crystal quality and device performance, reduced leakage current, and increased two-dimensional electron gas concentration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2026-04-01
- Publication Date
- 2026-06-26
AI Technical Summary
Existing GaN-based HEMT devices, when using silicon substrates, are prone to epitaxial layer cracking, warping, and increased dislocation density due to lattice mismatch and differences in thermal expansion coefficients, which affect device performance and reliability.
A composite buffer structure consisting of a SiO2 grid layer, a two-dimensional AlInN layer, and a superlattice layer is adopted. Through regional growth and stress compensation, lattice and thermal mismatch are alleviated, leakage current is reduced, and crystal quality is improved.
It effectively reduces thin film cracking and dislocation accumulation, improves crystal and device performance, reduces leakage current, increases two-dimensional electron gas concentration, and enhances the overall performance of HEMT devices.
Smart Images
Figure CN121968671B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of field-effect transistor technology, and more particularly to a HEMT epitaxial wafer and its fabrication method, and HEMT. Background Technology
[0002] Currently, GaN-based power switching devices mainly include AlGaN / GaN HEMT (HFET), GaN MOSFET, and MIS-HEMT structures. Among them, AlGaN / GaN HEMT has the advantages of simple process, mature technology, excellent forward conduction characteristics, and high operating frequency, making it the most popular structure among GaN power switching devices.
[0003] On the other hand, GaN-based power devices lack homogeneous substrates during growth and often employ heterogeneous substrates such as silicon, sapphire, or SiC. Existing mature processes mostly utilize sapphire substrates. Silicon substrates, due to their low cost, large size, and good compatibility with existing CMOS processes, are becoming an important direction for the mass production of GaN-based HEMTs; however, the significant lattice mismatch and difference in thermal expansion coefficients between silicon and GaN easily lead to epitaxial layer cracking, warping, and increased dislocation density, severely limiting device performance. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a HEMT epitaxial wafer and its preparation method, which can reduce leakage current and improve device performance and reliability.
[0005] Another technical problem that this invention aims to solve is to provide a HEMT with low leakage current and strong device performance.
[0006] To solve the above-mentioned technical problems, the present invention provides a HEMT epitaxial wafer, which includes a silicon substrate, and a composite buffer layer, a channel layer, an insertion layer, a barrier layer and a capping layer sequentially stacked on the silicon substrate.
[0007] The composite buffer layer comprises a SiO2 mesh layer, a two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer sequentially stacked on the silicon substrate; the superlattice layer comprises alternating InGaN layers and a second AlGaN layer.
[0008] Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer;
[0009] The proportion of Al component in the first AlGaN layer is less than the proportion of Al component in the second AlGaN layer.
[0010] As an improvement to the above technical solution, along the growth direction of the HEMT epitaxial wafer, the proportion of In component in the two-dimensional AlInN layer increases progressively; and / or
[0011] Along the growth direction of the HEMT epitaxial wafer, the Al composition in the first AlGaN layer decreases.
[0012] As an improvement to the above technical solution, along the growth direction of the HEMT epitaxial wafer, the proportion of In component in the two-dimensional AlInN layer increases from 0.01~0.05 to 0.1~0.2; and / or
[0013] Along the growth direction of the HEMT epitaxial wafer, the Al composition in the first AlGaN layer decreases from 0.08~0.1 to 0~0.01.
[0014] As an improvement to the above technical solution, after the two-dimensional AlInN layer is grown, it is annealed at 1000~1200℃ in an H2 atmosphere.
[0015] As an improvement to the above technical solution, the thickness of the SiO2 mesh layer is 10nm~100nm; the area of the silicon substrate exposed by a single mesh is 10~100μm. 2 ; and / or
[0016] The thickness of the two-dimensional AlInN layer is 20 nm to 120 nm, and the proportion of In component is 0.01 to 0.2%; and / or
[0017] The thickness of the first AlGaN layer is 20nm~100nm, and the proportion of its Al component is 0.01~0.1%.
[0018] As an improvement to the above technical solution, the number of periods of the superlattice layer is 3 to 20; and / or
[0019] The thickness of a single InGaN layer is 0.5 nm to 5 nm, and the In content is 0.01 to 0.2%; and / or
[0020] The thickness of a single second AlGaN layer is 5nm~15nm, and the proportion of Al component is 0.05~0.3%.
[0021] Accordingly, the present invention also discloses a method for preparing a HEMT epitaxial wafer, which includes:
[0022] Provide silicon substrates;
[0023] A composite buffer layer, a channel layer, an insertion layer, a barrier layer, and a capping layer are sequentially grown on the silicon substrate.
[0024] The composite buffer layer comprises a SiO2 mesh layer, a two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer sequentially stacked on the silicon substrate; the superlattice layer comprises alternating InGaN layers and a second AlGaN layer.
[0025] Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer;
[0026] The proportion of Al component in the first AlGaN layer is less than the proportion of Al component in the second AlGaN layer.
[0027] As an improvement to the above technical solution, the method for preparing the SiO2 mesh layer includes:
[0028] A SiO2 layer is grown on the silicon substrate by PECVD; wherein the growth temperature is 200℃~300℃, the cavity pressure is 500mtorr~1000mtorr, the RF power is 20W~80W, and the flow ratio of N2O to SiH4 is 1.5~2.
[0029] The SiO2 layer is etched to form multiple grids that expose the silicon substrate, resulting in a SiO2 grid layer.
[0030] As an improvement to the above technical solution, the two-dimensional AlInN layer, the superlattice layer, and the first AlGaN layer are all grown by MOCVD;
[0031] The growth temperature of the two-dimensional AlInN layer is 700℃~900℃, and the growth pressure is 50 torr~500 torr.
[0032] The growth temperature of the superlattice layer is 750℃~900℃, and the growth pressure is 50 torr~500 torr.
[0033] The growth temperature of the first AlGaN layer is 800℃~900℃, and the growth pressure is 50 torr~500 torr.
[0034] Accordingly, the present invention also discloses a HEMT, which includes the above-described HEMT epitaxial wafer.
[0035] Implementing this invention has the following beneficial effects:
[0036] The HEMT epitaxial wafer provided by this invention includes a composite buffer layer comprising a SiO2 grid layer, a two-dimensional AlInN layer, a superlattice layer, and a first AlGaN layer sequentially stacked on a silicon substrate. The superlattice layer comprises alternating InGaN layers and a second AlGaN layer. Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer. Based on the above-mentioned HEMT epitaxial wafer, firstly, the SiO2 grid layer enables regionalized growth of subsequent layers, reducing the accumulation of thermal stress, minimizing stress-induced film cracking, and improving yield; it also reduces dislocation accumulation in subsequent grown layers, improving crystal quality and device performance. Secondly, the two-dimensional AlInN layer effectively prevents "Ga remelting," ensuring a smooth surface and avoiding the formation of micron-sized holes on the epitaxial wafer surface, thus improving the crystal quality of subsequent layers and enhancing device performance. Thirdly, the superlattice layer formed by the alternating stacking of InGaN and second AlGaN layers effectively compensates for stress, improving the overall crystal quality of the epitaxial wafer. Fourthly, the proportion of Al component in the first AlGaN layer is less than that in the second AlGaN layer, which can effectively reduce the lattice mismatch with the subsequently grown GaN channel layer and improve the crystal quality of the channel layer. In summary, the HEMT epitaxial wafer in this invention effectively alleviates the lattice and thermal mismatch between the silicon substrate and the epitaxial layer through the composite buffer layer, releases the stress of the epitaxial layer, reduces the leakage current of the power device, increases the two-dimensional electron gas concentration, and thus improves the overall performance of the HEMT device. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of the structure of a HEMT epitaxial wafer in one embodiment of the present invention;
[0038] Figure 2 This is a flowchart of a method for preparing a HEMT epitaxial wafer according to an embodiment of the present invention. Detailed Implementation
[0039] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.
[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0042] In this invention, terms such as "first aspect" and "second aspect" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features.
[0043] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.
[0044] Unless otherwise specified, the temperature parameters in this invention can be either constant temperature processing or processing within a certain temperature range. The constant temperature processing allows temperature fluctuations within the precision range controlled by the instrument.
[0045] Please see Figure 1As a first aspect of the present invention, the present invention provides a HEMT epitaxial wafer, comprising a silicon substrate 100, and a composite buffer layer 200, a channel layer 300, an insertion layer 400, a barrier layer 500, and a capping layer 600 sequentially stacked on the silicon substrate 100; wherein, the composite buffer layer 200 comprises a SiO2 grid layer 210, a two-dimensional AlInN layer 220, a superlattice layer 230, and a first AlGaN layer 240 sequentially stacked on the silicon substrate 100; the superlattice layer 230 comprises alternating layers of InGaN 231 and a second AlGaN 232; a plurality of grids exposing the silicon substrate 100 are formed on the SiO2 grid layer 210. Based on the above-described HEMT epitaxial wafer, firstly, the regional growth of subsequent layers is achieved through the SiO2 grid layer 210, reducing the accumulation of thermal stress, reducing film cracking caused by stress, and improving the yield; at the same time, it also reduces the accumulation of dislocations in subsequent grown layers, improving crystal quality and device performance. Secondly, the two-dimensional AlInN layer 220 effectively prevents "Ga remelting," ensuring a smooth surface and avoiding the formation of micron-sized holes on the epitaxial wafer surface. This also improves the crystal quality of subsequent layers, enhancing device performance. Thirdly, the superlattice layer 230 formed by alternating InGaN layer 231 and second AlGaN layer 232 effectively compensates for stress, improving the overall crystal quality of the epitaxial wafer. Fourthly, the lower proportion of Al in the first AlGaN layer 240 compared to the second AlGaN layer 232 effectively reduces lattice mismatch with the subsequently grown GaN channel layer 300, improving the crystal quality of the channel layer 300. In summary, the HEMT epitaxial wafer of this invention effectively alleviates lattice and thermal mismatch between the silicon substrate 100 and the epitaxial layer through the composite buffer layer 200, releasing stress in the epitaxial layer, reducing leakage current in the power device, increasing the two-dimensional electron gas concentration, and thus improving the overall performance of the HEMT device.
[0046] The thickness of the SiO2 mesh layer 210 is 10nm to 100nm, exemplarily 20nm, 40nm, 60nm or 80nm, but not limited thereto. Preferably, in some embodiments, the thickness of the SiO2 mesh layer 210 is 40nm to 60nm. This thickness range can ensure the stability of the mesh structure and further improve the stress release efficiency.
[0047] Specifically, the grid formed by the SiO2 grid layer 210 to expose the silicon substrate 100 can be rectangular, hexagonal, circular, or elliptical, but is not limited to these shapes; preferably, the grid is square. The area of the silicon substrate 100 exposed by a single grid is 10 μm. 2 ~100μm 2 For example, 20μm 2 40μm 2 60μm2 or 80μm 2 However, this is not the only possibility. Preferably, in some embodiments, the area of the silicon substrate 100 exposed by a single grid is 30 μm. 2 ~50μm 2 .
[0048] Specifically, the width of the SiO2 grid strips used to separate adjacent grids is 3μm to 10μm, exemplarily 4μm, 6μm, or 8μm, but not limited to these. It should be noted that if a grid is not formed, the SiO2 grid layer 210 will not be able to achieve regionalized stress release and dislocation suppression, but will instead introduce stress, leading to an increased risk of epitaxial layer fracture.
[0049] The thickness of the two-dimensional AlInN layer 220 is greater than the depth of the mesh, ensuring that it completely covers the SiO2 mesh structure, thereby forming a continuous and uniform stress buffer interface during subsequent epitaxial growth. Specifically, the thickness of the two-dimensional AlInN layer 220 is 20nm to 120nm, exemplarily 40nm, 60nm, 80nm, or 100nm, but not limited thereto. Preferably, it is 50nm to 80nm.
[0050] Specifically, the proportion of In component in the two-dimensional AlInN layer 220 is 0.01~0.2%, exemplarily 0.04, 0.08, 0.12, 0.16 or 0.18, but not limited thereto. Preferably, in some embodiments, the proportion of In component in the two-dimensional AlInN layer 220 is 0.02~0.12. It should be noted that the proportion of In component in the two-dimensional AlInN layer 220 in this invention refers to the average proportion of the entire layer.
[0051] The superlattice layer 230 has 3 to 20 periods, exemplarily 5, 10, 15 or 18, but is not limited thereto. Preferably it is 5 to 15.
[0052] The thickness of a single InGaN layer 231 is 0.5 nm to 5 nm, exemplarily 0.8 nm, 1.3 nm, 2.0 nm, 3.5 nm, or 4.8 nm, but not limited thereto. Preferably, it is 1 nm to 4 nm. The proportion of In component in the InGaN layer 231 is 0.01 to 0.2%, exemplarily 0.03, 0.06, 0.10, 0.14, or 0.18, but not limited thereto. Preferably, it is 0.05 to 0.15.
[0053] The thickness of a single second AlGaN layer 232 is 5nm to 15nm, exemplarily 6nm, 8nm, 10nm, 12nm, or 14nm, but not limited thereto. Preferably, it is 8nm to 15nm. The proportion of Al component in the second AlGaN layer 232 is 0.05% to 0.3%, exemplarily 0.06%, 0.08%, 0.12%, 0.16%, or 0.22%, but not limited thereto.
[0054] The thickness of the first AlGaN layer 240 is 20nm to 100nm, exemplarily 30nm, 50nm, 70nm, or 90nm, but not limited thereto. Preferably, it is 20nm to 50nm. The proportion of Al component in the first AlGaN layer 240 is 0.01 to 0.1%, exemplarily 0.03, 0.05, 0.07, or 0.09, but not limited thereto. Preferably, it is 0.01 to 0.08.
[0055] Among them, the channel layer 300 is an undoped GaN layer with a thickness of 200nm~500nm.
[0056] The insertion layer 400 is an AlN layer, which can further improve the smoothness of the interface and increase the concentration and mobility of the two-dimensional electron gas. Its thickness is 0.5nm~5nm.
[0057] Among them, the barrier layer 500 is an AlGaN layer with an Al content of 0.2~0.3% and a thickness of 20nm~35nm.
[0058] Among them, the capping layer 600 is a GaN capping layer with a thickness of 2nm~6nm.
[0059] Preferably, in some embodiments, the proportion of In in the two-dimensional AlInN layer 220 increases gradually along the growth direction of the HEMT epitaxial wafer. Based on this gradient design, the lattice quality of the epitaxial layer can be further improved, thereby enhancing the overall performance of the HEMT device. More specifically, in some embodiments, the proportion of In in the two-dimensional AlInN layer 220 increases from 0.01~0.05 to 0.1~0.2%.
[0060] Preferably, in some embodiments, the Al composition in the first AlGaN layer 240 decreases along the growth direction of the HEMT epitaxial wafer. Based on this, the two-dimensional electron gas mobility and thermal stability of the channel layer 300 can be further improved, while alleviating the problem of interface stress concentration. More specifically, in some embodiments, the Al composition in the first AlGaN layer 240 decreases from 0.08~0.1 to 0~0.01.
[0061] Preferably, in some embodiments, after the two-dimensional AlInN layer 220 is grown, it is annealed at 1000~1200℃ in an H2 atmosphere. This method can redistribute the In atoms in the AlInN layer, effectively eliminating lattice defects and improving interface flatness, further enhancing the overall performance of the HEMT device.
[0062] Please see Figure 2 As a second aspect of the present invention, the present invention provides a method for preparing a HEMT epitaxial wafer, which includes the following steps:
[0063] S1: Provides a silicon substrate;
[0064] S2: A composite buffer layer, a channel layer, an insertion layer, a barrier layer, and a capping layer are sequentially grown on a silicon substrate;
[0065] The composite buffer layer comprises a SiO2 grid layer, a two-dimensional AlInN layer, a superlattice layer, and a first AlGaN layer sequentially stacked on a silicon substrate. The superlattice layer consists of alternating InGaN and second AlGaN layers. Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer. The proportion of Al in the first AlGaN layer is less than that in the second AlGaN layer. Based on the above fabrication method, the HEMT epitaxial wafer exhibits several advantages: First, the SiO2 grid layer enables regionalized growth of subsequent layers, reducing thermal stress accumulation, minimizing stress-induced film cracking, and improving yield. It also reduces dislocation accumulation in subsequent layers, improving crystal quality and device performance. Second, the two-dimensional AlInN layer effectively prevents "Ga remelting," ensuring a smooth surface and avoiding the formation of micron-sized holes on the epitaxial wafer surface, thus improving the crystal quality of subsequent layers and enhancing device performance. Third, the superlattice layer formed by alternating InGaN and second AlGaN layers effectively compensates for stress, improving the overall crystal quality of the epitaxial wafer. Fourthly, the proportion of Al component in the first AlGaN layer is less than that in the second AlGaN layer, which can effectively reduce the lattice mismatch with the subsequently grown GaN channel layer and improve the crystal quality of the channel layer. In summary, the HEMT epitaxial wafer in this invention effectively alleviates the lattice and thermal mismatch between the silicon substrate and the epitaxial layer through the composite buffer layer, releases the stress of the epitaxial layer, reduces the leakage current of the power device, increases the two-dimensional electron gas concentration, and thus improves the overall performance of the HEMT device.
[0066] Specifically, in some implementations, step S2 includes:
[0067] S21: Grow a composite buffer layer on the substrate;
[0068] Specifically, in some implementations, a SiO2 layer is first grown on a silicon substrate by PECVD, and then etched to form a grid that exposes the silicon substrate, resulting in a SiO2 grid layer; then, a two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer are grown on the SiO2 grid layer using MOCVD.
[0069] The process parameters for PECVD growth of SiO2 layers include: growth temperature of 200℃~300℃, chamber pressure of 500mtorr~1000mtorr, RF power of 20W~80W, and N2O to SiH4 flow ratio of 1.5~2. Under these conditions, the SiO2 layer grown has less stress accumulation, which is beneficial to the uniform nucleation and stress release of subsequent epitaxial layers.
[0070] When etching the SiO2 layer, either wet etching or dry etching processes can be used, but it is not limited to these.
[0071] The process parameters for MOCVD growth of two-dimensional AlInN layers include: growth temperature of 700℃~900℃ and growth pressure of 50 torr~500 torr. The process parameters for MOCVD growth of superlattice layers include: growth temperature of 750℃~900℃ and growth pressure of 50 torr~500 torr. The process parameters for MOCVD growth of the first AlGaN layer include: growth temperature of 800℃~900℃ and growth pressure of 50 torr~500 torr.
[0072] S22: Growing a channel layer on a composite buffer layer;
[0073] Specifically, in some implementations, an undoped GaN layer is grown by MOCVD as a channel layer at a growth temperature of 1000℃~1200℃ and a growth pressure of 50 torr~500 torr.
[0074] S23: Growing an insertion layer on the channel layer;
[0075] Specifically, in some implementations, an AlN layer is grown by MOCVD as an insertion layer. The growth temperature is 700℃~1100℃, and the growth pressure is 100 torr~200 torr.
[0076] S24: Grow a barrier layer on the insertion layer;
[0077] Specifically, in some implementations, an AlGaN layer is grown by MOCVD as a barrier layer. The growth temperature is 800℃~1200℃, and the growth pressure is 100 torr~200 torr.
[0078] S25: Growing a capping layer on the barrier layer.
[0079] Specifically, in some implementations, a GaN cap layer is grown using MOCVD. The growth temperature is 700℃~1100℃, and the growth pressure is 100 torr~200 torr.
[0080] Accordingly, the present invention also provides a HEMT comprising the above-described HEMT epitaxial wafer.
[0081] The present invention is further illustrated below with specific embodiments:
[0082] Example 1
[0083] This embodiment provides a HEMT epitaxial wafer, which includes a silicon substrate, and a composite buffer layer, a channel layer, an insertion layer, a barrier layer and a capping layer are sequentially stacked on the silicon substrate.
[0084] The composite buffer layer comprises a SiO2 grid layer, a two-dimensional AlInN layer, a superlattice layer, and a first AlGaN layer sequentially stacked on a silicon substrate. The SiO2 grid layer has a thickness of 45 nm and forms multiple square grids that expose the silicon substrate. The area of each square grid exposing the silicon substrate is 36 μm. 2 The width of the SiO2 grid strips used to separate adjacent grids is 5.5 μm. The thickness of the two-dimensional AlInN layer is 35 nm, and its In composition is 0.06, which remains constant. The superlattice layer consists of alternating layers of InGaN and AlGaN, with a period number of 6; the thickness of the InGaN layer is 3.1 nm, and its In composition is 0.08; the thickness of the second AlGaN layer is 10 nm, and its Al composition is 0.08. The thickness of the first AlGaN layer is 28 nm, and its Al composition is 0.05, which remains constant.
[0085] The channel layer is an undoped GaN layer with a thickness of 300 nm. The insertion layer is an AlN layer with a thickness of 3 nm. The barrier layer is an AlGaN layer with an Al content of 0.22 and a thickness of 25 nm. The capping layer is a GaN capping layer with a thickness of 4 nm.
[0086] The method for preparing the HEMT epitaxial wafer in this embodiment is as follows:
[0087] (1) Provide a silicon substrate;
[0088] (2) A SiO2 layer is formed on a silicon substrate by PECVD;
[0089] The growth temperature was 240℃, the cavity pressure was 950 mtorr, the RF power was 45W, and the flow ratio of N2O to SiH4 was 1.8.
[0090] (3) The SiO2 layer is etched by ICP etching process to form multiple grids that expose the silicon substrate, thus obtaining a SiO2 grid layer;
[0091] (4) A two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer are grown on the SiO2 grid layer to obtain a composite buffer layer;
[0092] Specifically, a two-dimensional AlInN layer, a superlattice layer, and a first AlGaN layer are grown by MOCVD; the growth temperature of the two-dimensional AlInN layer is 780℃ and the growth pressure is 100 torr; the growth temperature of the superlattice layer is 850℃ and the growth pressure is 300 torr; the growth temperature of the first AlGaN layer is 850℃ and the growth pressure is 300 torr.
[0093] (5) Growing a channel layer on the composite buffer layer;
[0094] Specifically, an undoped GaN layer is grown on the composite buffer layer as a channel layer at a growth temperature of 1050℃ and a growth pressure of 300 torr.
[0095] (6) Growing an insertion layer on the channel layer;
[0096] Specifically, an AlN layer was grown on the channel layer as an insertion layer. The growth temperature was 1100℃ and the growth pressure was 100 torr.
[0097] (7) Growing a barrier layer on the insertion layer;
[0098] Specifically, an AlGaN layer is grown on the insertion layer as a barrier layer. The growth temperature is 1120℃ and the growth pressure is 150 torr.
[0099] (8) Grow a capping layer on the barrier layer.
[0100] Specifically, a GaN cap layer is grown on the barrier layer as a capping layer. The growth temperature is 1000℃ and the growth pressure is 150 torr.
[0101] Example 2
[0102] This embodiment provides a HEMT epitaxial wafer, which differs from Embodiment 1 in that:
[0103] Along the growth direction of the HEMT epitaxial wafer, the proportion of In component in the two-dimensional AlInN layer increases from 0.01 to 0.1.
[0104] Everything else is the same as in Example 1.
[0105] Example 3
[0106] This embodiment provides a HEMT epitaxial wafer, which differs from Embodiment 2 in that:
[0107] Along the growth direction of the HEMT epitaxial wafer, the Al composition in the first AlGaN layer decreases from 0.08 to 0.01.
[0108] Everything else is the same as in Example 2.
[0109] Example 4
[0110] This embodiment provides a HEMT epitaxial wafer, which differs from Embodiment 3 in that:
[0111] After the two-dimensional AlInN layer was grown, it was annealed at 1100℃ in an H2 atmosphere.
[0112] Everything else is the same as in Example 3.
[0113] Comparative Example 1
[0114] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0115] No etching is performed on the SiO2 layer, i.e. step (3) is not included.
[0116] Everything else is the same as in Example 1.
[0117] Comparative Example 2
[0118] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0119] Excluding the SiO2 mesh layer.
[0120] Everything else is the same as in Example 1.
[0121] Comparative Example 3
[0122] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0123] Excluding two-dimensional AlInN layers.
[0124] Everything else is the same as in Example 1.
[0125] Comparative Example 4
[0126] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0127] Excluding superlattice layers.
[0128] Everything else is the same as in Example 1.
[0129] Comparative Example 5
[0130] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0131] Excluding the first AlGaN layer.
[0132] Comparative Example 6
[0133] This comparative example provides a HEMT epitaxial wafer, which differs from Example 1 in that:
[0134] An AlN layer grown by PVD was used as a composite buffer layer with a thickness of 20 nm.
[0135] Everything else is the same as in Example 1.
[0136] HEMT epitaxial wafers prepared in Examples 1-4 and Comparative Examples 1-6 were fabricated into HEMTs and tested. XRD analysis was also performed on the epitaxial wafers, and the specific results are as follows:
[0137]
[0138] As can be seen from the table above, the HEMT epitaxial wafer of this invention can effectively improve the crystal quality of the epitaxial wafer, reduce its leakage current, and improve the overall performance of the HEMT device. A comparison of Example 1 with Comparative Examples 1-6 shows that when the composite buffer layer structure of this invention is changed, the crystal quality of the HEMT epitaxial wafer decreases and the leakage current increases.
[0139] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.
Claims
1. A HEMT epitaxial wafer, characterized in that, The system includes a silicon substrate, and a composite buffer layer, a channel layer, an insertion layer, a barrier layer, and a capping layer sequentially stacked on the silicon substrate. The composite buffer layer comprises a SiO2 mesh layer, a two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer sequentially stacked on the silicon substrate; the superlattice layer comprises alternating InGaN layers and a second AlGaN layer. Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer; The proportion of Al component in the first AlGaN layer is less than the proportion of Al component in the second AlGaN layer; Along the growth direction of the HEMT epitaxial wafer, the proportion of In component in the two-dimensional AlInN layer increases progressively. Along the growth direction of the HEMT epitaxial wafer, the Al composition in the first AlGaN layer decreases.
2. The HEMT epitaxial wafer as described in claim 1, characterized in that, Along the growth direction of the HEMT epitaxial wafer, the proportion of In component in the two-dimensional AlInN layer increases from 0.01~0.05 to 0.1~0.2; and / or Along the growth direction of the HEMT epitaxial wafer, the Al composition in the first AlGaN layer decreases from 0.08~0.1 to 0~0.
01.
3. The HEMT epitaxial wafer as described in claim 1, characterized in that, After the two-dimensional AlInN layer is grown, it is annealed at 1000~1200℃ in H2 atmosphere.
4. The HEMT epitaxial wafer as described in claim 1, characterized in that, The thickness of the SiO2 mesh layer is 10 nm to 100 nm; the area of the silicon substrate exposed by a single mesh is 10 to 100 μm. 2 ; and / or The thickness of the two-dimensional AlInN layer is 20 nm to 120 nm, and the proportion of In component is 0.01 to 0.2%; and / or The thickness of the first AlGaN layer is 20nm~100nm, and the proportion of its Al component is 0.01~0.1%.
5. The HEMT epitaxial wafer as described in claim 1, characterized in that, The superlattice layer has a period number of 3 to 20; and / or The thickness of a single InGaN layer is 0.5 nm to 5 nm, and the In content is 0.01 to 0.2%; and / or The thickness of a single second AlGaN layer is 5nm~15nm, and the proportion of Al component is 0.05~0.3%.
6. A method for preparing a HEMT epitaxial wafer, used to prepare the HEMT epitaxial wafer as described in any one of claims 1 to 5, characterized in that, include: Provide silicon substrates; A composite buffer layer, a channel layer, an insertion layer, a barrier layer, and a capping layer are sequentially grown on the silicon substrate. The composite buffer layer comprises a SiO2 mesh layer, a two-dimensional AlInN layer, a superlattice layer and a first AlGaN layer sequentially stacked on the silicon substrate; the superlattice layer comprises alternating InGaN layers and a second AlGaN layer. Multiple grids exposing the silicon substrate are formed on the SiO2 grid layer; The proportion of Al component in the first AlGaN layer is less than the proportion of Al component in the second AlGaN layer.
7. The method for preparing a HEMT epitaxial wafer as described in claim 6, characterized in that, The method for preparing the SiO2 mesh layer includes: A SiO2 layer is grown on the silicon substrate by PECVD; wherein the growth temperature is 200℃~300℃, the cavity pressure is 500mtorr~1000mtorr, the RF power is 20W~80W, and the flow ratio of N2O to SiH4 is 1.5~2. The SiO2 layer is etched to form multiple grids that expose the silicon substrate, resulting in a SiO2 grid layer.
8. The method for preparing a HEMT epitaxial wafer as described in claim 6, characterized in that, The two-dimensional AlInN layer, the superlattice layer, and the first AlGaN layer are all grown by MOCVD. The growth temperature of the two-dimensional AlInN layer is 700℃~900℃, and the growth pressure is 50 torr~500 torr. The growth temperature of the superlattice layer is 750℃~900℃, and the growth pressure is 50 torr~500 torr. The growth temperature of the first AlGaN layer is 800℃~900℃, and the growth pressure is 50 torr~500 torr.
9. A HEMT, characterized in that, Includes the HEMT epitaxial wafer as described in any one of claims 1 to 5.