A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, vertically arranged active pillars, a gate dielectric layer, a gate, a drain extension liner layer and a grid support structure. The gate dielectric layer is formed only in the channel region of the active pillars; the drain extension liner layer is formed on the sidewall of the drain region to increase the surface area; the grid support structure is formed outside the drain extension liner layer and comprises at least two layers of material and forms a ladder structure along the word line direction. The manufacturing method comprises the steps of forming an active pillar pattern, forming a gate dielectric layer only in the channel region, forming a drain extension liner layer and forming the multi-layer ladder grid support structure through a self-alignment process. The application significantly enhances the mechanical stability of the pillars, reduces the parasitic capacitance and leakage current and comprehensively improves the device performance and reliability by virtue of the unique structural design and self-alignment manufacturing process while effectively reducing the drain contact resistance.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device manufacturing methods, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] As semiconductor memory devices (such as dynamic random access memory, DRAM) evolve towards higher integration and smaller cell sizes, 4F² pillar transistor technology has become one of the key pathways to achieving high-density memory because it can realize a memory cell within four times the area of ​​a single minimum feature size (F) squared. In this technology, a vertical silicon pillar serves as the channel of the transistor, and its top region constitutes the drain.

[0003] However, as feature size (DR) continues to shrink, the size of the pillar and the area of ​​its top drain region also decrease dramatically. This directly leads to two significant problems: First, the resistance of the drain itself and the contact resistance (Rc) between it and the contact pad above it increase dramatically, severely limiting the read / write speed and energy efficiency of the device; second, the slender pillar structure is prone to physical bending or even collapse during subsequent complex manufacturing processes (such as deposition, etching, chemical mechanical polishing, etc.), leading to device failure and becoming a major bottleneck in process integration.

[0004] To address the issue of column bending, existing technologies propose directly constructing a single-layer mesh support structure, similar to capacitor support structures, on the column. For example, a related patent (such as US5874760A) describes a method for forming a high-density vertical transistor array using self-aligned shallow trench isolation technology. Although such designs theoretically achieve a cell area of ​​4F², directly constructing the mesh support on the active column has inherent drawbacks: first, the structure introduces additional parasitic capacitance and may exacerbate gate leakage current, degrading the device's electrical performance; second, the design of the gate length (Lg) is often limited to accommodate the mesh structure, sacrificing optimization space for device performance; and third, this "one-size-fits-all" support method has limited effectiveness in improving stress-induced column bending.

[0005] In addition, other improvement solutions, such as simply shortening the gate length or developing new grid materials, can alleviate a specific problem to some extent, but none of them fundamentally solve the core contradiction that is interconnected and mutually restrictive among the three factors: increased drain resistance, insufficient mechanical stability of the gate, and worsening parasitic effects.

[0006] Therefore, there is an urgent need for an innovative structural design and manufacturing method that can effectively improve the electrical performance of the drain side and reduce parasitic effects while ensuring the physical stability of the column, thereby promoting the practical application of 4F² columnar transistor technology. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the defects in the prior art, thereby providing a semiconductor device and a method for manufacturing the same.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] First aspect: This application provides a semiconductor device, comprising:

[0010] Substrate;

[0011] An active pillar is vertically disposed on the substrate. Multiple active pillars are disposed, and each active pillar includes a source region, a channel region, and a drain region.

[0012] A gate dielectric layer is formed around the channel region of the active pillar;

[0013] A gate is disposed around the gate dielectric layer;

[0014] A drain extension liner is formed on the sidewall of the drain region of the active pillar;

[0015] A grid support structure is formed on the outside of the drain extension pad layer, and the grid support structure includes multiple material layers;

[0016] A first oxide layer is located between the drain extension liner layer and the grid support structure.

[0017] In the above scheme, multiple vertically arranged active pillars constitute the basic unit of device integration. By confining the gate dielectric layer around the channel region of the active pillar, the gate dielectric layer does not cover its drain region, thus providing space for the formation of the drain extension pad layer on the sidewall of the drain region. The addition of the drain extension pad layer directly increases the lateral contact area of ​​the drain, helping to reduce the resistance when current flows through the drain region. At the same time, the grid support structure of at least two material layers formed outside the extension pad layer provides the necessary lateral mechanical support for the high aspect ratio active pillar, enhancing its structural stability in subsequent processes.

[0018] Furthermore, the grid support structure with at least two material layers, through its multi-layer configuration, not only provides mechanical support but also helps optimize the electric field distribution in the region and reduce the direct contact area with conductive structures at the interlayer interfaces, thus providing a structural basis for reducing parasitic capacitance. The gate is arranged around the gate dielectric layer, working synergistically with the aforementioned features to achieve a comprehensive improvement in the electrical performance and mechanical reliability of the device while ensuring gate control capability.

[0019] As expected, the ladder-like structure design brings additional benefits to the optimization of electrical performance. Its discontinuous nature reduces the contact area between the grid support structure and the drain extension liner, which directly helps to reduce the parasitic capacitance that may form between the two.

[0020] It should be noted that the surface of the drain extension liner layer needs to be oxidized to form the first oxide layer before the grid support structure is deposited.

[0021] Preferably, the material of the grid support structure includes a silicon nitride-based material, wherein the silicon nitride-based material is selected from at least one of silicon nitride, silicon carbide, silicon boron nitride, or silicon carbonitride;

[0022] And / or,

[0023] Along the direction of the character lines, the grid support structure (6) has a ladder-like structure.

[0024] In the aforementioned solutions, the materials generally possess high hardness, high chemical stability, and excellent etching selectivity. Mechanically, their high modulus provides the necessary rigidity for the mesh support structure, ensuring effective lateral support strength for the active pillars. Process-wise, their chemical stability ensures they are not easily corroded in subsequent wet or dry processing steps, while their excellent etching selectivity (especially relative to oxides and silicon) guarantees precise patterning of the mesh structure and definition of channel regions, avoiding over-etching or accidental damage to the support structure.

[0025] Furthermore, this specific material selection has a positive impact on the electrical performance of the device. Such silicon nitride-based materials typically have a moderate dielectric constant (generally higher than silicon dioxide but lower than high-k dielectrics), and when the grid support structure is inevitably adjacent to the gate or drain extension pad layer, their dielectric properties help to keep the additional parasitic capacitance introduced therefrom at a relatively low and stable level while achieving the mechanical support function, thus achieving a good balance between mechanical robustness and electrical performance.

[0026] Furthermore, the grid support structure is trapezoidal, extending in a direction parallel to the substrate. This means that its support profile has discontinuous concave-convex features within the horizontal cross-section. This specific geometry offers advantages primarily at the mechanical level: compared to continuous ring supports, the trapezoidal discontinuous support points provide anchoring at critical locations while reducing full-area contact with the column sidewalls. This effectively constrains lateral displacement of the column and prevents bending, while reducing additional stress caused by the difference in thermal expansion coefficients between the support structure and the column.

[0027] Preferably, the mesh support structure is in direct contact with the metal material of the gate in the depth direction; or, an oxide spacer layer is provided between the mesh support structure and the metal material of the gate.

[0028] In the above scheme, by limiting the mesh support structure to directly contact the gate metal material in the depth direction, a lateral auxiliary attachment interface and mechanical anchoring point are provided for the gate metal. This configuration can enhance the overall structural integrity and local rigidity of the gate stack in the vertical direction. In particular, when dealing with thermal stress in subsequent processes or service, it helps to constrain the deformation of the gate metal layer, thereby improving the long-term stability and reliability of the gate structure.

[0029] Furthermore, by placing an oxide spacer layer between the grid support structure and the gate metal material, an isolation barrier is established between the two. This oxide spacer layer can effectively block potential leakage paths generated from the gate metal through the grid support structure, ensuring the independence and accuracy of the gate control potential. At the same time, this oxide layer, as a buffer medium, can also alleviate the interface stress that may be caused by differences in material properties (such as the coefficient of thermal expansion) between the grid support structure and the gate metal, thus ensuring the mechanical integrity of the interface while achieving reliable electrical isolation.

[0030] Preferably, the thickness of the oxide layer is less than the thickness of the gate dielectric layer.

[0031] In the above scheme, by setting the thickness of the oxide layer to be less than the thickness of the gate dielectric layer, the interface characteristics between the drain extension pad layer and the grid support structure are controlled. This thickness relationship ensures that the interface oxide layer, while fulfilling its necessary electrical isolation and interface passivation functions, does not become a dominant source of parasitic capacitance in the critical capacitance path of the device. Its thinner thickness keeps its capacitance contribution at a low level, thereby minimizing its negative impact on overall device performance (such as RC delay) at the electrical level.

[0032] It should be understood that this specific thickness relationship is also significant at the process level. A thinner oxide layer is more easily and controllably partially retained or completely removed during subsequent etching processes that define the channel region, thus providing a larger process window and greater flexibility for forming clear, self-aligned device structures. This helps improve process reliability and device manufacturing yield.

[0033] Preferably, it further includes a bit line isolation structure extending along the bit line direction and a word line isolation structure extending along the word line direction;

[0034] in,

[0035] The material of the word line isolation structure is the same as or belongs to the same type of silicon nitride-based material as the material of the grid support structure.

[0036] In the above scheme, the material of the word line isolation structure and the mesh support structure are the same or belong to the same type of silicon nitride-based material, achieving uniformity or high compatibility of the material system between the key support structure and the isolation structure. Firstly, at the process level, this significantly simplifies the material deposition and patterning process, reducing process complexity and manufacturing costs. Secondly, it avoids the interfacial stress mismatch problem that may arise from using multiple heterogeneous materials, which helps improve the interfacial thermomechanical stability between the isolation structure, the mesh support structure, and the surrounding medium, thereby enhancing the structural reliability of the entire device during thermal cycling.

[0037] Preferably, the drain extension pad layer is a silicon layer formed by selective epitaxial growth or chemical vapor deposition.

[0038] In the above scheme, the drain extension pad is a silicon layer formed by selective epitaxy (SEG) or chemical vapor deposition (CVD), providing two mature and controllable process paths for the formation of a high-quality extension layer. Selective epitaxy allows for crystallographic matching directly on the exposed single-crystal silicon drain region, resulting in an extension layer with perfect crystal continuity and extremely low defect density with the original drain, thus achieving the lowest contact resistance and excellent electrical interface characteristics. Chemical vapor deposition provides another highly conformal coverage capability, forming a uniform and dense silicon layer on complex three-dimensional surface structures, ensuring precise control over the thickness and morphology of the drain extension pad, and effectively increasing the electrical contact area.

[0039] Furthermore, all of the above methods possess excellent process compatibility and scalability. Selective epitaxial growth enables self-aligned region-selective deposition without additional patterning steps, simplifying the process flow. Chemical vapor deposition (CVD) offers good tolerance for front-end process morphology, a wide process window, and easy integration into mass production processes. Both methods can reliably form drain extension pads, providing a solid and feasible manufacturing foundation for reducing drain series resistance and improving device performance and consistency.

[0040] Second aspect: This application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0041] A substrate is provided, and an active column pattern is formed on the substrate;

[0042] A gate dielectric layer is formed only in the channel region of the active column;

[0043] A drain extension liner layer is formed on the sidewall of the drain region of the active column by selective epitaxial growth or chemical vapor deposition.

[0044] A grid support structure with multiple dielectric material layers and a ladder-like structure along the word line direction is formed on the outside of the drain extension pad layer through a self-aligned process.

[0045] In the above scheme, the step of "forming a gate dielectric layer only in the channel region of the active pillar" is a core design that differs from traditional processes. This step reserves space for subsequent structural enhancement in the drain region and is a prerequisite for achieving low-resistance drain contacts and a high-stability support structure. The step of "forming a drain extension pad layer on the sidewall of the drain region" directly affects the electrical performance of the device. Through the defined selective epitaxial growth or chemical vapor deposition method, a silicon layer is controllably grown in the drain region, substantially increasing the effective surface area of ​​the drain. This is a key process for directly reducing drain series resistance and contact resistance. The step of "forming a multi-layer mesh support structure on the outside of the drain extension pad layer through a self-aligned process" constructs a multi-layer composite structure that combines mechanical support and optimized electrical interface functions without the need for additional photolithography masks. This self-aligned process not only simplifies the process and improves integration accuracy, but also the multi-layer mesh support structure effectively enhances the mechanical stability of the pillar and helps control parasitic capacitance, achieving synergistic optimization of device electrical performance improvement and mechanical reliability enhancement.

[0046] Preferably, the step of forming the active column pattern includes:

[0047] A silicon-germanium layer and a silicon layer are sequentially formed on the substrate;

[0048] Using the silicon-germanium layer as an etch stop layer, the silicon layer is etched along the bit line direction to form a first gap;

[0049] After filling the first gap, etching is performed along the word line direction perpendicular to the bit line direction to form a second gap, wherein the bottom depth of the second gap is less than the bottom depth of the first gap.

[0050] In the above scheme, by sequentially forming a silicon-germanium layer and a silicon layer on the substrate, a key material foundation and stop layer are established for subsequent processes. Bit line etching is performed using the silicon-germanium layer as the etch stop layer. By utilizing the significant etch selectivity between silicon and silicon-germanium, the etching process can be automatically and precisely stopped when a preset depth is reached, thereby forming a first gap with uniform depth and controllable morphology. After filling the first gap, word line etching is performed, which allows for the self-alignment and definition of independent pillars at the intersection points.

[0051] Specifically, by making the bottom depth of the second gap less than that of the first gap, the bottom of the final column has a non-flat, stepped support base in three-dimensional space. This provides additional mechanical anchoring effect for the column in subsequent processes, further enhancing its resistance to lateral stress. It also helps to optimize the stress distribution of the subsequent filling material, thus improving the robustness of the overall structure from the molding stage.

[0052] Preferably, the step of forming the ladder-shaped grid support structure includes:

[0053] The surface of the drain extension pad layer is oxidized to form a first oxide layer;

[0054] A silicon nitride-based material layer is deposited on the first oxide layer;

[0055] The silicon nitride-based material layer is etched back to define a ladder-like structure;

[0056] The thickness of the first oxide layer is less than the thickness that can be removed by the subsequent oxide etch-back process to expose the trench region, so that the first oxide layer is retained under the grid support structure.

[0057] In the above scheme, the step of partially oxidizing the drain extension pad layer to form an oxide layer first generates a dense, high-quality dielectric layer with low interface states on the silicon surface. This dielectric layer serves as the substrate for subsequent silicon nitride-based material deposition, optimizing interface bonding quality and providing electrical isolation. Next, a silicon nitride-based material layer is deposited. This material, due to its high mechanical strength and good chemical stability, is selected as the main structural material for the mesh support. Subsequently, the silicon nitride-based material layer is etched back to define the mesh shape. This step precisely forms the desired ladder-like or mesh-like sidewall contours through anisotropic etching, thereby simultaneously achieving the electrical design goals of mechanical support and reducing contact area.

[0058] Crucially, the oxide layer thickness is limited to a thickness smaller than that removed by the subsequent oxide etch-back process for channel formation. This ensures that while the oxide in the exposed areas is removed to open the channel region during the subsequent global oxide etch-back step, the portion of the oxide layer beneath the silicon nitride mesh is preserved. This retained thin oxide layer acts as a permanent interface passivation layer, stabilizing the interface between the drain-extended silicon and the silicon nitride mesh. It also serves as a stress buffer layer, mitigating stress caused by differences in the thermal expansion coefficients of the materials. Furthermore, it acts as a defined electrical isolation layer, ensuring electrical insulation between the drain and the mesh support structure. This is vital for suppressing leakage current and reducing parasitic capacitance, ensuring that the multilayer mesh support structure achieves excellent mechanical properties while its electrical behavior is precisely optimized and controlled.

[0059] Preferably, the manufacturing method further includes the following steps:

[0060] A gate is formed surrounding the gate dielectric layer, wherein the sidewalls of the gate are in direct contact with the grid support structure in the depth direction, or an oxide spacer layer is formed between the gate and the grid support structure.

[0061] In the above scheme, by providing two specific interface configuration options between the gate and the grid support structure, key process determinism and electrical reliability are guaranteed for the integration of the gate.

[0062] The direct contact between the gate sidewall and the grid support structure forms a stable mechanical connection interface with a large contact area, which can effectively enhance the lateral stability of the gate stack. In particular, when dealing with the thermal budget of subsequent processes, it helps to suppress the deformation or peeling of the gate metal due to stress.

[0063] Alternatively, an oxide spacer layer can be formed between the two, creating a defined, high-performance electrical isolation barrier. This oxide layer blocks potential leakage current paths from the gate to the grid support structure, ensuring the absolute independence of the gate control potential and signal integrity. At the same time, the oxide layer also acts as a stress buffer layer, mitigating interface defects that may be caused by direct contact between two different materials.

[0064] The two preset configurations mentioned above provide proven and flexibly selectable optimization solutions to address the conflicting requirements of mechanical stability and electrical isolation in gate integration.

[0065] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0066] 1. A drain extension pad layer is formed on the sidewall of the drain region of the active pillar, which increases the drain surface area and reduces the drain resistance and the contact resistance between the drain and the pad.

[0067] 2. The ladder-shaped grid support structure can prevent the source pillars from physically bending in subsequent processes, and can also improve the design freedom of the gate length of the device. In addition, the word line side can achieve self-alignment during the gate metal etch-back process, which improves process deviation and device characteristic deviation.

[0068] 3. The grid support structure using silicon nitride-based materials can reduce parasitic capacitance and leakage current generated at the drain terminal;

[0069] 4. The mesh support structure is in direct contact with the metal material of the gate or through an oxide spacer layer in the depth direction, which optimizes the electrical connection performance of the device;

[0070] 5. The oxide layer thickness between the drain extension pad layer and the grid support structure is smaller than the gate dielectric layer thickness, which helps to accurately control the electrical characteristics of the device;

[0071] 6. The word line isolation structure and the grid support structure use the same or similar silicon nitride-based materials, which enhances the structural stability and electrical consistency of the device;

[0072] 7. By selectively epitaxially growing or chemically vapor-depositing to form a drain electrode extension liner, the surface area of ​​the drain electrode region can be effectively increased;

[0073] 8. In the manufacturing method, a silicon-germanium layer is used as an etch stop layer to form gaps, which can precisely control the pattern of the active pillars;

[0074] 9. During the formation of the multi-layer mesh support structure, some of the oxide layers formed by oxidation are retained below the mesh support structure, which helps to ensure the performance and stability of the device. Attached Figure Description

[0075] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0076] Figure 1 This is a vertical cross-sectional view of the back bit line of a 4F² vertical channel transistor dynamic random access memory array in the prior art, in the bit line direction.

[0077] Figure 2 This is a vertical cross-sectional view of the back bit line of the 4F² vertical channel transistor dynamic random access memory array in this embodiment, taken in the bit line direction.

[0078] Figure 3 This is a schematic diagram of the zero-layer structure in this embodiment.

[0079] Figure 4 This is a vertical cross-sectional view of the bitline layer in the bitline direction in this embodiment.

[0080] Figure 5 This is a vertical cross-sectional view of the character line layer in the character line direction in this embodiment.

[0081] Figure 6 This is a vertical cross-sectional view of the active mesh structure in the bitline direction in this embodiment.

[0082] Figure 7 This is a top view of the active mesh structure in this embodiment.

[0083] Figure 8 This is a vertical cross-sectional view of the active mesh structure in the word line direction in this embodiment.

[0084] Explanation of reference numerals in the attached figures:

[0085] 1. Substrate; 2. Active pillar; 3. Gate dielectric layer; 4. Gate electrode; 5. Drain extension pad layer; 6. Mesh support structure;

[0086] 21. Source region; 22. Channel region; 23. Drain region;

[0087] 10. Substrate silicon layer; 20. Silicon-germanium epitaxial layer; 30. Silicon epitaxial layer; 40. Pad oxide layer; 50. Silicon nitride layer; 60. Interstitial filler; 70. ALD silicon nitride layer; 80. ALD oxide layer. Detailed Implementation

[0088] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0089] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0090] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0091] The core of this invention is to provide a semiconductor device.

[0092] Another core aspect of this invention is to provide a method for manufacturing a semiconductor device, used to manufacture the aforementioned semiconductor device.

[0093] With the development of semiconductor memory devices, especially dynamic random access memory (DRAM), towards higher densities and smaller cell sizes, the 4F² (where F is the minimum feature size) cylindrical transistor architecture has become a key technological path for realizing high-density memory cells. In this architecture, the vertical silicon pillars simultaneously serve as the channel and source / drain regions of the transistor, theoretically enabling the realization of all transistor functions within a very small footprint.

[0094] In existing technologies, such as those disclosed in US Patent 5874760A, a self-aligned shallow trench isolation technique is used to form a square vertical pillar array on a silicon substrate. Each pillar is surrounded by a gate-around stack structure (including a gate dielectric and a gate electrode), with the drain located at the top of the pillar and the source located on the substrate. This design achieves a true 4F² cell area, laying the foundation for high-density memory arrays.

[0095] However, as process nodes continue to evolve and feature dimensions continue to shrink, the physical dimensions (diameter and height) of the column also shrink proportionally, which raises a series of interconnected and serious problems:

[0096] The drastic reduction in the area of ​​the drain region at the top of the cylinder leads to a significant increase in the drain's series resistance. Simultaneously, this reduced area also causes a sharp increase in the contact resistance between the drain and the upper contact pad. The combined effect of these two resistances severely degrades the device's current drive capability and read / write speed, limiting memory performance improvements.

[0097] Mechanical stability bottleneck: As the cylindrical structure becomes increasingly slender, it is highly susceptible to physical bending or even collapse during subsequent complex manufacturing processes (such as thin film deposition, etching, and chemical mechanical polishing). This structural failure directly leads to device scrapping and has become a key process bottleneck restricting the mass production of 4F² cylindrical transistor technology.

[0098] In current common solutions to address column bending, the industry typically attempts to directly construct a single-layer mesh or support structure on the column. However, this simple support solution introduces new problems:

[0099] Parasitic effects are amplified: the directly constructed support structure forms additional parasitic capacitance between the active pillar and the gate, which may become a path for leakage current, degrading the electrical characteristics of the device, especially dynamic power consumption and signal integrity.

[0100] Design freedom is limited: In order to accommodate the support structure, the design of key dimensions such as gate length is often constrained, making it difficult to optimize device performance and sacrificing the switching characteristics of transistors;

[0101] Limited improvement effect: Single-layer support has limited effect on resisting column bending caused by complex process stress, and its material selection is limited by process compatibility.

[0102] Therefore, while attempting to solve mechanical stability (bending resistance), existing technologies often sacrifice electrical performance (high resistance, large parasitic effects) or design flexibility, failing to fundamentally and synergistically resolve this series of contradictions.

[0103] In the existing technology, please refer to Figure 1 (Previous generation 4F²VCTDRAM array structure). In this typical prior art solution, the fabrication process of the gate dielectric layer 3 has significant limitations: it extends along the sidewall of the active pillar 2, from the source region 21 through the channel region 22, and covers the top drain region 23. This structural design introduces two interrelated serious problems:

[0104] The reduction in effective drain area and the surge in resistance: The coverage of drain region 23 by gate dielectric layer 3 effectively encroaches on the already extremely limited conductive area of ​​the drain sidewalls due to the shrinking feature size. This directly leads to a significant increase in the series resistance of the drain itself. At the same time, the reduced contact area also causes a sharp increase in the contact resistance between the drain and the upper contact pad, severely degrading the device's current drive capability and read / write speed.

[0105] Process flow and structural bottlenecks: Based on the aforementioned structure, gate metal is further fabricated to complete the MOS structure, and pads and capacitors are built. Finally, bit lines are fabricated on the back side of the wafer. However, as process nodes shrink, the aspect ratio of the pillars continuously increases, making them prone to physical bending in subsequent processes. To address this issue, the industry typically attempts to directly construct simple support structures on the pillars, but this introduces additional parasitic capacitance and leakage current, and limits the design optimization space for the gate 4 length.

[0106] Therefore, existing technologies have always struggled to achieve a good balance between high electrical performance (low resistance), high mechanical reliability (bending resistance), and low parasitic effects. Figure 1 The structure shown and its derived process solutions have become a key bottleneck restricting the further improvement of the performance of 4F² cylindrical transistors and their reliable mass production.

[0107] See Figures 2 to 8This invention provides a semiconductor device including a substrate 1, an active pillar 2, a gate dielectric layer 3, a gate 4, a drain extension pad layer 5, and a grid support structure 6. The active pillar 2 is vertically disposed on the substrate 1, and multiple active pillars 2 are provided. Each active pillar 2 includes a source region 21, a channel region 22, and a drain region 23. The gate dielectric layer 3 is formed in the channel region 22 of the active pillar 2. The gate 4 is disposed around the gate dielectric layer 3. The drain extension pad layer 5 is formed on the sidewall of the drain region 23 of the active pillar 2. The grid support structure 6 is formed on the outside of the drain extension pad layer 5 and includes multiple material layers. Along the word line direction, the grid support structure 6 has a ladder-like structure, and a first oxide layer is located between the drain extension pad layer 5 and the grid support structure 6.

[0108] Specifically, substrate 1 is a semiconductor material, such as a silicon substrate. Multiple active pillars 2 are arranged vertically in an array on substrate 1. Each active pillar 2 is a vertical pillar structure, with its lower portion in contact with substrate 1 forming a source region 21, its middle portion forming a channel region 22, and its top portion forming a drain region 23. A gate dielectric layer 3 (e.g., silicon oxide) continuously covers the surrounding surface of the channel region 22. A gate 4 (e.g., metal or heavily doped polysilicon) surrounds and covers the gate dielectric layer 3. A drain extension pad layer 5 (e.g., epitaxial silicon) completely covers the sidewalls of the drain region 23 and is connected to the top surface of the drain region 23. A mesh support structure 6 surrounds and directly contacts the outer surface of the drain extension pad layer 5. The mesh support structure 6 has a composite layered structure consisting of at least two stacked material layers in a direction perpendicular to substrate 1. From a viewing angle parallel to substrate 1 and along the word line direction, the outline of the mesh support structure 6 appears as a trapezoidal pattern composed of alternating continuous protrusions and depressions. The ladder-shaped structure provides effective lateral support for the drain region 23 of the active column 2.

[0109] Optionally, the substrate 1 is a single-crystal silicon substrate 1, or it can be a silicon-on-insulator, silicon carbide, or gallium nitride-based substrate 1; its surface flatness meets the requirement that the roughness Ra after chemical mechanical polishing is ≤0.2nm, and the thickness can be set to 500μm~750μm according to process requirements. This application embodiment does not make any special limitation on this.

[0110] Optionally, the active pillar 2 is a vertically extending silicon-based pillar, and its cross-sectional shape can be circular, elliptical, rectangular, or polygonal; its height is 80nm to 200nm, and its diameter or equivalent width is 30nm to 60nm; the active pillar 2 is formed by patterning the silicon epitaxial layer 30 through a dry etching process, and a silicon-germanium layer is used as the etching stop layer; each active pillar 2 includes a source region 21, a channel region 22, and a drain region 23 in sequence along the vertical direction. The three are vertical partitioned structures formed by different doping processes of homogeneous silicon materials, wherein the source region 21 and the drain region 23 are heavily doped n-type or p-type regions, and the channel region 22 is a lightly doped or intrinsic silicon region; the number of active pillars 2 is set according to the storage array density requirements, for example, in a 4F² cell structure, they are arranged in rows and columns, with each column containing 128 to 512 active pillars 2.

[0111] Optionally, the gate dielectric layer 3 is formed only in the channel region 22 of the active pillar 2, and does not cover the source region 21 and the drain region 23; its material is silicon dioxide, a high dielectric constant material, or a stack thereof, for example... , Its thickness is 1.2nm to 3.0nm, and it can be formed by atomic layer deposition or thermal oxidation process; the gate dielectric layer 3 continuously covers the sidewalls and top of the channel region 22 to ensure gate control capability; its lateral boundary is defined by self-aligned etch-back process, the bottom terminates at the lower boundary of the channel region 22, and the top terminates at the upper boundary of the channel region 22, thus strictly limiting its action only to the channel region 22.

[0112] Optionally, the gate 4 is a metal gate 4, which is disposed around the gate dielectric layer 3 in a fully enclosed configuration; its material includes at least one of tungsten, titanium nitride, tantalum nitride or cobalt; it is filled in the gaps around the channel region 22 by atomic layer deposition combined with chemical mechanical polishing process; the length of the gate 4 in the depth direction (i.e. the gate 4 length) is 10nm to 25nm, which is independent of the overall height of the active pillar 2 and can be adjusted without changing the pillar structure, thereby improving the device design freedom.

[0113] Optionally, the drain extension pad layer 5 is formed on the sidewall of the drain region 23 of the active pillar 2, without covering the top surface of the drain region 23 and the channel region 22; its material is monocrystalline silicon, polycrystalline silicon or amorphous silicon, and it is formed by selective epitaxial growth or chemical vapor deposition process; its thickness is 5nm to 15nm, and it is uniformly covered along the sidewall of the drain region 23; the drain extension pad layer 5 is used to increase the effective surface area of ​​the drain region 23, thereby reducing the drain resistance itself and the contact resistance of subsequent metal contacts; its formation process does not interfere with the gate dielectric layer 3 and the gate 4, avoiding the introduction of additional photolithography overlay errors.

[0114] Optionally, the mesh support structure 6 is formed on the outside of the drain extension pad layer 5, that is, between the drain extension pad layer 5 and the peripheral isolation structure; the mesh support structure 6 includes multiple material layers, from the inside out: a first oxide layer and a silicon nitride-based material layer; the first oxide layer is obtained by partial oxidation of the drain extension pad layer 5, with a thickness of 2nm to 8nm, which is less than the thickness that can be removed by the subsequent oxide etch-back process to form the channel, and thus is retained in the final structure; the silicon nitride-based material layer is selected from at least one of silicon nitride, silicon carbide, boron silicon nitride, or silicon carbonitride, and is formed by atomic layer deposition. The structure consists of a multilayer material layer with a thickness of 10nm to 30nm. This multilayer material layer together forms a grid support structure 6 with a trapezoidal cross-section. In a plane parallel to the substrate 1, it presents a periodic alternating arrangement of openings and support arms. The opening area is used for subsequent word line / bit line routing, and the support arm area provides mechanical constraints. The grid support structure 6 can directly contact the metal material of the gate 4 in the depth direction, or an oxide spacer layer can be set between the two. Its overall structure not only provides radial support for the active pillar 2 to suppress bending, but also reduces the parasitic capacitance and leakage current between the gate 4 and the drain by regulating the interface electric field distribution through multilayer dielectric materials.

[0115] Furthermore, the cross-section of the mesh support structure 6 in the plane parallel to the substrate 1 is a trapezoidal structure. This means that in the horizontal cross-section perpendicular to the normal direction of the substrate 1 (i.e., the Z direction), the sidewall contour of the mesh support structure 6 along the extension direction of the letter line has a stepped or sloping continuous transition shape, with at least one step surface or a gradually inclined surface. Its width gradually increases or smoothly expands from the side near the drain extension pad layer 5 to the side away from the drain extension pad layer 5. The step height, step width, inclination angle and number of steps of the trapezoidal structure are not particularly limited and can be set according to the actual process window, stress distribution requirements and self-alignment accuracy requirements. For example, it can be a single-level step structure, or a two-level or multi-level step structure, or a sloping structure with a continuous linear inclination angle of 5° to 30°. The inclination angle is adjusted according to the conformal preservation capability of silicon nitride-based material deposition and etch-back. This application embodiment does not make any special limitations on this.

[0116] The ladder-like structure is arranged along the word line direction, with the innermost layer directly adjacent to the outer surface of the drain extension pad layer 5. The projected profile of this structure in the word line direction partially overlaps or is closely adjacent to the projected profile of the word line isolation structure in the same direction, so as to jointly bear the anisotropic mechanical load from the word line metal filling and CMP process. Each step or inclined section of the ladder-like structure is made of the same silicon nitride material, or is formed by stacking multiple layers of silicon nitride material. The interfaces between the layers are continuous and without voids. Its formation depends on the anisotropic removal behavior of the oxide / silicon nitride stack by the self-aligned etching back etching process. Specifically, by controlling the back etching gas composition, bias power and time parameters, the etching front exhibits non-uniform advancement characteristics in the WL direction, thereby naturally forming a ladder-like morphology.

[0117] The positional relationship between the top boundary of the ladder structure and the gate 4 in the depth direction satisfies the following: after the secondary etch-back of the oxide is completed, the depth of the top surface of the highest step or the top of the slope of the ladder structure is not lower than the top depth of the gate dielectric layer 3 and not higher than the bottom depth of the gate metal layer 4. This depth relationship ensures that the ladder structure provides mechanical support without interfering with the gate dielectric integrity of the channel region 22 and the electrical connection of the gate 4. Its specific depth can be controlled synergistically by adjusting the initial oxide layer thickness, silicon nitride deposition thickness and etch-back amount.

[0118] The cross-sectional shape of the ladder-like structure in the bit line direction is different from that in the word line direction. In the cross-section in the bit line direction, the grid support structure 6 is approximately rectangular or has a straight edge structure with rounded corners, and its sidewalls are basically perpendicular to the surface of the substrate 1. This anisotropic cross-sectional shape is due to the difference between the bit line gap and the word line gap in terms of etching depth, termination layer response and subsequent oxidation / deposition conformality. In particular, the bottom morphology caused by the bit line etching with the silicon-germanium layer as the termination layer makes it difficult to form a ladder-like profile in the BL direction, while the WL direction is more likely to achieve ladder-like evolution due to deeper etching and the stacked response of ALD oxide / silicon nitride.

[0119] In the aforementioned semiconductor device, since the gate dielectric layer 3 is limited to the channel region 22 and does not encroach on the top space of the drain region 23, the drain extension pad layer 5 can effectively expand its surface area in the sidewall direction, thereby significantly reducing the drain resistance and contact resistance. Because the mesh support structure 6 is composed of multiple layers of materials arranged in a ladder-like pattern, compared to a single-layer structure, it provides the same mechanical support strength while reducing the direct contact area between the high-dielectric-constant material and the gate 4 metal, thus suppressing parasitic capacitance growth. Since the oxide layer thickness in the multilayer structure is controlled and retained in the final device, it ensures both the electrical continuity of the drain extension region and maintains effective electrical isolation in the gate process. Because the entire structure is implemented through a self-aligned process, it avoids… The photolithography overlay error improved the spatial alignment accuracy between the active pillar 2, the drain extension pad layer 5, and the grid support structure 6. Because the grid support structure 6 has a trapezoidal cross-section in a plane parallel to the substrate 1, it forms a sidewall interface with gradually varying support stiffness in the word line direction. On the one hand, this disperses concentrated stress to a larger contact area during word line metal deposition and CMP, significantly suppressing lateral displacement or bending of the active pillar 2. On the other hand, this trapezoidal profile serves as a physical mask in the subsequent gate 4 metal etch-back process, guiding the etching front to self-align and stop along the ramp or step edge, reducing the impact of photolithography overlay errors on the morphology of the word line-side gate 4, thereby improving the consistency of critical device dimensions and the uniformity of electrical parameter distribution. Ultimately, while maintaining the 4F² cell area, electrical performance, process robustness, and device reliability were simultaneously improved.

[0120] The semiconductor device provided by the present invention will now be described in more detail with reference to the accompanying drawings and specific embodiments.

[0121] In one specific embodiment, the material of the grid support structure 6 includes a silicon nitride-based material, which is selected from at least one of silicon nitride, silicon carbide, silicon boron nitride, or silicon carbonitride.

[0122] Specifically, the silicon nitride-based material layer serves as at least one layer in a multilayer material structure. This type of material was chosen based on its comprehensive physical and electrical properties: it possesses high mechanical strength and hardness, providing robust lateral support for the active pillar 2 and effectively resisting subsequent process stresses, thereby suppressing pillar bending. Simultaneously, compared to conventional dielectric materials (such as silicon oxide), this type of material typically exhibits superior chemical stability and etching selectivity, facilitating precise patterning and structural definition in integrated circuit processes. Furthermore, silicon nitride-based materials have a moderate dielectric constant; applying them to the grid support structure 6 helps to achieve mechanical support while avoiding the introduction of excessively high parasitic capacitance, thus reducing the overall parasitic effects of the device and improving electrical performance.

[0123] The material of the grid support structure 6 includes silicon nitride-based materials, which means that at least one layer of the material constituting the grid support structure 6 is a silicon nitride-based material. The silicon nitride-based material can serve as the main support layer, dielectric isolation layer or stress control layer in the grid support structure 6. Its specific function depends on its position in the multilayer material layers and the physicochemical properties of the adjacent material layers.

[0124] Silicon nitride is an inorganic non-metallic material with high Young's modulus, good thermal stability, and moderate dielectric constant. Its stoichiometry can be... Silicon nitride can be either silicon-rich or nitrogen-rich to suit different etching selectivity and dielectric performance requirements under different process windows. It can be formed through atomic layer deposition, chemical vapor deposition, or physical vapor deposition, with a thickness of [missing information]. , or .

[0125] Silicon carbide nitrogen is a ternary compound formed by introducing carbon atoms into the SiN lattice. Its carbon content can be controlled according to the precursor ratio and process parameters, with a typical range of [missing information]. The introduction of carbon can further improve the hardness and oxidation resistance of the material and reduce the dielectric constant, thereby reducing parasitic capacitance while maintaining mechanical support strength. SiCN can be prepared by ALD using silicon source, carbon source and nitrogen source co-reaction, and its density and stress state can be adjusted according to the annealing temperature.

[0126] Boron silicon nitride is a composite nitride system containing boron, nitrogen, and silicon. The boron element can be derived from the BN microcrystalline phase or the B–N–Si solid solution phase. This material combines the high thermal conductivity of BN with the excellent adhesion of SiN, which can alleviate the thermal mismatch stress at the interface of multilayer structures. It is suitable for applications that require both thermal management and low K. It can be achieved through co-sputtering or pulsed laser deposition, and the composition ratio is adjustable.

[0127] Silicon carbonitride is a non-stoichiometric compound in which carbon and nitrogen are co-doped in a silicon-nitrogen network. Its structure contains various bonding modes such as Si–C, Si–N, and C–N, and it can exhibit diamond-like or ceramic-like properties. This material exhibits excellent selectivity in dry etching, which is beneficial for accurately defining the mesh shape in subsequent etching processes. It can be achieved by combining carbon precursors with plasma-enhanced CVD or ALD.

[0128] Silicon nitride-based materials are selected from at least one of the four materials mentioned above, including but not limited to: single material layer (such as pure SiN layer), two-component stack (such as SiN / SiCN alternating layer), gradient component layer (continuous transition from SiN to SiCN), or nanocomposite layer (such as BN nanodomains dispersed in SiCN). The thickness, interface roughness, and crystallinity (amorphous / microcrystalline) of each material layer can be adjusted according to actual process conditions and device performance targets. For example, amorphous state can be used to suppress grain boundary leakage, or controllable microcrystals can be introduced to improve elastic modulus.

[0129] By constructing a grid support structure 6 using silicon nitride-based materials with high mechanical strength, controllable dielectric constant, and good process compatibility, the structure provides effective bending support while significantly suppressing the growth of parasitic capacitance and the formation of illegal current paths between the gate 4 and the drain extension region. Especially in high-temperature back-end processes, the material system maintains structural integrity and interface stability, avoiding support failure or leakage current deterioration caused by material interdiffusion or phase transition, thereby ensuring the electrical reliability and long-term operational stability of the device at a miniaturized scale.

[0130] In one specific embodiment, the mesh support structure 6 is in direct contact with the metal material of the gate 4 in the depth direction.

[0131] Specifically, in the final structure of the semiconductor device, after the gate 4 is formed, a portion of its sidewalls in the depth direction are directly adjacent to and in physical contact with the corresponding sidewalls of the mesh support structure 6, without a continuous and complete isolation layer made of dielectric material between them. This direct contact interface is naturally formed during the metal deposition and filling process of the gate 4. This configuration allows the mesh support structure 6 to not only support the drain extension pad layer 5 and the active pillar 2, but also to provide direct lateral auxiliary support for the gate 4. This structure helps to improve the structural stiffness and thermomechanical stability of the gate 4 outside the channel region 22, thereby potentially enhancing the reliability of the entire device during manufacturing and service. The interface relationship of the direct contact is as follows: Figure 2 As shown, the gate 4 metal extends to connect with the outer ladder-shaped mesh support structure 6.

[0132] The mesh support structure 6 is in direct contact with the metal material of the gate 4 in the depth direction. This means that the bottom layer material surface of the mesh support structure 6 and the metal material surface of the gate 4 are in physical contact in the direction perpendicular to the substrate 1, without any continuous dielectric layer or barrier layer sandwiched between them. This contact method is suitable for manufacturing scenarios with high requirements for device integration density and high cleanliness process environment and high-quality interface passivation capability. For example, after using atomic layer deposition to grow silicon nitride-based materials in situ and simultaneously implementing plasma interface treatment, the interface state density can be effectively reduced and the leakage current of the gate 4 can be suppressed.

[0133] In one specific embodiment, an oxide spacer layer is provided between the metal material of the mesh support structure 6 and the gate 4.

[0134] Specifically, during the semiconductor device manufacturing process, an oxide layer is formed on the corresponding sidewall of the grid support structure 6 before or after the metal material of the gate 4 is formed. This oxide layer serves as a spacer layer, located between the grid support structure 6 and the subsequently formed metal sidewall of the gate 4. Therefore, in the depth direction perpendicular to the substrate 1, the gate 4 and the grid support structure 6 are physically separated by this oxide spacer layer. This provides electrical isolation between the metal material of the grid support structure 6 and the gate 4, effectively blocking potential leakage current paths between them, thereby ensuring the independence of the gate control signal and the reliability of device operation. Simultaneously, this oxide spacer layer also serves as a stress buffer layer, helping to alleviate thermal mismatch stress between different materials.

[0135] It should be understood that the oxide spacer layer between the mesh support structure 6 and the metal material of the gate 4 refers to the formation of a continuous, dense oxide layer with controllable thickness between the top layer of the mesh support structure 6 and the bottom layer of the metal material of the gate 4. The material of the oxide spacer layer is silicon dioxide, and its thickness is 0.5nm to 3nm, or 1nm to 2nm. This application does not make any special limitation on this. The thickness range must meet the following requirements: it is sufficient to block the direct tunneling path between the metal and the silicon nitride material, and it will not significantly increase the equivalent oxide layer thickness or introduce additional stress due to excessive thickness. The oxide spacer layer can be formed by in-situ thermal oxidation, ALD deposition or plasma oxidation. Its formation time is after the mesh support structure 6 has completed the etch-back and before the metal deposition of the gate 4.

[0136] It should be noted that the "direct contact" and "setting an oxide spacer layer" in the above two embodiments are two mutually exclusive structural configuration options, and the two cannot coexist in the same device structure. In the actual manufacturing process, the process path can be switched according to the application requirements of the target device (such as high-performance logic cells tend to choose direct contact to improve driving capability, while high-reliability memory cells tend to choose oxide spacer layers to suppress off-state leakage). There is no need to modify the photolithography mask or reconstruct the core process module. It can be achieved simply by adjusting the combination order of the deposition and oxidation steps.

[0137] When using a direct-contact structure, optimized interface engineering controls can maintain high integration while ensuring gate control stability. When using an oxide spacer structure, high barrier height and low defect density are introduced. The layer significantly suppresses the direct tunneling current and hot electron injection between the gate 4 metal and the silicon nitride-based mesh support structure 6, thereby reducing the off-state leakage current and improving the device's switching ratio and long-term operational reliability.

[0138] In one specific embodiment, a first oxide layer is further included between the drain extension pad layer 5 and the grid support structure 6, the thickness of which is less than the thickness of the gate dielectric layer 3.

[0139] Specifically, the first oxide layer existing between the drain extension pad layer 5 and the mesh support structure 6 is formed by a partial oxidation process on the silicon surface of the drain extension pad layer 5. This first oxide layer is grown directly on the surface of the drain extension pad layer 5 and is located between it and the inner material layer of the mesh support structure 6. Its thickness is less than that of the gate dielectric layer 3, ensuring that while the first oxide layer acts as an interface buffer layer to achieve physical isolation and passivation, it does not become a dominant source of parasitic capacitance in the critical capacitance path of the device, thereby reducing its negative impact on the overall device performance. In addition, this thinner thickness also allows for better process control and selectivity in subsequent process steps (such as global oxide etchback to expose the channel region 22).

[0140] It should be understood that the first oxide layer is formed between the outer surface of the drain extension pad layer 5 and the inner surface of the mesh support structure 6 to provide electrical isolation and interface stress buffer between the two. The material of the first oxide layer is silicon dioxide, which is formed by atomic layer deposition or thermal oxidation process, and the thickness ranges from 1nm to 5nm. This thickness can be set according to the actual process window, thermal budget and etching selectivity of subsequent oxide etch-back process, for example, it can be 2nm or 3nm. This application embodiment does not make special limitations on this. The thickness of the gate dielectric layer 3 is 6nm to 10nm. Therefore, the thickness of the first oxide layer is less than the thickness of the gate dielectric layer 3 to ensure that it only undertakes the local interface isolation function and does not replace the main insulation function of the gate dielectric layer 3. The first oxide layer undergoes at least one oxide etch-back process in the subsequent manufacturing process. The thickness of the first oxide layer is less than the maximum thickness that can be completely removed by the etch-back process, so that it is partially retained below the channel region 22 and the bottom of the gate 4, and used as one of the positioning reference layers for the subsequent formation of the gate dielectric layer 3 and the gate 4 metal layer.

[0141] The first oxide layer and the drain extension pad layer 5 form a direct contact interface without an intermediate transition layer. The first oxide layer and the mesh support structure 6 also form a direct contact interface. Furthermore, since the mesh support structure 6 is made of silicon nitride, the first oxide layer... The interface can effectively alleviate the stress concentration caused by the mismatch of thermal expansion coefficients and suppress the generation of microcracks at the heterogeneous interface. In optional embodiments, the first oxide layer can also be replaced with phosphorus-doped silicon dioxide, boron-doped silicon dioxide or silicon oxynitride. Its dielectric constant and thermal stability must meet the requirement that it does not flow or decompose significantly in subsequent high-temperature processes, and maintain good interface compatibility with adjacent silicon-based and silicon nitride materials.

[0142] The lateral coverage of the first oxide layer is consistent with the sidewall contour of the drain extension pad layer 5, extends continuously along the sidewall of the drain region 23 of the active pillar 2, and surrounds the entire drain extension pad layer 5. Its top end is at the top edge of the drain extension pad layer 5, and its bottom end is at the bottom edge of the drain extension pad layer 5. It does not extend upward to the channel region 22, nor downward to the source region 21. In an optional embodiment, the oxide layer can achieve a thickness gradient distribution by controlling the oxidation time, temperature, or number of ALD cycles. For example, the thickness near the top region is slightly larger, and the thickness near the bottom region is slightly smaller, in order to adapt to the stress distribution differences at different height positions. This application embodiment does not make any special limitation in this regard.

[0143] As is expected, a first oxide layer with controlled thickness is introduced between the drain extension pad layer 5 and the grid support structure 6. This first oxide layer can provide stable electrical isolation between the two, reduce the risk of lateral leakage current in the drain, and alleviate the interfacial thermal stress caused by the difference in material system. Since its thickness is clearly less than that of the gate dielectric layer 3, it does not occupy the critical space of the channel region, thus ensuring the miniaturization target of the device. At the same time, this thin oxide layer is partially retained in the subsequent self-aligned etch-back process, providing an auxiliary reference for the formation of the gate dielectric layer 3 and the positioning of the gate metal 4, thereby improving the repeatability and robustness of the overall process.

[0144] In one specific embodiment, the semiconductor device further includes a bit line isolation structure extending along the bit line direction and a word line isolation structure extending along the word line direction, wherein the material of the word line isolation structure is the same as or belongs to the same type of silicon nitride-based material as the material of the mesh support structure 6.

[0145] Specifically, the bit line isolation structure and the word line isolation structure extend in two mutually perpendicular directions and fill the spaces between adjacent active pillars 2 to form electrical isolation. The bit line isolation structure extending along the bit line direction can be made of an oxide dielectric, while the word line isolation structure extending along the word line direction is made of a silicon nitride-based material. This material is the same as the silicon nitride-based material constituting the grid support structure 6 (e.g., both are silicon nitride), or belongs to the same category of materials with similar physicochemical properties (e.g., the grid support structure 6 uses silicon carbide nitride, while the word line isolation structure uses silicon nitride). This material design makes the grid support structure 6 and the word line isolation structure materially compatible or unified, which helps simplify process integration and improve the interfacial thermomechanical stability between different parts of the device.

[0146] It should be understood that the bit line isolation structure extends along the first direction to achieve electrical isolation between adjacent active pillars 2. Its structure is an insulating structure that is perpendicular to the surface of the substrate 1 and embedded in the substrate 1 or the interlayer medium. The word line isolation structure extends along the second direction and is orthogonally arranged with the bit line isolation structure to form a three-dimensional cross isolation network. The first direction and the second direction are perpendicular to each other. For example, the first direction is the X direction and the second direction is the Y direction. Both are parallel to the surface of the substrate 1.

[0147] The material of the bit line isolation structure includes oxides, nitrides or stacks thereof, such as silicon dioxide, silicon nitride, aluminum oxide or combinations thereof. The bit line isolation structure can be formed by deep trench isolation, shallow trench isolation or atomic layer deposition filling process, and its depth extends into the interior of the substrate 1 or at least through the bottom region of the active pillar 2 to ensure effective isolation.

[0148] The material of the word line isolation structure is the same as or belongs to the same type of silicon nitride-based material as the material of the grid support structure 6. The silicon nitride-based material is selected from at least one of silicon nitride, silicon carbide, silicon boron nitride, or silicon carbonitride. This limitation allows the word line isolation structure and the grid support structure 6 to be continuously deposited in the same process chamber by atomic layer deposition or chemical vapor deposition, and to share the same heat treatment, etching, and etch-back process windows. For example, in the ALD deposition process, the word line isolation structure and the grid support structure 6 can be formed simultaneously by using the same precursor and reaction conditions.

[0149] The word line isolation structure and the grid support structure 6 maintain a high degree of consistency in material composition, crystal structure and density. When both are amorphous silicon nitride, this consistency ensures that no significant stress gradient or element interdiffusion is generated at the interface during subsequent high-temperature annealing or gate 4 metal filling, thereby avoiding defects such as microcracks, voids or interface peeling.

[0150] Although the word line isolation structure and the grid support structure 6 are physically separated and have different functions, they can share the same mask pattern definition step and the same dry etching gas system (such as...) during the manufacturing process. Patterning is performed using a mixed gas. For example, after the overall deposition of silicon nitride-based materials is completed, the sidewall contour of the word line isolation structure and the multi-layer grid opening of the grid support structure 6 can be formed simultaneously by one photolithography and one anisotropic dry etching. This self-alignment characteristic makes the overlay error less than 2nm, improving the structural uniformity and electrical repeatability of the device array.

[0151] It is foreseeable that, while maintaining the 4F² cell area constraint, the word line isolation structure and the grid support structure 6 share the silicon nitride-based material system, thereby reducing independent deposition and etching steps during manufacturing and lowering process complexity. At the same time, the consistency of the intrinsic parameters of the material suppresses local warping and interface failure caused by thermal mismatch, enhancing the overall mechanical stability of the three-dimensional pillar structure. In addition, the shared process window supports high-precision self-aligned patterning, improving the spatial alignment accuracy between the word line and the active pillar 2, thereby improving the threshold voltage uniformity and leakage current consistency of the device.

[0152] In one specific embodiment, the drain extension pad 5 is a silicon layer formed by selective epitaxial growth or chemical vapor deposition.

[0153] Specifically, the drain extension liner layer 5 is formed by either selective epitaxial growth or chemical vapor deposition. Selective epitaxial growth involves selectively growing single-crystal silicon on the exposed silicon surface of the drain region 23 using a vapor phase epitaxy process under specific process gas atmosphere and temperature conditions. This method enables atomically precise, lattice-matched silicon layer deposition on the sidewalls and top edge of the drain region 23, thereby significantly increasing the conductive surface area while ensuring extremely low interface resistance and excellent crystal quality between the newly grown silicon layer and the existing drain silicon.

[0154] Chemical vapor deposition (CVD) is a process in which a polycrystalline or amorphous silicon layer is non-selectively deposited on the surface of the drain region 23 through the decomposition reaction of a silicon source gas (such as silane). This method provides highly conformal coverage, forming a silicon layer of uniform thickness even on complex three-dimensional surface structures, and effectively increasing the effective conductive area of ​​the drain.

[0155] Regardless of which method is used, the resulting silicon layer (i.e., drain extension pad layer 5) is directly and firmly attached to the original silicon surface of the drain region 23. Its fundamental purpose is to reduce the series resistance in the vertical direction of current flow and the subsequent contact resistance with the contact electrode by increasing the conductive area of ​​the sidewall.

[0156] It should be understood that, in this process, selective epitaxial growth is performed on the exposed single-crystal silicon surface (i.e., the exposed silicon crystal surface at the top and sidewalls of the drain region 23 of the active pillar 2), using a gaseous silicon precursor as the source, at a controlled temperature. Pressure 10–100 Torr and carrier gas atmosphere ( or Under the substrate 1, a single-crystal silicon layer with the same lattice orientation as the substrate 1 is directionally grown. The thickness of the single-crystal silicon layer is 5nm–50nm, and its doping concentration is controlled by in-situ doping, introducing phosphorus (P) or arsenic (As) to form n-type doping.

[0157] Chemical vapor deposition involves depositing an amorphous silicon or microcrystalline silicon layer on the exposed surface of the same drain region 23 using low-pressure CVD or plasma-enhanced CVD. The layer is then recrystallized through an annealing process to form a silicon layer with controllable crystallinity and interface characteristics. The thickness of the silicon layer is 10 nm–80 nm, and its composition can be pure silicon or contain trace amounts of carbon, germanium, or nitrogen to adjust stress and dielectric properties.

[0158] Selective epitaxial growth and chemical vapor deposition can be used individually or in combination: for example, a basic silicon film is first formed by CVD, and then SEG is performed on it to improve the top crystal quality. The drain extension pad layer 5 covers the entire sidewall of the drain region 23 of the active pillar 2 and extends upward to part of the top surface. Its lateral extension width is 20nm–100nm. The surface morphology of the drain extension pad layer 5 meets the compatibility requirements of subsequent processes: under selective epitaxial growth conditions, its surface roughness is less than 0.5nm; under chemical vapor deposition conditions, the surface roughness after annealing is less than 1.0nm; and the case where the surface roughness is ≤2.0nm is also within the scope of this application.

[0159] It is foreseeable that, without changing the 4F² cell area, a high-quality silicon layer with controllable thickness can be constructed on the sidewall of the drain region 23 by selective epitaxial growth or chemical vapor deposition, which can significantly expand the effective contact area between the drain and the upper metal layer. Since the silicon layer has good lattice matching with the active pillar 2 bulk silicon or has good interface continuity after annealing, the drain-metal contact interface barrier and defect density are reduced, which ultimately effectively reduces the contact resistance and drain resistance, and alleviates the interconnection bottleneck problem in high-density DRAM devices.

[0160] Please refer to Figures 2 to 8 This application further discloses a method for manufacturing a semiconductor device, used to manufacture the aforementioned semiconductor device, the method comprising the following steps:

[0161] S1. Provide a substrate 1 and form an active pillar 2 pattern on the substrate 1;

[0162] S2. A gate dielectric layer 3 is formed only in the channel region 22 of the active column 2;

[0163] S3. On the sidewall of the drain region 23 of the active column 2, a drain extension liner layer 5 is formed by selective epitaxial growth or chemical vapor deposition.

[0164] S4. Through a self-aligned process, a grid support structure 6 with multiple dielectric material layers and a ladder-like structure along the word line direction is formed on the outside of the drain extension pad layer 5.

[0165] Step S1 specifically includes:

[0166] Step S11: Sequentially form a silicon-germanium layer and a silicon layer on substrate 1;

[0167] Step S12: Using the silicon-germanium layer as the etching stop layer, etch the silicon layer along the bit line direction to form the first gap;

[0168] Step S13: After filling the first gap, etch along the word line direction perpendicular to the bit line direction to form a second gap, wherein the bottom depth of the second gap is less than the bottom depth of the first gap.

[0169] like Figure 3 As shown in the figure, reference numeral 10 is the substrate silicon layer, reference numeral 20 is the silicon-germanium epitaxial layer, reference numeral 30 is the silicon epitaxial layer, reference numeral 40 is the pad oxide layer, and reference numeral 50 is the silicon nitride layer. The pad oxide layer 40 and the silicon nitride layer 50 serve as mask structures, which are responsible for the pattern definition and etching protection functions of subsequent processes.

[0170] like Figure 4 As shown in the figure, reference numeral 20 represents the silicon-germanium epitaxial layer, and reference numeral 60 represents the gap filler.

[0171] like Figure 5 As shown in the figure, reference numeral 20 represents the silicon-germanium epitaxial layer, reference numeral 80 represents the oxide layer grown using atomic layer deposition (ALD), and reference numeral 70 represents the silicon nitride layer prepared using ALD, which also serves as an interstitial filler.

[0172] Specifically, substrate 1 is a single-crystal silicon substrate 1. The active pillar 2 pattern is defined on substrate 1 by a patterning process to form multiple vertically extending silicon pillar structures. The patterning process includes sequentially depositing a silicon-germanium epitaxial layer 20 and a silicon epitaxial layer 30 on the surface of substrate 1. The silicon-germanium layer is used as the etching stop layer for subsequent dry etching. The bit line direction pattern is defined by a self-aligned double patterning or self-aligned quadruple patterning process. Then, the word line direction pattern is defined perpendicular to the bit line direction, thereby forming a pillar array pattern with anisotropic depth characteristics. The bottom of the bit line direction gap terminates at the upper surface of the silicon-germanium layer, while the bottom depth of the word line direction gap is 50~100nm less than the bottom depth of the bit line direction gap. This forms an asymmetric slope structure on the sidewall of the pillar, providing a geometric reference for the spatial positioning of the subsequent drain expansion and grid support structure 6.

[0173] In an optional embodiment, step S1 may involve first growing a silicon-germanium epitaxial layer 20 on a silicon substrate 1, using the silicon-germanium epitaxial layer 20 as a termination layer in back-side thinning, chemical mechanical polishing, or lift-off processes, and then growing a silicon epitaxial layer 30 on it for fabricating actual devices. This epitaxial layer can be customized according to the doping concentration requirements of the device channel. Subsequently, a bilayer film structure of silicon dioxide and silicon nitride is formed on the surface of the silicon layer and used as a mask layer.

[0174] To fabricate the back-side bit lines, a bit line patterning process is performed. The mask layer and the underlying silicon epitaxial layer 30 are patterned along the bit line direction using photolithography and etching processes. The silicon epitaxial layer 30 is etched using a dry active etching process until the etching stops at the silicon-germanium epitaxial layer 20 as the etch stop layer, thus forming a first gap in the bit line direction. Subsequently, an atomic layer deposition process is used to fill the first gap with oxide. For larger gap regions, after atomic layer deposition of oxide, a silicon nitride pad layer deposition, spin-coating oxide coating, and thermal treatment processes can be sequentially performed, followed by chemical mechanical polishing (CMP) to achieve planarization. The CMP stop layer can be selected according to the structure of the mask layer.

[0175] The word line layer patterning process is performed, and its mask fabrication process is consistent with that of the bit line patterning process. The word line layer is arranged perpendicularly to the bit line direction. A dry etching process is used to etch along the word line direction to form a second gap, and the etching termination position is set at a depth of 50 to 100 nanometers below the bottom of the first gap (bit line gap). After the word line gap is formed, an oxide layer is deposited using atomic layer deposition (ALD), and the thickness of the deposited oxide layer is no greater than the thickness of the word line metal layer to be fabricated subsequently. Next, silicon nitride is deposited on the oxide layer using the same ALD process to form a silicon nitride isolation wall for device isolation.

[0176] In other alternative embodiments, step S1 may also involve using a single-layer silicon dioxide film structure as a mask layer instead of the aforementioned double-layer film structure.

[0177] In other alternative embodiments, step S1 may also be performed by directly etching the word line direction instead of performing CMP planarization after completing bit line etching and filling oxide. The filled oxide is used as a local masking layer to allow the word line etching to penetrate deeper into the uncovered area, thereby achieving depth control without additional masks.

[0178] In one alternative implementation, the bit line orientation etching method is as follows: using a reactive ion etching device, with an RF power of 150–250W, a chamber pressure of 3–8 mTorr, and a gas flow rate of Under these conditions, directional etching is performed on the silicon layer until the silicon-germanium layer interface signal is captured in real time by the optical emission spectrum.

[0179] In another alternative implementation, the bit-line orientation etching method includes: based on a capacitively coupled plasma etching system, by periodically modulating the bias power (pulsed bias, duty cycle 30%–50%), suppressing sidewall redeposition, improving the integrity of the silicon-germanium layer interface at the bottom of the gap, thereby ensuring etching stop accuracy better than ±2nm.

[0180] Furthermore, the word line etching method adopts a step-by-step etching strategy: first, the filling oxide layer is pre-etched with lower energy to expose the underlying silicon layer; then, it is switched to a high selectivity silicon etching mode to penetrate the silicon layer and enter the substrate 1 below the silicon-germanium layer. This method can avoid silicon-germanium layer fragmentation or micromask defects caused by a single strong etching, and improve the verticality of the second gap sidewall and the flatness of the bottom.

[0181] In step one of this embodiment, a silicon-germanium layer and a silicon layer are sequentially constructed on substrate 1. The high etch selectivity of the silicon-germanium layer to silicon is utilized to terminate the bit line etching. Based on this, orthogonal word line etching is performed on the structure that has filled the first gap, breaking through the constraint of single-step etching on depth consistency and achieving a differentiated structure of the gap depth in the bit line and word line directions. This difference not only meets the differentiated requirements of electrical isolation strength and mechanical support stiffness in different directions, but also allows the deeper gap in the word line direction to more effectively accommodate the subsequent gate 4 stacking structure. At the same time, the residual part of the silicon-germanium layer is retained as a stress relief buffer layer, which synergistically improves the overall morphological stability and process robustness of the three-dimensional pillar structure.

[0182] In step S2, "only in the channel region 22" means that the coverage of the gate dielectric layer 3 is limited to the middle section of the active pillar 2 located between the source region 21 and the drain region 23, and does not extend to the top of the source region 21 or the sidewall of the drain region 23. The gate dielectric layer 3 is a silicon dioxide or high dielectric constant material layer formed by thermal oxidation or atomic layer deposition. Its formation method depends on the geometry and surface chemical state of the pillar sidewall constructed above. After the oxide back etching is completed between the word line and the bit line, the silicon at the top of the pillar is exposed, while the sidewall is still partially covered by the residual oxide or silicon nitride pad layer. At this time, only the exposed top area of ​​the pillar is subjected to controlled oxidation or ALD deposition, so that the gate dielectric layer 3 is naturally limited to the height range of the channel, avoiding coverage interference to the drain extension region.

[0183] In step S3, after the active pillar 2 pattern is defined in step S1, the oxide filling the gaps between the bit lines and word lines is etched by a self-aligned etch-back process. The etching depth must reach at least the fabrication depth of the subsequent drain structure, thereby exposing the silicon surface (i.e., drain region 23) at the top of the active pillar 2.

[0184] On the exposed drain region 23 silicon surface, a silicon material layer is formed by selective epitaxial growth or chemical vapor deposition process as a drain extension pad layer 5.

[0185] Selective epitaxial growth: Under specific process conditions, silicon atoms are selectively epitaxially grown on the surface of exposed single-crystal silicon (drain region 23) to form a high-quality single-crystal silicon layer with a continuous crystal structure.

[0186] Chemical vapor deposition: A polycrystalline or amorphous silicon layer is deposited conformally on all surfaces, including the drain region 23, through the decomposition reaction of silicon source gas, and the desired portion is retained through subsequent processes.

[0187] The formed drain extension pad layer 5 is directly attached to the original drain silicon surface and significantly increases the sidewall conductive area of ​​the drain region 23. This is the key structural basis for achieving the technical effect of reducing drain series resistance and contact resistance.

[0188] Among them, the drain extension pad layer 5 is a silicon material layer, and the "sidewall of drain region 23" specifically refers to the vertical sidewall surface of the active pillar 2 located within the height range of drain region 23, excluding the top plane of the pillar or the sidewall of channel region 22. The formation method includes selective epitaxial growth or chemical vapor deposition. Both use the exposed silicon surface of the pillar sidewall as the nucleation site and grow spontaneously under maskless conditions, thereby achieving directional coverage of the sidewall of drain region 23. This process does not rely on photolithography alignment and has natural self-alignment characteristics. The formed silicon layer extends upward along the sidewall, effectively increasing the lateral projection area and three-dimensional contact volume of drain region 23, providing a larger surface area for subsequent metal contact.

[0189] In one alternative implementation, the method for forming the drain extension pad layer 5 can be: after completing oxide etchback and exposing the silicon at the top of the pillar and the drain sidewall, introducing silicon precursor and HCl gas, in... Selective epitaxial growth is performed at a temperature that results in a growth rate much higher on silicon surfaces than on oxide or silicon nitride surfaces, thus forming a continuous silicon layer only on the drain sidewall.

[0190] In another alternative implementation, the method for forming the drain extension liner layer 5 may include: depositing an amorphous silicon thin layer at the same temperature window using low-pressure chemical vapor deposition, followed by solid-state crystallization annealing, so that the silicon layer grows in a preferred orientation on the sidewall of the pillar to form an extension liner layer with good crystal quality.

[0191] Furthermore, the method for forming the drain extension liner layer 5 can also be: pre-depositing an ultrathin metal catalyst layer (such as Ni or Co) on the sidewall of the pillar, and then introducing silicon source gas to accelerate the selective deposition of silicon on the sidewall through the metal-induced crystallization mechanism, thereby improving the growth uniformity and thickness controllability.

[0192] Step S4 specifically includes:

[0193] S41. Oxidize the surface of the drain extension pad layer 5 to form a first oxide layer;

[0194] S42, Deposit a silicon nitride-based material layer on the first oxide layer;

[0195] S43. Etch back the silicon nitride material layer to define the ladder structure.

[0196] The thickness of the first oxide layer is less than the thickness that can be removed by the subsequent oxide etch-back process to expose the channel region 22, so that the first oxide layer is retained below the grid support structure 6.

[0197] Specifically, firstly, without employing additional photolithography processes, a self-aligned process is used to perform a global etching back of the oxides filling the bit line gaps and word line gaps. This etching back can be done using dry or wet etching, and its depth must be greater than or equal to the fabrication depth of the drain extension pad layer 5, thereby exposing the drain extension pad layer 5 and part of the pillar sidewall area into the formed groove. This step defines the space for the subsequent formation of the mesh support structure 6.

[0198] A thermal oxidation process is performed on the silicon surface of the exposed drain extension pad layer 5, causing partial oxidation of its surface to form a first oxide layer on the outside of the drain extension pad layer 5. The thickness of this first oxide layer is less than the thickness of the silicon material in the drain extension pad layer 5, and is ensured to be less than the thickness that can be removed by the global oxide etch-back process performed in a subsequent step to expose the channel. This allows the first oxide layer to be retained as a permanent interface layer in subsequent processes.

[0199] On the first oxide layer, an atomic layer deposition process is used to conformally deposit a silicon nitride-based material as the main layer of the grid support structure 6. The silicon nitride-based material can be at least one of silicon nitride, silicon carbide, silicon boron nitride, or silicon carbonitride.

[0200] An anisotropic dry etch-back process is performed on the deposited silicon nitride-based material layer. This etch-back process selectively removes material in the horizontal direction, retaining silicon nitride-based material only in the vertical direction of the drain extension pad layer 5 sidewalls and at the steps formed by the etch-back process. By precisely controlling this etch-back process, a ladder-like mesh structure with periodic uneven features, composed of the retained silicon nitride-based material, is formed along the word line direction on a plane parallel to the substrate 1.

[0201] After defining the ladder-like mesh structure, an oxide etch-back process is performed. This process further removes residual oxide at the bottom of the bit line gaps that was not completely removed by the silicon nitride etch-back. This step serves two purposes: first, it exposes the silicon surface of the channel region 22 of the active pillar 2, preparing for the subsequent formation of the gate dielectric layer 3; second, during this process, the first oxide layer located below and protected by the mesh support structure 6 (silicon nitride-based material layer) is completely preserved because its thickness is less than the etch-back capability of this step, thus forming a stable first dielectric layer between the drain extension pad layer 5 and the mesh support structure 6. Furthermore, depending on the process conditions, in related steps before the gate 4 metal deposition, the silicon located at the corner between the mesh support structure 6 and the adjacent isolation structure may be completely oxidized, potentially forming an additional oxide spacer layer between the mesh support structure 6 and the subsequently formed gate 4 metal.

[0202] It should be noted that "self-aligned process" refers to the process of transferring patterns through global etching and deposition operations without using independent photolithography steps. Instead, it uses the pre-formed structure (including drain extension pad layer 5, gap oxide, and isolation wall) as a physical mask or etching stop reference. The "multi-layer mesh support structure 6" is composed of at least two layers of different materials, including an inner oxide layer and an outer silicon nitride-based material. It is mesh-shaped on the cross-section parallel to the substrate 1, covers the entire sidewall height of the drain extension pad layer 5 in the depth direction, and extends to a certain range above it, forming a mechanical envelope support for the top of the pillar. This structure presents a trapezoidal profile in the word line direction and works with the word line isolation wall to form a three-dimensional constraint system.

[0203] In one alternative implementation, the method for forming the multi-layer mesh support structure 6 may be as follows: first, the drain extension pad layer 5 is partially oxidized by low-temperature wet or dry method to generate an oxide layer with a thickness of 1~3nm on its surface; then, an atomic layer deposition is used to cover the oxide layer with a silicon nitride material layer; finally, anisotropic etching is performed on the silicon nitride material layer so that the material is retained only on the sidewalls and top edge of the drain extension pad layer 5 to form a mesh-like profile.

[0204] In another alternative implementation, the method for forming the multilayer mesh support structure 6 may include: after the drain extension pad layer 5 is formed, first depositing a SiN pad layer using ALD, and then depositing another layer... Subsequently, synchronously and Selective etching back is performed, utilizing the difference in etching rates between the two processes to control the remaining structural morphology, ultimately preserving the SiN-based mesh framework and retaining a controllable thickness beneath it. Buffer layer.

[0205] Furthermore, the method for forming the multilayer mesh support structure 6 can also be as follows: after completing the drain-extended silicon growth, instead of separate oxidation, a SiCN layer is directly deposited by ALD. During subsequent high-temperature annealing, the SiCN layer undergoes an interfacial reaction with the underlying silicon, forming in situ... The composite interface not only meets the requirements of multi-layer structures, but also enhances the interlayer bonding and thermal stability.

[0206] In one alternative implementation, the partial oxidation method can be: thermal oxidation in a nitrogen-oxygen mixed atmosphere at 400–600°C, controlling the oxidation time to be 30–120 seconds, to generate a layer with a thickness of 1.5 ± 0.3 nm on the surface of the drain extension liner 5. layer;

[0207] In another alternative implementation, the partial oxidation method may include: employing Plasma pulses are used to oxidize the drain extension liner layer 5 at room temperature to 200°C. Each pulse lasts for 1 to 5 seconds and is repeated 5 to 20 times to obtain an oxide layer with uniform thickness distribution and low interface defect density.

[0208] Furthermore, partial oxidation methods can also employ atomic layer oxidation: sequentially introducing a silicon precursor (such as...) ) and oxygen precursors (such as or After completing 1 to 3 ALO cycles, a controllable thickness and stable composition are constructed on the surface of the drain extension liner 5. Interface layer.

[0209] In one alternative implementation, the silicon nitride-based material layer can be deposited using atomic layer deposition (ALD) at a temperature of 250–350°C. and As a reaction precursor, the deposition thickness is 8–15 nm. layer;

[0210] In another alternative implementation, the deposition method of the silicon nitride-based material layer may include: employing a low-pressure chemical vapor deposition process at 700–800°C, and The reactant gas is used to deposit a thickness of 10–20 nm. layer;

[0211] Furthermore, the deposition method for silicon nitride-based material layers can also employ plasma-enhanced chemical vapor deposition (PECVD): at a substrate temperature of 300–400°C, with… and Using a precursor gas, radio frequency power is applied to excite plasma, and a gradient refractive index is deposited. layer.

[0212] In one alternative implementation, the etch-back method can be: using The mixed gas is subjected to dry anisotropic etching at a chamber pressure of 0.5–2 Pa and a radio frequency power of 200–500 W for 60–180 seconds until the silicon nitride material layer stops on the surface of the oxide layer.

[0213] In another alternative implementation, the etch-back method may include: employing High selectivity etching is performed using a mixed gas at a pressure of 1–3 Pa, a WICP power of 300–600 W, and a bias power of 50–150 W to enhance the protection of the underlying oxide layer.

[0214] Furthermore, the etching back method can also employ multi-step stepped etching: first, the upper silicon nitride material is rapidly removed under high bias conditions, and then the process is switched to low bias and high gas flow conditions for fine finishing, so as to obtain a mesh structure profile with a sidewall verticality better than 88°.

[0215] This application achieves the following technical effects through the above steps: First, the above-constructed columnar pattern with depth differences lays the geometric foundation for the subsequent spatial separation of the drain and channel regions 22; second, the above-relying on this geometric feature achieves the selective formation of the gate dielectric layer 3, ensuring that it only covers the channel and does not invade the drain region; third, the above-relying on the intrinsic reactive activity of the silicon surface, the above-relying on the drain sidewall achieves self-aligned silicon expansion without photolithography, directly expanding the contact area; next, the above-relying on the aforementioned expanded silicon as a template, the above-relying on self-aligned oxidation and silicon nitride deposition / etchback constructs a multi-layered mesh structure on its outer side that has both mechanical support and electrical isolation functions; finally, the above-relying on the drain expansion action is clearly limited to two interchangeable process paths: selective epitaxy or chemical vapor deposition, ensuring process robustness and production line compatibility. Overall, a strict input-output dependency relationship is formed between each step: the column pattern determines the spatial distribution of the channel and drain; the channel region 22 defines the positioning of the guiding gate dielectric layer 3; the exposed state of the drain sidewall triggers selective silicon growth; the silicon expansion morphology inversely constrains the envelope range of the grid support structure 6; and the entire process completely avoids multiple photolithography overlay errors, improving the control accuracy of key structural dimensions to the sub-nanometer level, thereby simultaneously reducing Rc, suppressing column bending, reducing parasitic capacitance, and improving manufacturing yield and process repeatability while maintaining the 4F² cell area.

[0216] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A semiconductor device, comprising: Substrate (1); An active pillar (2) is vertically disposed on the substrate (1). Multiple active pillars (2) are disposed, and each active pillar (2) includes a source region (21), a channel region (22) and a drain region (23). Its characteristic is that it further includes: A gate dielectric layer (3) is formed in the channel region (22) of the active pillar (2). A gate (4) is disposed around the gate dielectric layer (3); A drain extension liner (5) is formed on the sidewall of the drain region (23) of the active column (2); A grid support structure (6) is formed on the outside of the drain extension pad layer (5), the grid support structure (6) comprising multiple layers of material; A first oxide layer is located between the drain extension pad layer (5) and the grid support structure (6).

2. The semiconductor device according to claim 1, characterized in that, The material of the grid support structure (6) includes a silicon nitride-based material, which is selected from at least one of silicon nitride, silicon carbide, silicon boron nitride, or silicon carbonitride; And / or, Along the direction of the character lines, the grid support structure (6) has a ladder-like structure.

3. The semiconductor device according to claim 1, characterized in that, The mesh support structure (6) is in direct contact with the metal material of the gate (4) in the depth direction; or, an oxide spacer layer is provided between the mesh support structure (6) and the metal material of the gate (4).

4. The semiconductor device according to claim 1, characterized in that, The thickness of the oxide layer is less than the thickness of the gate dielectric layer (3).

5. The semiconductor device according to claim 1, characterized in that, It also includes bit line isolation structures extending along the bit line direction and word line isolation structures extending along the word line direction; in, The material of the word line isolation structure is the same as or belongs to the same type of silicon nitride material as the material of the grid support structure (6).

6. The semiconductor device according to claim 1, characterized in that, The drain extension pad layer (5) is a silicon layer formed by selective epitaxial growth or chemical vapor deposition.

7. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and an active column pattern is formed on the substrate; A gate dielectric layer is formed in the channel region of the active column; A drain extension liner layer is formed on the sidewall of the drain region of the active column by selective epitaxial growth or chemical vapor deposition. A grid support structure with multiple dielectric material layers and a ladder-like structure along the word line direction is formed on the outside of the drain extension pad layer through a self-aligned process.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The steps for forming an active column pattern include: A silicon-germanium layer and a silicon layer are sequentially formed on the substrate; Using the silicon-germanium layer as an etch stop layer, the silicon layer is etched along the bit line direction to form a first gap; After filling the first gap, etching is performed along the word line direction perpendicular to the bit line direction to form a second gap, wherein the bottom depth of the second gap is less than the bottom depth of the first gap.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The steps in forming the ladder-shaped grid support structure include: The surface of the drain extension pad layer is oxidized to form a first oxide layer; A silicon nitride-based material layer is deposited on the first oxide layer; The silicon nitride-based material layer is etched back to define a ladder-like structure; The thickness of the first oxide layer is less than the thickness that can be removed by the subsequent oxide etch-back process to expose the trench region, so that the first oxide layer is retained under the grid support structure.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The manufacturing method further includes the following steps: A gate is formed surrounding the gate dielectric layer, wherein the sidewalls of the gate are in direct contact with the grid support structure in the depth direction, or an oxide spacer layer is formed between the gate and the grid support structure.

Images