Memory chip test circuit

Abstract

According to the memory chip test circuit provided by the utility model, the first test loop and the second test loop are arranged in parallel in the second side channel of the first analog switch and can be used for testing different test items, and the register is arranged in the second test loop and can be used for testing the test items corresponding to the first test loop. Meanwhile, an address signal of a next to-be-tested memory is sent to the second test loop in advance and is stored in the register, after a test item corresponding to the first test loop is completed, the address signal stored in the register can be sent out only by sending a switching instruction to the register, and the first analog switch is controlled to switch an input port of a corresponding channel; therefore, the address signal updating waiting time can be effectively shortened, the switching speed can be improved, signal interference in the switching action of the first analog switch can be shielded, and the test reliability can be improved.

Description

Technical Field

[0001] This utility model relates to the field of chip testing technology, and in particular to a memory chip testing circuit. Background Technology

[0002] To ensure the quality of memory chips leaving the factory, it is necessary to test multiple dimensions of the memory chips, including functionality, performance, reliability, and environmental adaptability. To improve testing efficiency, batch testing is usually performed, connecting multiple memory chips under test in parallel to a test bus. The memory chip under test is selected by the address signal on the test bus, and IIC bus signals are transmitted through the IIC communication bus (including the serial data line SDA and the clock signal line CLK). Each memory chip under test can be tested sequentially through a set of test buses.

[0003] After the current memory chip test is completed, the address signal needs to be updated to perform the next memory chip test. However, the transmission of the updated address signal from the test machine to the memory chip under test takes a certain amount of time, which reduces the test efficiency. The higher the test switching frequency, the greater the impact. Utility Model Content

[0004] Therefore, the purpose of this utility model is to provide a memory chip test circuit to solve the problem that the transmission time of the update address signal reduces the test efficiency.

[0005] This utility model provides a memory chip testing circuit, including a primary testing module. The primary testing module includes: a chip-under-test (DUT) connection board, a primary testing interface connected to a testing machine, and a primary transfer circuit connecting the primary testing interface and the DUT connection board.

[0006] The test bus of the chip under test connection board has multiple test bits connected in parallel, and the first-level transmission circuit includes a first analog switch and a register;

[0007] The first side port of each channel of the first analog switch is connected to the test bus one by one. The second side port of each channel of the first analog switch is a parallel port, and a first test circuit and a second test circuit are connected in parallel. One of the first test circuit and the second test circuit is used for electrical testing, and the other is used for read and write testing.

[0008] The address lines and write protection control lines in the second test circuit, as well as the control terminal of the first analog switch, are connected to the register, and the control terminal of the register is connected to the first-level test port;

[0009] The communication bus in the second test loop and the first test loop are connected to the first-level test port.

[0010] Optionally, it also includes a secondary test module, wherein multiple primary test modules are connected in parallel, as well as a bidirectional voltage level converter, a second analog switch, and a bus buffer, wherein...

[0011] The first test circuit is directly connected to the secondary test port of the secondary test module through the primary test port and the connecting line;

[0012] The communication bus in the second test circuit is connected to the address port and write protection control port in the second-level test port in sequence through the first-level test port, the bidirectional voltage level converter and the second analog switch;

[0013] The control terminal of the register is connected to the secondary test port through the primary test port and the bus buffer;

[0014] The secondary test port is connected to the test machine.

[0015] Optionally, the bidirectional voltage level converter is provided with multiple communication bus channels, each communication bus channel being connected to at least one of the first-level test modules.

[0016] Optionally, the register includes a shift register.

[0017] The memory chip test circuit provided by this utility model sets up a first test circuit and a second test circuit in parallel, which can be used for testing different test items. When performing the test item corresponding to the first test circuit, the address signal of the next memory under test can be sent to the second test circuit in advance and stored in a register. After the test item corresponding to the first test circuit is completed, only a switching instruction needs to be sent to the register to send out the address signal stored in the register and control the first analog switch to switch the input port of the corresponding channel. This can effectively reduce the address signal update waiting time, improve the switching speed, and the time consumed by the register update output is less than the channel switching time of the first analog switch. When the first analog switch is switched, the input signal of the corresponding channel of the first analog switch can be stabilized, avoiding signal glitches, shielding the signal interference in the switching action of the first analog switch, and improving the test reliability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the first-level test module of the memory chip test circuit in this embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of the secondary test module of the memory chip test circuit in this embodiment of the present invention.

[0020] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this utility model. Detailed Implementation

[0021] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of this utility model are shown in the drawings. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0022] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] To address the issue of reduced testing efficiency due to the long transmission time of address update signals, this invention provides a memory chip testing circuit. It includes a first test circuit and a second test circuit connected in parallel, suitable for testing different items. While performing the test item corresponding to the first test circuit, the address signal of the next memory under test can be pre-sent to the second test circuit and stored in a register. After the test item corresponding to the first test circuit is completed, a switching instruction is sent to the register to send out the address signal stored in the register and control the first analog switch to switch the input port of the corresponding channel. This effectively reduces the address signal update waiting time, increases the switching speed, and the time consumed by updating the register output is less than the channel switching time of the first analog switch. When the first analog switch completes its switching, the input signal of the corresponding channel of the first analog switch can be stabilized, signal glitches can be avoided, signal interference during the switching action of the first analog switch can be shielded, and testing reliability can be improved.

[0025] Specifically, please refer to Figure 1 The diagram shown is a schematic diagram of the first-level test module of the memory chip test circuit in this embodiment.

[0026] The primary test module includes a chip-under-test (DUT) connection board (not shown in the figure, connected by a first connector H1 and a test bus), a primary test interface H2 connected to the tester, and a primary transmission circuit connecting the primary test interface H2 and the DUT connection board. The DUT connection board has multiple test bits connected in parallel on its test bus (corresponding to the DUT memory chip sockets so that after the DUT memory chip is plugged into the socket, the test pins are connected to the corresponding wiring in the test bus). The primary transmission circuit transmits test-related signals and data between the tester and the DUT memory chip.

[0027] The signals transmitted in the test bus and the first connector H1 include address signals (A0, A1, A2), IIC communication bus signals (SDA and CLK), write protection control signals (WP), and power signals (the power requirements vary depending on the test item), with a corresponding total of 8 wirings.

[0028] The primary transmission circuit includes a first analog switch and a register U14. The first side port of each channel of the first analog switch is connected to the test bus one by one through the first connector H1. The second side port of each channel of the first analog switch is a parallel port, and a first test circuit and a second test circuit are connected in parallel. In this embodiment, the first test circuit is used for electrical testing (testing of the connection of the memory chip, IO (input / output) leakage current, IO level, power supply leakage current, operating current, etc.) and for read / write testing.

[0029] The address lines and write protection control lines in the second test loop, as well as the control terminal of the first analog switch, are connected to register U14. The control terminal of register U14 is connected to the first-level test port H2. Since register U14 is a unidirectional transmission circuit, while the IIC bus signals in electrical testing and read / write testing require bidirectional communication, the IIC communication buses in both the first and second test loops are directly connected to the first-level test port H2 via the first analog switch. However, due to different specific test items, different interfaces are configured in the test machine, requiring separate settings. For example, in this embodiment, the SDA and CLK interfaces in the first-level test port H2 are used for the first test loop, and the SDA-Write and CLK-Write interfaces are used for the second test loop.

[0030] To avoid interference between data and power, in this embodiment, the first analog switch includes a first switch U11, a second switch U12, and a third switch U13. The first and second switches U11 and U12 are used for transmitting address signals, write protection control signals, and IIC communication bus signals. The third switch U13 is used for power transmission. The first power supply VCC-F and the second power supply VCC-S are used for electrical testing, and the third unit VCC-Write is used for read / write testing. Specifically, the first and second switches U11 can be selected as SN74CBT3257C type switches, and the third switch U13 can be selected as a 74HC4053 / TMUX4053 type switch.

[0031] To facilitate address signal updates during read / write tests, in this embodiment, register U14 includes a shift register, which can reduce the number of inputs. For a three-bit binary address signal, a 74AHC595 shift register can be selected.

[0032] Specifically, the output signal of port Q1 of register U14 is used for the enable control of the first switch U11, the second switch U12 and the third switch U13, and the output signal of port Q2 is used for the input port switching control of the channels of the first switch U11, the second switch U12 and the third switch U13.

[0033] To improve testing efficiency, such as Figure 2 As shown, in this embodiment, a secondary test module is also included. The secondary test module has multiple primary test modules 100 connected in parallel, as well as a bidirectional voltage level converter 21, a second analog switch 22 and a bus buffer 20. The multiple primary test modules 100 can be tested in parallel, and most of the corresponding primary test interfaces are connected in parallel. The communication bus used for read and write tests is led out through the bidirectional voltage level converter 21 and the second analog switch 22 respectively.

[0034] The first test circuit is directly connected to the second-level test port of the second-level test module through the first-level test port and the connecting line, so as to the test machine 500 through the second-level test port; the communication bus in the second test circuit is connected to the address port, communication bus port and write protection control port in the second-level test port through the first-level test port, the bidirectional voltage level converter 21 and the second analog switch 22 in sequence; the control terminal of the register is connected to the second-level test port through the first-level test port and the bus buffer 20.

[0035] In the read / write test, the address signal and write protection control signal are provided through registers. The address port, communication bus port and write protection control port used for electrical testing in the first-level test port have no input and can be reused for the parallel layout of the communication bus in the read / write test. In this embodiment, except for the power line, there are 6 reusable electrical ports in the first-level test port, which can realize the parallel layout of three sets of IIC communication buses and correspondingly set up three sets of first-level test modules 100.

[0036] In an optional embodiment, the secondary test module can include more primary test modules 100, arranged in groups, with the primary test modules 100 within each group cascaded. After the previous stage test is completed, the subsequent stage test is activated, and the number of primary test modules 100 tested simultaneously can be controlled to be no more than three. Correspondingly, the bidirectional voltage level converter 21 is provided with multiple sets of communication bus channels, each communication bus channel being connected to at least one primary test module 100.

[0037] Specifically, the bus buffer 20 can be a 74AHC125-EP type bus buffer, which can improve signal reliability. The bidirectional voltage level converter 21 can be a TCA9406 type converter, and the second analog switch 22 can be a 74CBT3257C type switch. The quantity can be selected adaptably to meet the requirements.

[0038] The memory chip test circuit provided by this utility model can be used for testing IIC interface EEPROM memory of the 24CXX series. The first switch U11 and the second switch U12 are selected as SN74CBT3257C type switches, which can avoid the problem of port voltage misleading the first analog switch in the continuity test of the protection diode.

[0039] The memory chip test circuit provided by this utility model sets up a first test circuit and a second test circuit in parallel, which can be used for testing different test items. When performing the test item corresponding to the first test circuit, the address signal of the next memory under test can be sent to the second test circuit in advance and stored in a register. After the test item corresponding to the first test circuit is completed, only a switching instruction needs to be sent to the register to send out the address signal stored in the register and control the first analog switch to switch the input port of the corresponding channel. This can effectively reduce the address signal update waiting time, improve the switching speed, and the time consumed by the register update output is less than the channel switching time of the first analog switch. When the first analog switch is switched, the input signal of the corresponding channel of the first analog switch can be stabilized, avoiding signal glitches, shielding the signal interference in the switching action of the first analog switch, and improving the test reliability.

[0040] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0041] The embodiments described above are merely illustrative of several specific implementations of this utility model, and while the descriptions are detailed, they should not be construed as limiting the scope of protection of this utility model. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these modifications and improvements all fall within the scope of protection of this utility model. Therefore, the scope of protection of this utility model patent should be determined by the appended claims.

Claims

1. A memory chip testing circuit, characterized in that, The system includes a primary test module, comprising: a chip-under-test (DUT) connection board, a primary test interface connected to a tester, and a primary transfer circuit connecting the primary test interface to the DUT connection board. The test bus of the chip under test connection board has multiple test bits connected in parallel, and the first-level transmission circuit includes a first analog switch and a register; The first side port of each channel of the first analog switch is connected to the test bus one by one. The second side port of each channel of the first analog switch is a parallel port, and a first test circuit and a second test circuit are connected in parallel. One of the first test circuit and the second test circuit is used for electrical testing, and the other is used for read and write testing. The address lines and write protection control lines in the second test circuit, as well as the control terminal of the first analog switch, are connected to the register, and the control terminal of the register is connected to the first-level test port; The communication bus in the second test loop and the first test loop are connected to the first-level test port.

2. The memory chip test circuit according to claim 1, characterized in that, It also includes a secondary test module, in which multiple primary test modules are connected in parallel, as well as a bidirectional voltage level converter, a second analog switch, and a bus buffer. The first test circuit is directly connected to the secondary test port of the secondary test module through the primary test port and the connecting line; The communication bus in the second test circuit is connected to the address port and write protection control port in the second-level test port in sequence through the first-level test port, the bidirectional voltage level converter and the second analog switch; The control terminal of the register is connected to the secondary test port through the primary test port and the bus buffer; The secondary test port is connected to the test machine.

3. The memory chip test circuit according to claim 2, characterized in that, The bidirectional voltage level converter is provided with multiple communication bus channels, and each communication bus channel is connected to at least one of the first-level test modules.

4. The memory chip test circuit according to claim 1, characterized in that, The registers include shift registers.

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