Highly reliable trench gate silicon carbide vdmos
By dividing the conductive channels of silicon carbide VDMOS into lateral and vertical sections and combining them with a floating gate structure, the problem of long-term conduction caused by single-event gate breakdown is solved, thereby improving the reliability of the device and the stability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- GLOBAL POWER TECH CO LTD
- Filing Date
- 2025-05-07
- Publication Date
- 2026-05-29
AI Technical Summary
Silicon carbide VDMOS devices are less resistant to single-event radiation due to gate oxide quality issues in commercial aerospace and deep space exploration. This results in the device remaining on for an extended period during single-event gate breakdown, affecting device reliability.
A highly reliable trench-gate silicon carbide VDMOS is designed by dividing the conductive channel of the device into two directions, lateral and longitudinal, to construct a floating gate structure. This enables dual conductive channel control of the device and maintains withstand voltage capability during dielectric breakdown. The floating gate is constructed to shield the gate-drain capacitance, thereby improving the switching speed and protecting the device.
When a single-event gate breaks down, the device stops conducting, maintains its withstand voltage capability, improves system stability and device reliability, and ensures normal system operation.
Smart Images
Figure CN224306192U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a high-reliability trench gate silicon carbide VDMOS. Background Technology
[0002] Silicon carbide VDMOS's inherent wide bandgap characteristics can effectively meet the requirements of high total dose radiation resistance. However, due to its gate oxide quality issues, its radiation resistance to single particles is relatively weak, which limits its application in commercial aerospace, deep space exploration and other fields. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a highly reliable trench gate silicon carbide VDMOS. By splitting the conductive channel of the device, the device will not have a long-term conduction problem when a single-particle gate breakdown occurs in a single direction, thus ensuring the device is turned off and providing a large current freewheeling current for the body diode, thereby improving the reliability of the device.
[0004] This invention provides a high-reliability trench-gate silicon carbide VDMOS, comprising:
[0005] silicon carbide substrate;
[0006] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has grooves.
[0007] P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer;
[0008] A P-type well region is provided, wherein the lower side of the P-type well region is connected to the upper side of the drift layer, and the outer side of the P-type well region is connected to the inner side of the P-type source region; an N-type source region is provided on the P-type well region.
[0009] An insulating dielectric layer is provided at its lower part within the groove, and the insulating dielectric layer is connected to the P-type well region and the N-type source region; a floating gate and a trench are provided within the insulating dielectric layer; the floating gate is located below the trench;
[0010] A gate metal layer is disposed within the trench;
[0011] A source metal layer, wherein the source metal layer is connected to the N-type source region and the P-type source region respectively;
[0012] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0013] The advantages of this utility model are:
[0014] I. This utility model divides the conductive channel of the device into two directions, transverse and longitudinal. When the device is broken down by a single particle in the transverse or longitudinal dielectric of the device gate insulation, the device will no longer conduct, but the withstand voltage of the device can still be maintained, which will not affect the working state of the system and improve the stability of the system.
[0015] II. The gate metal layer of this utility model can control the formation of lateral conductive channels and longitudinal conductive channels, so that the gate metal layer can control the two conductive channels of the device.
[0016] Third, this utility model constructs a floating gate, which has two functions: one is to shield the gate from the drain capacitance and improve the switching speed of the device; the other is to form a protective vertical gate structure for the device, which provides effective buffering in the event of single-particle damage. Attached Figure Description
[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0018] Figure 1 This is a schematic diagram of a high-reliability trench-gate silicon carbide VDMOS according to this utility model.
[0019] Figure 2 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 1 .
[0020] Figure 3 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 2 .
[0021] Figure 4 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 3 .
[0022] Figure 5 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 4 .
[0023] Figure 6 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 5 .
[0024] Figure 7 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 6 .
[0025] Figure 8 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 7 .
[0026] Figure 9 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 8 .
[0027] Figure 10 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 9 .
[0028] Figure 11 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 .
[0029] Figure 12 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 one.
[0030] Figure 13 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 two.
[0031] Figure 14 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 three.
[0032] Figure 15 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 Four.
[0033] Figure 16 This is a cross-sectional view of the process of a high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 five. Detailed Implementation
[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0039] like Figures 1 to 16 As shown, this application embodiment provides a high-reliability trench-gate silicon carbide VDMOS, comprising:
[0040] Silicon carbide substrate 1;
[0041] A drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; a groove 21 is provided on the drift layer 2;
[0042] P-type source region 3, the lower side of which is connected to the upper side of the drift layer 2;
[0043] P-type well region 4, the lower side of the P-type well region 4 is connected to the upper side of the drift layer 2, and the outer side of the P-type well region 4 is connected to the inner side of the P-type source region 3; an N-type source region 41 is provided on the P-type well region 4;
[0044] An insulating dielectric layer 5 is disposed at its lower part within the groove 21. The insulating dielectric layer 5 is connected to the P-type well region 4 and the N-type source region 41. A floating grid 51 and a trench 52 are provided within the insulating dielectric layer 5. The floating grid 51 is located below the trench 52.
[0045] A gate metal layer 6 is disposed within the trench 52;
[0046] Source metal layer 7, which is connected to the N-type source region 41 and the P-type source region 3 respectively;
[0047] And a drain metal layer 8, which is connected to the lower side of the silicon carbide substrate 1.
[0048] In this embodiment, preferably, the trench 52 is an inverted convex shape, and the gate metal layer 6 matches the trench 52.
[0049] In this embodiment, preferably, the upper side of the levitation gate 51 is lower than the upper side of the drift layer 2.
[0050] In this embodiment, preferably, the thickness of the P-type well region 4 is equal to the sum of the thickness of the N-type source region 41 and the thickness of the P-type source region 3.
[0051] In this embodiment, preferably, the doping concentration of the P-type source region 3 is greater than the doping concentration of the P-type well region 4.
[0052] In this embodiment, preferably, the doping concentration of the N-type source region 41 is greater than the doping concentration of the P-type well region 4.
[0053] like Figures 1 to 16 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:
[0054] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 8, and epitaxially grow on the upper side of silicon carbide substrate 1 to form drift layer 2.
[0055] Step 2: Form a barrier layer 9 above the drift layer 2, etch the barrier layer 9 to form a via, and implant ions to form a P-type source region 3;
[0056] Step 3: Remove the barrier layer from Step 2, reform the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions to form a P-type well region 4;
[0057] Step 4: Remove the barrier layer from Step 3, reform the barrier layer 9, etch the barrier layer 9 to form a via, and implant ions to form an N-type source region 41;
[0058] Step 5: Remove the barrier layer from step 4, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the drift layer 2 and the P-type well region 4 to form a groove 21, and deposit to form the first insulating layer 53.
[0059] Step 6: Remove the barrier layer from step 5, reform the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal, and form a floating gate 51;
[0060] Step 7: Remove the barrier layer from step 6, reform the barrier layer 9, etch the barrier layer 9 to form a through hole, and oxidize to form a second insulating layer 54. The second insulating layer 54 has a first groove 541 inside.
[0061] Step 8: Remove the barrier layer from step 7, reform the barrier layer 9, etch the barrier layer 9 to form a via, deposit metal, and form the first metal layer 61.
[0062] Step 9: Remove the barrier layer from step 8, reform the barrier layer 9, etch the barrier layer 9 to form a via, and etch the drift layer 2 and the second insulating layer 54 to the upper side of the P-type well region 4, and deposit to form the third insulating layer 55.
[0063] Step 10: Remove the barrier layer from step 9, reform the barrier layer 9, etch the barrier layer 9 to form a via, deposit and form the fourth insulating layer 56. The insulating dielectric layer 5 includes the first insulating layer 53, the second insulating layer 54, the third insulating layer 55 and the fourth insulating layer 56. The insulating dielectric layer 5 has a trench 52.
[0064] Step 11: Remove the barrier layer from step 10, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the fourth insulating layer 56, deposit metal to form a second metal layer 62, and the gate metal layer 6 includes a first metal layer 61 and a second metal layer 62.
[0065] Step 12: Remove the barrier layer from Step 11, reform the barrier layer 9, etch the barrier layer 9 to form a via, etch the drift layer 2 to the upper side of the P-type source region 3, deposit metal to form the source metal layer 7, remove the barrier layer 9, and complete the fabrication.
[0066] Another embodiment of this utility model includes a drain metal layer 8, an N-type silicon carbide substrate 1, an N-type drift layer 2, an insulating dielectric layer 5, a floating gate 51, a P-type well region 4, a P-type source region 3, an N-type source region 41, a gate metal layer 6, and a source metal layer 7; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 6-10e16cm. -3 The doping concentration of P-type well region 4 is 6-10e16cm. -3 The doping concentration of P-type source region 3 is 1-5e19cm. -3 The insulating dielectric layer 5 can be made of silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm. -3 ;
[0067] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration of the P-type well region 4 is to achieve the breakdown voltage of the pn junction structure of the device when the drain of the device is subjected to high voltage. The doping concentration of the P-type source region 3 is to reduce the contact resistance between the P-type source region 3 and the source metal layer 7, thereby reducing the parasitic diode conduction loss of the device.
[0068] The thickness of the N-type silicon carbide substrate 1 is 1 μm, and the thickness of the N-type drift layer 2 is 50-100 μm, adjusted within this range according to different requirements for the device's withstand voltage characteristics. The maximum thickness of the insulating dielectric layer 5 is 1.5 μm. The thickness of the insulating dielectric at the bottom of the floating gate 51 is 100-200 nm. 100 nm can improve the resistance to single-particle interference. To reduce the difficulty of the manufacturing process, the thickness of the floating gate 51 is 200 nm. The thickness of the insulating dielectric between the floating gate 51 and the device gate metal layer 6 is 100-200 nm. The width of the insulating dielectric from the device gate metal layer 6 to the P-type well regions 4 on its left and right sides is 50 nm. This is for... To ensure gate control capability, the thickness of the insulating medium above the N-type source region 41 and the P-type well region 4 is 50 nm, and the thickness of the gate metal layer 6 above the P-type well region 4 is 350 nm. This is to ensure the gate control capability of the device and ensure the formation of the lateral conductive channel. The maximum thickness of the P-type well region 4 is 600 nm, the thickness of the N-type source region 41 is 300 nm, and the maximum thickness of the gate metal layer 6 is 900 nm. The lower side of the gate metal layer 6 is 100 nm higher than the lower side of the P-type well region 4. This is to avoid the gate insulation medium reliability problem caused by the electric field concentration at the corner of the insulating medium. The thickness of the source metal layer 7 is 700 nm, and the thickness of the P-type source region 3 is 300 nm.
[0069] The width of the floating gate 51 is 1μm, the width of the lower part of the gate metal layer 6 is 1.4μm, the width of the upper part is 2.4μm, the maximum width of the P-type well region 4 is 800nm, and the width of the N-type source region 41 is 400nm. This is to ensure that the gate metal layer 6 covers the lateral conductive channel and ensures gate control capability. The width of the P-type source region 3 is 1μm. This is to ensure that the device can achieve freewheeling when it is not working, to ensure the derating operation of the power system, and to improve reliability. The width of the insulating dielectric between the gate metal layer 6 and the source metal layer 7 is 300nm. This is to ensure the isolation between the gate metal and the source metal.
[0070] This invention divides the conductive channel of the device into two directions, transverse and longitudinal. When the device is broken down by a single particle in the transverse or longitudinal dielectric of the gate insulation, the device will no longer conduct, but the withstand voltage of the device can still be maintained, which will not affect the working state of the system and improve the stability of the system.
[0071] The gate metal layer 6 of this invention can control the formation of lateral conductive channels and longitudinal conductive channels, so that the gate metal layer 6 can control the two conductive channels of the device.
[0072] This invention constructs a floating gate 51, which has two functions: one is to shield the gate from the drain capacitance, thereby improving the switching speed of the device; the other is to form a protective vertical gate structure for the device, providing effective buffering in the event of single-particle damage.
[0073] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A high-reliability trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer is provided with grooves; P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer; A P-type well region is provided, wherein the lower side of the P-type well region is connected to the upper side of the drift layer, and the outer side of the P-type well region is connected to the inner side of the P-type source region; an N-type source region is provided on the P-type well region. An insulating dielectric layer is provided at its lower part within the groove, and the insulating dielectric layer is connected to the P-type well region and the N-type source region; The insulating dielectric layer is provided with a suspended grid and trenches; The suspended grid is located below the trench; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the N-type source region and the P-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The trench is an inverted convex shape, and the gate metal layer matches the trench.
3. The high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The upper side of the suspended grid is lower than the upper side of the drift layer.
4. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the P-type well region is equal to the sum of the thickness of the N-type source region and the thickness of the P-type source region.
5. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region.
6. A high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the N-type source region is greater than the doping concentration of the P-type well region.