A method, apparatus, equipment, and medium for clock tree synthesis processing based on the critical path.

Abstract

This disclosure relates to a method, apparatus, device, and medium for clock tree synthesis processing based on critical paths. The method includes: determining a critical path in a chip; wherein the chip includes multiple modules and multiple IPs; adjusting the positions of the modules and / or IPs in the chip based on the critical path to obtain an updated chip layout; generating a clock tree based on the critical path and the chip layout, the clock tree including clock sources and multiple nodes; and performing clock tree synthesis processing based on a preset clock skew to reduce the clock skew of the critical path. This method considers the critical path in the chip during clock tree synthesis processing, reducing the clock skew of the critical path, ensuring that the clock tree in complex chips has small clock tree delays and clock skew, and a balanced clock tree, thereby ensuring timing consistency in the chip physical design and achieving the goal of reducing chip area and chip power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, specifically to a clock tree synthesis processing method, apparatus, device, and medium based on critical path. Background Technology

[0002] Traditional H-type clock tree synthesis, when the number of internal IPs (Intellectual Property) is limited and the placement area of ​​standard cells is relatively regular, uses a large number of buffers for nodes with high output fanout in the clock tree in the hope of achieving a balanced clock tree. However, as chip designs become larger and the number of IPs used in chips increases, the placement area of ​​standard cells within the chip becomes extremely irregular, making it difficult for the traditional binary tree-based H-type clock tree to exert its original advantages. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a clock tree synthesis processing method, apparatus, device and medium based on critical path.

[0004] According to a first aspect of the present disclosure, a clock tree synthesis processing method based on a critical path is provided, the method comprising:

[0005] Identify the critical paths within the chip; wherein the chip comprises multiple modules and multiple IPs;

[0006] Based on the critical path, the positions of the modules and / or IPs in the chip are adjusted to obtain an updated chip layout;

[0007] Based on the critical path and the chip layout, a clock tree is generated, which includes clock sources and multiple nodes.

[0008] Clock tree synthesis is performed based on a preset clock skew to reduce the clock skew of the critical path.

[0009] In some embodiments, the critical path includes a first critical path between two modules and a second critical path within a module. Adjusting the positions of the modules and / or the IPs in the chip based on the critical paths to obtain an updated chip layout includes:

[0010] When the number of first critical paths between the two modules exceeds a first threshold, the two modules are placed adjacent to each other to obtain an updated chip layout; wherein, there are no other modules between the two adjusted modules; and / or,

[0011] When the number of second critical paths within the module exceeds a second threshold, the IP associated with the module is placed within the module to obtain an updated chip layout.

[0012] In some embodiments, generating a clock tree based on the critical path and the chip layout includes:

[0013] Based on the critical path and the chip layout, the clock source location and multiple first node locations of the clock tree to be generated are determined;

[0014] Based on the multiple first node positions, multiple second node positions are automatically generated, wherein the level of the second node is lower than the level of the first node;

[0015] The clock tree is determined based on the clock source location, the multiple first node locations, and the multiple second node locations.

[0016] In some embodiments, determining the clock source location and multiple first node locations of the clock tree to be generated based on the critical path and the chip layout includes:

[0017] Based on the critical path and the chip layout, the middle position of the chip is determined as the clock source position, and the position where two adjacent modules are connected is determined as the first node position.

[0018] In some embodiments, determining the critical path in the chip includes:

[0019] Static timing analysis is performed on the chip to obtain the timing margin of each path in the chip;

[0020] The path whose timing margin is less than the third threshold is identified as the critical path.

[0021] In some embodiments, generating a clock tree based on the critical path and the chip layout includes:

[0022] When there are multiple clocks in the chip, multiple clock trees are generated based on the critical path and the chip layout; wherein, there is no intersection between the multiple clock trees.

[0023] In some embodiments, the clock tree is an H-type clock tree.

[0024] According to a second aspect of the present disclosure, a clock tree synthesis processing apparatus based on a critical path is provided, the apparatus comprising:

[0025] A critical path determination module is configured to determine the critical path in a chip; wherein the chip includes multiple modules and multiple IPs;

[0026] The chip layout update module is configured to adjust the position of the module and / or the IP in the chip based on the critical path to obtain an updated chip layout.

[0027] A clock tree generation module is configured to generate a clock tree based on the critical path and the chip layout, the clock tree including a clock source and multiple nodes;

[0028] The clock tree synthesis module is configured to perform clock tree synthesis processing based on a preset clock skew, so as to reduce the clock skew of the critical path.

[0029] In some embodiments, the critical path includes a first critical path between two modules and a second critical path within a module, and the chip layout update module is configured to:

[0030] When the number of first critical paths between the two modules exceeds a first threshold, the two modules are placed adjacent to each other to obtain an updated chip layout; wherein, there are no other modules between the two adjusted modules; and / or,

[0031] When the number of second critical paths within the module exceeds a second threshold, the IP associated with the module is placed within the module to obtain an updated chip layout.

[0032] In some embodiments, the clock tree generation module is configured to:

[0033] Based on the critical path and the chip layout, the clock source location and multiple first node locations of the clock tree to be generated are determined;

[0034] Based on the multiple first node positions, multiple second node positions are automatically generated, wherein the level of the second node is lower than the level of the first node;

[0035] The clock tree is determined based on the clock source location, the multiple first node locations, and the multiple second node locations.

[0036] In some embodiments, the clock tree generation module is configured to:

[0037] Based on the critical path and the chip layout, the middle position of the chip is determined as the clock source position, and the position where two adjacent modules are connected is determined as the first node position.

[0038] In some embodiments, the critical path determination module is configured to:

[0039] Static timing analysis is performed on the chip to obtain the timing margin of each path in the chip;

[0040] The path whose timing margin is less than the third threshold is identified as the critical path.

[0041] In some embodiments, the clock tree generation module is configured to:

[0042] When there are multiple clocks in the chip, multiple clock trees are generated based on the critical path and the chip layout; wherein, there is no intersection between the multiple clock trees.

[0043] In some embodiments, the clock tree is an H-type clock tree.

[0044] According to a third aspect of the present disclosure, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the method as described in the first aspect.

[0045] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0046] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0047] The method provided in this disclosure first updates the chip layout based on the critical path in the chip, then generates a clock tree based on the critical path and the updated chip layout, and finally performs clock tree synthesis processing. That is, when performing clock tree synthesis processing, the critical path in the chip is considered to reduce the clock skew of the critical path, ensuring that the clock tree in the complex chip has small clock tree delay and clock skew, and a balanced clock tree, thereby ensuring the timing consistency in the chip physical design and achieving the purpose of reducing chip area and chip power consumption.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0050] Figure 1 This is a schematic diagram of an H-type clock tree according to an exemplary embodiment.

[0051] Figure 2This is a flowchart illustrating a clock tree synthesis processing method based on a critical path, according to an exemplary embodiment.

[0052] Figure 3 This is a flowchart illustrating a clock tree synthesis processing method based on a critical path, according to an exemplary embodiment.

[0053] Figure 4 This is a schematic diagram illustrating a chip design according to an exemplary embodiment.

[0054] Figure 5 This is a flowchart illustrating a clock tree synthesis processing method based on a critical path, according to an exemplary embodiment.

[0055] Figure 6 This is a flowchart illustrating a clock tree synthesis processing apparatus based on a critical path, according to an exemplary embodiment.

[0056] Figure 7 This is a block diagram of a computer device according to an exemplary embodiment.

[0057] In the picture:

[0058] 700 - Computer equipment; 701 - Computing unit; 702 - ROM; 703 - RAM; 704 - Bus; 705 - Input / output interface; 706 - Input unit; 707 - Output unit; 708 - Storage unit; 709 - Communication unit. Detailed Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0060] Figure 1 This is a schematic diagram of an H-type clock tree according to an exemplary embodiment, see [link to example]. Figure 1 , Figure 1 The H-type clock tree shown is the ideal clock tree, from... Figure 1It can be seen that even though two adjacent flip-flops (e.g., A and B) are in two separate sub-clock trees, the clock skew and clock delay between them are relatively small due to the overall balance of the clock trees. As chip designs become larger and the number of IPs used in a chip increases, the available space for standard cells within the chip becomes extremely irregular. This makes it difficult to obtain a balanced clock tree using the original clock tree synthesis methods, and consequently, the traditional H-type clock tree based on binary trees loses its original advantages.

[0061] This disclosure provides a clock tree synthesis method based on critical paths. When performing clock tree synthesis, the critical paths in the chip are considered to reduce the clock skew of the critical paths, ensuring that the clock tree in the complex chip has small clock tree delay and clock skew, and a balanced clock tree, thereby ensuring the timing consistency in the chip physical design, and achieving the purpose of reducing chip area and chip power consumption.

[0062] The method provided in this disclosure is executed by a computer device, which can be a device with chip design capabilities, such as a mobile phone, tablet computer, laptop computer, desktop computer, or wearable device.

[0063] Figure 2 This is a flowchart illustrating a clock tree synthesis processing method based on a critical path, according to an exemplary embodiment, executed by an electronic device. See also... Figure 2 The method includes the following steps:

[0064] Step S201: Determine the critical path in the chip; wherein the chip includes multiple modules and multiple IPs.

[0065] The chip may include multiple modules and multiple IPs, and each module may include IPs and standard cells. A critical path is a path whose timing slack is less than a preset threshold. There are multiple critical paths in the chip, including a first critical path between two modules and a second critical path within a module.

[0066] Step S202: Based on the critical path, adjust the positions of modules and / or IPs in the chip to obtain the updated chip layout.

[0067] To make the chip layout more reasonable, the positions of modules and / or IPs in the chip are adjusted based on the critical path. In the updated chip layout, modules with more critical paths between modules are placed close together, and modules with more critical paths within a module are placed close to the relevant IPs. In other words, the relevant IPs are placed in the module.

[0068] It should be noted that when making adjustments, if there are many critical paths between modules but few critical paths within a module, you can adjust only the position of the module; if there are few critical paths between modules but many critical paths within a module, you can adjust only the position of the IP address; if there are many critical paths between modules and many critical paths within a module, you should adjust both the position of the module and the position of the IP address.

[0069] Step S203: Based on the critical path and chip layout, generate a clock tree, which includes clock sources and multiple nodes.

[0070] To make the clock tree in the chip more balanced, the clock tree is generated by considering the critical path and chip layout, that is, generating the clock source location and node location. This allows the generated clock tree to take into account the critical path and reduce clock latency and clock skew. The clock tree is an H-shaped clock tree.

[0071] Step S204: Perform clock tree synthesis processing based on preset clock skew to reduce the clock skew of the critical path.

[0072] The preset clock skew is a pre-set clock skew that is smaller than the actual clock skew. For example, if the actual clock skew is 10, then the preset clock skew is 7. By setting a clock skew smaller than the actual clock skew, the clock skew of the critical path is reduced, thereby preventing a decrease in the timing margin of the critical path.

[0073] The method provided in this disclosure first updates the chip layout based on the critical path in the chip, then generates a clock tree based on the critical path and the updated chip layout, and finally performs clock tree synthesis processing. That is, when performing clock tree synthesis processing, the critical path in the chip is considered to reduce the clock skew of the critical path, ensuring that the clock tree in the complex chip has small clock tree delay and clock skew, and a balanced clock tree, thereby ensuring the timing consistency in the chip physical design and achieving the purpose of reducing chip area and chip power consumption.

[0074] Figure 3 This is a flowchart illustrating a clock tree synthesis processing method based on a critical path, according to an exemplary embodiment, executed by an electronic device. See also... Figure 3 The method includes the following steps:

[0075] Step S301: Determine the critical path in the chip. The critical path includes a first critical path between two modules and a second critical path within a module.

[0076] In some embodiments, static timing analysis is performed on the chip to obtain the timing margin of each path in the chip; the paths with timing margins less than a third threshold are identified as critical paths. When the timing margin is less than the third threshold, the timing margin does not meet the constraint requirements; therefore, the paths with timing margins less than the third threshold are identified as critical paths.

[0077] Optionally, paths with a timing margin less than the third threshold are identified as critical paths, including: when the timing margin of a path is less than the third threshold and the path is between two modules, the path is identified as the first critical path; when the timing margin of a path is less than the third threshold and the path is within a module, the path is identified as the second critical path.

[0078] Step S302: When the number of first critical paths between two modules is greater than the first threshold, the two modules are placed adjacent to each other to obtain the updated chip layout.

[0079] When the number of critical paths between two modules exceeds a first threshold, it indicates that there are many critical paths between them. Therefore, it's best for these two modules to be as close as possible within the chip. Thus, the module positions are adjusted to place them adjacent to each other. The first threshold is a pre-set value. After adjustment, there are no other modules between the two modules.

[0080] In some embodiments, when the number of first critical paths between a module and multiple modules all exceeds a first threshold, the module needs to be placed adjacent to the other multiple modules. For example, if the module is module 1 and the multiple modules include module 2 and module 3, then module 2 can be placed to the left of module 1 and module 3 can be placed to the right of module 1.

[0081] In some embodiments, when the number of first critical paths between multiple modules exceeds a first threshold, when adjusting the module positions, it is necessary to place two modules adjacent to each other as much as possible while ensuring the chip layout. The condition for meeting this condition is that the number of first critical paths between two modules exceeds the first threshold.

[0082] See one example. Figure 4 The diagram shown is a schematic of the chip design. Figure 4 The chip shown comprises eight modules, separated by white dashed lines. The first module in the first row, the first and third modules in the second row, and the two modules in the third row contain numerous IPs. There are critical paths between the six modules in the first and second rows. Therefore, the six modules in the first and second rows are placed close together, and the number of critical paths between any two adjacent modules is less than the number of critical paths between any two non-adjacent modules.

[0083] Step S303: When the number of second critical paths inside the module is greater than the second threshold, the IP related to the module is placed in the module to obtain the updated chip layout.

[0084] When the number of second critical paths within a module exceeds a second threshold, it indicates that there are many second critical paths within the module. In this case, the closer the IPs related to the module are to the module in the chip, the better. Therefore, by adjusting the position of the IPs related to the module, the module-related IPs are placed within the module. The second threshold is a preset value.

[0085] It should be noted that the present invention describes the example of executing step S302 first and then step S303. In another embodiment, step S303 can be executed first and then step S302. The present invention does not restrict the execution order of steps S302 and S303.

[0086] Step S304: Based on the critical path and chip layout, determine the clock source location and multiple first node locations of the clock tree to be generated.

[0087] In related technologies, clock trees in chips are directly generated using software. However, in this embodiment, due to the irregular placement of IPs and standard cells in the chip, the clock tree generated directly using software has poor balance. To obtain a clock tree with better balance, the clock source positions and multiple first node positions of the clock tree to be generated are first determined based on the critical path and chip layout. Each first node includes at least a level 1 node.

[0088] In some embodiments, based on the critical path and chip layout, the middle position of the chip is determined as the clock source position, and the position where two adjacent modules are connected is determined as the first node position.

[0089] See one example. Figure 4 The diagram shown is as follows. Figure 4 In the diagram, triangles represent clock sources, squares represent level 1 nodes, and circles represent level 2 nodes. From... Figure 4 As can be seen, the clock source is located in the middle of the chip, and the four level-1 nodes are located at the connection points between the two modules. The level-1 nodes are not set up in the traditional H-shaped clock tree format, but rather to reduce clock skew on the critical path. Figure 4 The four locations shown are each set with a level 1 node.

[0090] In this embodiment of the disclosure, the clock source is located in the middle of the chip to reduce clock delay, and the first node is located at the position where two adjacent modules are connected to reduce clock skew.

[0091] Step S305: Based on multiple first node positions, automatically generate multiple second node positions, where the level of the second node is lower than that of the first node.

[0092] When the first node includes level 1 nodes, based on the position of the level 1 nodes, the positions of nodes of lower level than level 1, starting from that level 1 node, are automatically generated; when the first node includes level 2 nodes, based on the position of the level 2 nodes, the positions of nodes of lower level than level 2, starting from that level 2 node, are automatically generated. Here, "automatically generated" means that the nodes are generated by calling software.

[0093] See one example. Figure 4 The diagram shown illustrates that when the first node includes level 1 nodes, it automatically generates nodes based on the level 1 nodes. Figure 4 The diagram shows the positions of level 2 nodes and lower-level nodes. When the first node includes level 2 nodes, level 3 nodes and lower-level nodes are automatically generated based on the level 2 nodes.

[0094] Step S306: Determine the clock tree based on the clock source location, multiple first node locations, and multiple second node locations.

[0095] Once the clock source location, multiple first node locations, and multiple second node locations are determined, the clock tree is established.

[0096] It should be noted that the above embodiment describes the generation process of a clock tree based on the existence of one clock tree in the chip. In another embodiment, when multiple clocks exist in the chip, since the paths between different clock domains are false paths or multi-cycle paths, and the different clock domains do not intersect, multiple clock trees are generated based on the critical path and chip layout when multiple clocks exist in the chip; wherein, there is no intersection between the multiple clock trees. The generation process of each clock tree is the same as the generation process of the clock tree in the above embodiment, and will not be repeated here.

[0097] Step S307: Perform clock tree synthesis processing based on preset clock skew to reduce the clock skew of the critical path.

[0098] The method provided in this disclosure first updates the chip layout based on the critical path in the chip, then generates a clock tree based on the critical path and the updated chip layout, and finally performs clock tree synthesis processing. That is, when performing clock tree synthesis processing, the critical path in the chip is considered to reduce the clock skew of the critical path, ensuring that the clock tree in the complex chip has small clock tree delay and clock skew, and a balanced clock tree, thereby ensuring the timing consistency in the chip physical design and achieving the purpose of reducing chip area and chip power consumption.

[0099] In one example, the flowchart of the clock tree synthesis processing method based on the critical path is as follows: Figure 5 As shown, see Figure 5 The method includes the following steps:

[0100] Step S501: Analyze the critical path after chip synthesis.

[0101] Step S502: Optimize chip layout based on critical paths: When the number of first critical paths between two modules is greater than a first threshold, place the two modules adjacent to each other; when the number of second critical paths within a module is greater than a second threshold, place the IP related to that module in that module.

[0102] Step S503: Based on the critical path and chip layout, determine the clock source position, level 1 node position, and level 2 node position of the H-type clock tree, so that the main structure of the clock tree takes into account the critical path, thereby enabling the module-level clock tree to be automatically generated by software using H-type clock tree synthesis technology.

[0103] The module-level clock tree refers to the bottom part of the clock tree starting from the level 2 node. This module-level clock tree is also the sub-clock tree starting from the level 2 node in the complete clock tree.

[0104] Step S504: Set a smaller clock skew for clock tree synthesis to ensure that the critical path has a smaller clock skew and that the critical path still has a certain timing margin after routing in the chip.

[0105] The "smaller clock skew setting" refers to a clock skew that is smaller than the actual clock skew. For example, if the actual clock skew is 10, then the "smaller clock skew setting" is 7.

[0106] The implementation methods for steps S501-S504 are described above. Figure 3 The embodiments shown will not be described in detail here.

[0107] Figure 6 This is a flowchart illustrating a clock tree synthesis processing apparatus based on a critical path according to an exemplary embodiment. See also... Figure 6 The device includes:

[0108] Critical path determination module 601 is configured to determine the critical path in a chip; wherein the chip includes multiple modules and multiple IPs;

[0109] Chip layout update module 602 is configured to adjust the position of modules and / or IPs in the chip based on the critical path to obtain an updated chip layout.

[0110] Clock tree generation module 603 is configured to generate a clock tree based on the critical path and chip layout. The clock tree includes clock sources and multiple nodes.

[0111] The clock tree synthesis module 604 is configured to perform clock tree synthesis processing based on a preset clock skew, so as to reduce the clock skew of the critical path.

[0112] In some embodiments, the critical path includes a first critical path between two modules and a second critical path within a module. The chip layout update module 602 is configured to:

[0113] When the number of first critical paths between two modules exceeds a first threshold, the two modules are placed adjacently to obtain an updated chip layout; wherein, there are no other modules between the two adjusted modules; and / or,

[0114] When the number of second critical paths within a module exceeds a second threshold, the IP associated with the module is placed within the module to obtain an updated chip layout.

[0115] In some embodiments, the clock tree generation module 603 is configured to:

[0116] Based on the critical path and chip layout, the clock source location and multiple first node locations of the clock tree to be generated are determined.

[0117] Based on multiple first node positions, multiple second node positions are automatically generated, with the level of the second node being lower than that of the first node;

[0118] The clock tree is determined based on the clock source location, multiple first node locations, and multiple second node locations.

[0119] In some embodiments, the clock tree generation module 603 is configured to:

[0120] Based on the critical path and chip layout, the middle position of the chip is determined as the clock source position, and the position where two adjacent modules are connected is determined as the first node position.

[0121] In some embodiments, the critical path determination module 601 is configured to:

[0122] Perform static timing analysis on the chip to obtain the timing margin of each path in the chip;

[0123] Paths with a timing margin less than the third threshold are identified as critical paths.

[0124] In some embodiments, the clock tree generation module 603 is configured to:

[0125] When there are multiple clocks in a chip, multiple clock trees are generated based on the critical path and chip layout; there is no overlap between the multiple clock trees.

[0126] In some embodiments, the clock tree is an H-type clock tree.

[0127] Each module in the aforementioned clock tree synthesis processing device based on the critical path can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0128] In one exemplary embodiment, a computer device is provided, including a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the above-described clock tree synthesis processing method based on critical path.

[0129] In one exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements the above-described clock tree synthesis processing method based on the critical path. The computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device, etc.

[0130] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described clock tree synthesis method based on critical path.

[0131] refer to Figure 7 The following description serves as a structural block diagram of the computer device disclosed herein. The computer device includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. The RAM 703 may also store various programs and data required for the operation of the computer device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0132] Multiple components in computer device 700 are connected to I / O interface 705, including: input unit 706, output unit 707, storage unit 708, and communication unit 709. Input unit 706 can be any type of device capable of inputting information into computer device 700. Input unit 706 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of computer device 700, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 707 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 708 may include, but is not limited to, hard disk and optical disk. Communication unit 709 allows computer device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0133] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as the shooting method. For example, in some embodiments, the shooting method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the computer device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of the shooting method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the shooting method by any other suitable means (e.g., by means of firmware).

[0134] The computer device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described imaging method.

[0135] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0136] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A clock tree synthesis processing method based on the critical path, characterized in that, The method includes: Identify the critical paths within the chip; wherein the chip comprises multiple modules and multiple IPs; Based on the critical path, the positions of the modules and / or IPs in the chip are adjusted to obtain an updated chip layout; Based on the critical path and the chip layout, a clock tree is generated, which includes clock sources and multiple nodes. Clock tree synthesis is performed based on a preset clock skew to reduce the clock skew of the critical path. The preset clock skew is a pre-set clock skew that is smaller than the actual clock skew. The determination of the critical path in the chip includes: Static timing analysis is performed on the chip to obtain the timing margin of each path in the chip; The path whose timing margin is less than the third threshold is identified as the critical path; The critical path includes a first critical path between two modules and a second critical path within a module. Adjusting the positions of the modules and / or IPs in the chip based on the critical paths to obtain an updated chip layout includes: When the number of first critical paths between the two modules exceeds a first threshold, the two modules are placed adjacent to each other to obtain an updated chip layout; wherein, there are no other modules between the two adjusted modules; and / or, When the number of second critical paths within the module exceeds a second threshold, the IP associated with the module is placed within the module to obtain an updated chip layout.

2. The method according to claim 1, characterized in that, The generation of the clock tree based on the critical path and the chip layout includes: Based on the critical path and the chip layout, the clock source location and multiple first node locations of the clock tree to be generated are determined. Based on the multiple first node positions, multiple second node positions are automatically generated, wherein the level of the second node is lower than the level of the first node; The clock tree is determined based on the clock source location, the multiple first node locations, and the multiple second node locations.

3. The method according to claim 2, characterized in that, The process of determining the clock source location and multiple first node locations of the clock tree to be generated based on the critical path and the chip layout includes: Based on the critical path and the chip layout, the middle position of the chip is determined as the clock source position, and the position where two adjacent modules are connected is determined as the first node position.

4. The method according to claim 1, characterized in that, The generation of the clock tree based on the critical path and the chip layout includes: When there are multiple clocks in the chip, multiple clock trees are generated based on the critical path and the chip layout; wherein, there is no intersection between the multiple clock trees.

5. The method according to claim 1, characterized in that, The clock tree is an H-type clock tree.

6. A clock tree synthesis processing device based on the critical path, characterized in that, The device includes: A critical path determination module is configured to determine the critical path in a chip; wherein the chip includes multiple modules and multiple IPs; The chip layout update module is configured to adjust the position of the module and / or the IP in the chip based on the critical path to obtain an updated chip layout. A clock tree generation module is configured to generate a clock tree based on the critical path and the chip layout, the clock tree including a clock source and multiple nodes; The clock tree synthesis module is configured to perform clock tree synthesis processing based on a preset clock skew, so as to reduce the clock skew of the critical path. The preset clock skew is a pre-set clock skew, which is smaller than the actual clock skew. The determination of the critical path in the chip includes: Static timing analysis is performed on the chip to obtain the timing margin of each path in the chip; The path whose timing margin is less than the third threshold is identified as the critical path; The critical path includes a first critical path between two modules and a second critical path within a module. Adjusting the positions of the modules and / or IPs in the chip based on the critical paths to obtain an updated chip layout includes: When the number of first critical paths between the two modules exceeds a first threshold, the two modules are placed adjacent to each other to obtain an updated chip layout; wherein, there are no other modules between the two adjusted modules; and / or, When the number of second critical paths within the module exceeds a second threshold, the IP associated with the module is placed within the module to obtain an updated chip layout.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 5.

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