Power switch with normally-on transistor

Abstract

A power switch comprises: a common-source common-gate structure having a normally-on transistor connected in series with a normally-off transistor at a common-source common-gate node; a first diode connected between the gate of the normally-on transistor and a first ground, the first ground being common to the common-source common-gate structure and the diode; and a controller comprising: a controller power supply having a power supply output terminal connected to the common-source common-gate node, at which the controller power supply provides a voltage relative to a second ground, the second ground floating relative to the first ground; and a first controller output terminal connected to the gate of the normally-on transistor, at which the controller generates a first voltage relative to the second ground.

Description

[0001] field

[0002] Embodiments of the present invention relate to a power switch including a normally ON transistor, typically a depletion mode transistor controlled to be normally off.

[0003] background

[0004] Almost all types of modern optical and electronic devices, from computers to powertrains, include power switching circuits for generating timing pulses, data packets, and / or delivering power. In order to deliver power to an electric powertrain, such as a powertrain for delivering power to an electric vehicle, a power switch that can be quickly turned on and off to couple and decouple a high voltage power source to a load is required. III-V high electron mobility transistors (HEMTs), such as GaN (gallium nitride) transistors, are particularly advantageous for such applications. III-V HEMTs are wide bandgap transistors characterized by high breakdown voltage, high current density, and low on-state resistance. However, III-V HEMTs are typically normally-on depletion mode transistors. As a result, in power switching circuits using these transistors as switching elements, a controller needs to continuously control the on / off state of the transistor and keep the transistor off as long as the transistor is coupled to a power source and does not need to be turned on to switch power from the power source to the load. Without such control, large current transients may be generated that damage the power switch, the load, and / or the power supply, for example, if the switching circuit is connected to the power supply before connecting to the controller, or if the controller fails during operation.

[0005] Overview

[0006] One aspect of an embodiment of the present disclosure is directed to providing a fast switching power switch including a normally-on transistor, optionally a depletion mode transistor. The power switch is configured to electrically connect and disconnect a load to a load power supply and prevent generation of large current transients that could damage the power switch, the load, and / or the power supply.

[0007] In an embodiment, the power switch includes a cascode structure, in which a normally-on transistor is connected in series with a normally-off (optionally enhanced mode) transistor at a node of the cascode structure. A diode, optionally referred to as a safety diode, is connected between the gate of the normally-on transistor and a first ground, which is common to the cascode structure and the diode. A controller powered by a controller power supply controls the gates of the transistors in depletion mode and enhancement mode. The output of the controller power supply providing a controller voltage relative to the second ground is connected to the cascode node. The second ground may be referred to as a floating ground or a ground floating relative to the first ground, which is not directly connected to the first ground and has a voltage offset relative to the first ground in response to the voltage of the cascode node minus the controller voltage. The absolute value of the controller power supply voltage is greater than the absolute value of the threshold voltage of the normally-on transistor.

[0008] The controller dynamically controls the on / off state of the transistor to turn the power switch on and off and prevent large transient currents, and is configured to keep the normally-on transistor off as long as the enhancement mode transistor is off. The controller controls the gate to make the cascode structure conductive and turn on the power switch by first turning on the enhancement mode transistor and then turning on the normally-on transistor. When the power switch is turned on, the cascode structure provides a conductive path through which current can flow from the load power supply connected to the power switch to provide power to the load connected to the power switch. The controller controls the gate to make the cascode structure non-conductive, and turns off the power switch to prevent current from the load power supply from flowing through the cascode structure, and provides power to the load by turning off the normally-on transistor when the enhancement mode transistor is turned on.

[0009] For a situation also referred to as an abnormal situation, in the abnormal situation, when the enhancement mode transistor is turned off, the power switch is connected to the load power supply, and the controller does not operate to keep the normally-on transistor turned off, the safety diode operates to turn off the normally-on transistor and protect the power switch, the load and / or the load power supply from damage caused by large transient currents.

[0010] Although according to embodiments of the present disclosure, the depletion mode transistor and the enhancement mode transistor may be n-channel or p-channel transistors, for ease of presentation and reference to voltage polarity, in the following discussion, it is assumed by way of example that the depletion mode transistor and the enhancement mode transistor are n-channel transistors. It is assumed that the source of the enhancement mode transistor is connected to a first ground, and the anode of the safety diode is connected to the gate of the normally-on transistor. It is assumed that the first ground voltage is a zero reference voltage, and the load power supply provides a positive voltage relative to the first ground.

[0011] For an abnormal situation, in which the power switch is connected to the load power supply and the controller does not operate to keep the normally-on transistor turned off when the enhancement mode transistor is turned off, the voltage of the drain and source of the normally-on transistor becomes substantially equal to the positive voltage provided by the load power supply relative to the first ground. The safety diode limits the voltage at the gate of the normally-on transistor relative to the first ground to a positive forward voltage of the safety diode, which is less than the positive voltage of the power supply by at least the absolute value of the threshold voltage of the normally-on transistor. The forward voltage of the safety diode thereby generates a gate-to-source voltage for the normally-on transistor that is less than the threshold voltage, and turns off the normally-on transistor to prevent transient currents from damaging the power switch, the load, and / or the power supply.

[0012] When the controller subsequently turns on the enhancement mode transistor, the common source and common gate node, the source of the normally-on transistor, the drain of the enhancement mode transistor, and thus the controller power supply output are electrically connected to the first ground. Therefore, the voltage of the second ground is assumed to be a voltage optionally referred to as a controller operation reference voltage, which is about the controller power supply voltage less than the first ground. As a result, the controller sets the gate voltage of the normally-on transistor to the controller operation reference voltage, and keeps the normally-on transistor turned off and the power switch turned off. The controller operates to conduct the normally-on transistor and turn on the power switch by applying a "turn-on" positive voltage relative to the controller operation reference voltage to the gate of the normally-on transistor. The turn-on voltage has an amplitude that causes the voltage of the normally-on transistor gate to rise to an absolute value greater than the voltage of the first ground minus the normally-on transistor threshold voltage, but less than the voltage of the first ground plus the forward voltage of the safety diode. Therefore, the turn-on voltage is not shunted to the ground by the safety diode, but a gate-to-source voltage for the normally-on transistor is generated, which gate-to-source voltage conducts the normally-on transistor and turns on the power switch.

[0013] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Non-limiting examples of embodiments of the present invention are described below with reference to the attached drawings listed after this paragraph. The same structures, elements, or components that appear in more than one drawing are generally labeled with the same numbers in all drawings in which they appear. The dimensions of the components and features shown in the drawings are selected for convenience and clarity of presentation and are not necessarily shown to scale.

[0016] Figure 1A A schematic diagram of a power switch according to an embodiment of the present disclosure is shown, the power switch comprising a controller, a cascode structure including depletion mode and enhancement mode transistors controlled by the controller, and a safety diode;

[0017] Figure 1B shows a timeline along which a voltage generated by a controller to control a power switch is schematically shown as a function of time according to an embodiment of the present disclosure;

[0018] Figure 2 Schematically shows a similar Figure 1A A power switch of the power switch shown has an additional safety diode to protect the controller power supply from parasitic current;

[0019] Figure 3A The power switch according to an embodiment of the present disclosure is schematically shown. The power switch is similar to Figure 2 The power switch shown, and includes a comparator that disables operation of the controller when a voltage from a controller power supply is insufficient to achieve intended operation of the power switch;

[0020] Figure 3B Schematically shows a similar Figure 3A A power switch of the power switch shown in FIG. 1 , wherein the safety diode is replaced by a normally closed switch; and

[0021] Figure 4A and Figure 4B Different configurations of a control circuit according to embodiments of the present disclosure are schematically shown, the control circuit being operable to control a normally-off enhancement mode transistor of a power switch having a cascode structure.

[0022] Detailed Description

[0023] In the discussion, unless otherwise stated, adjectives such as "substantially" and "approximately" that modify the condition or relational characteristics of one or more features of the embodiments of the present disclosure should be understood to mean that the condition or feature is defined within an acceptable tolerance for the operation of the embodiment for which it is intended to be applied. Wherever a general term in the present disclosure is described by reference to an example instance or a list of example instances, the one or more examples mentioned are by way of non-limiting example instances of the general term, and the general term is not intended to be limited to the one or more specific example instances mentioned. The phrase "in an embodiment", whether or not associated with a permission, such as "may", "optionally" or "as an example", is used to introduce an example for consideration, but is not necessarily a desired configuration of a possible embodiment of the present disclosure. Unless otherwise stated, the word "or" in the specification and claims is considered to be an inclusive "or", not an exclusive "or", and represents any combination of at least one or more of the items it combines.

[0024] Figure 1AA power switch 20 according to an embodiment of the present disclosure is schematically shown. The power switch 20 comprises: a cascode structure 30 having a normally-on (optionally depletion mode) transistor 31 connected in series with a normally-off transistor 32; a controller 60 controlling the transistor; and a safety diode 50 operating to turn off the normally-on transistor in the absence of proper control by the controller.

[0025] The cascode structure 30 is connected between terminals 41 and 42, the load and the load power supply are connected to the terminals 41 and 42, and the power switch controls the power transfer from the power supply to the load for the load and the load power supply. Optionally, the terminal 42 is connected to the ground G1, and for the convenience of representation, it is assumed that the ground G1 has a voltage equal to zero. The drain D31 of the normally-on transistor 31 is connected to the terminal 41, and the source S32 of the enhancement mode transistor 32 is connected to the terminal 42, and thus connected to the ground G1. The drain D32 of the enhancement transistor 32 is connected to the source S31 of the normally-on transistor 31 at the cascode node N33. Optionally, as Figure 1A As shown, transistors 31 and 32 are n-channel transistors, each having a threshold voltage V31. th and V32 th , and the normally-off transistor 32 is an enhancement mode transistor. The safety diode 50 is connected between the gate G31 of the normally-on transistor 31 and the ground G1, and the anode of the safety diode is connected to the gate. Figure 1A In the embodiment, a load schematically represented by a resistor 40 and a load power supply LPS are connected in series to power switch terminals 41 and 42, and the load power supply LPS provides a positive voltage V relative to the ground G1. LPS To supply power to the load.

[0026] The voltage signal generated by the controller 60 is referenced to a ground G2 that is floating relative to the ground G1. The controller includes a controller power supply CPS that generates a positive voltage V at an output 61 of the power supply relative to G2. CPS , the positive voltage V CPS Greater than the threshold voltage V31 th The absolute value and optional threshold voltage V32 th The output terminal 61 is electrically connected to the common source and common gate node N33 and a DC isolator or isolated gate driver 62, optionally generally referred to as a DC isolator. The DC isolator 62 connects the controller power supply CPS to the gate G32 of the enhancement transistor 32. When the controller power supply CPS provides a voltage V to the DC isolator 62 CPSWhen the DC isolator generates or is controllable to generate a DC voltage at the gate G32 relative to the ground G1. The DC voltage provided by the DC isolator at the gate G32 generates a gate-to-source voltage V32 for the enhancement mode transistor 32. GS , the gate to source voltage V32 GS Greater than the threshold voltage V32 of the enhancement mode transistor th , and turns on the enhancement mode transistor to connect the cascode node N33 to the ground G1.

[0027] According to an embodiment of the present disclosure, the controller 60 includes an isolated power amplifier operating as a gate driver 70, which receives power from the controller power supply CPS and controls the on / off state of the normally-on transistor 31. The gate driver has an input terminal 72 and an output terminal 71 connected to the gate G31 of the normally-on transistor 31, and the gate driver receives a switch control signal from a gate driver controller (not shown) through the input terminal 72. When the voltage V CPS When powered, the switch control signal controls the gate driver to generate an output voltage V relative to ground G2 at the output terminal 71. 71 Voltage V 71 The voltage of the control gate G31 and the gate-to-source voltage V31 for the normally-on transistor 31 GS , the gate to source voltage V31 GS Controls the on / off state of the normally-on transistor 31. As described below, as long as the controller power supply CPS provides power to the DC isolator 62 to keep the enhancement mode transistor 32 turned on, V at the output terminal 71 71 And thus the voltage V31 GS The normally-on transistor 31 is controlled to be turned off or on, thereby controlling the power switch 20 to be turned off or on.

[0028] Since the output terminal 61 of the controller power supply CPS is connected to the common source and common gate node N33, and the ground G2 is floating relative to the ground G1, the voltage V 71 Generates gate-to-source voltage V31 for normally-on transistor 31 GS =(V 71- V CPS) In the absence of a switch control signal from the gate driver, the controller voltage V 71 is zero with respect to G2, and the gate-to-source voltage V31 GS Equal to -V CPS As a result, because V CPS Greater than the absolute value of the threshold voltage V31 of the normally-on transistor 31 th |, so V31 GS Smaller than V31th , and operates to turn off the normally-on transistor and keep the normally-on transistor off.

[0029] On the other hand, according to an embodiment of the present disclosure, when triggered by an appropriate switch control signal at input terminal 72, gate driver 70 causes voltage V 71 Increase relative to G2 to generate a value greater than V31 th The gate-to-source voltage V31 GS =(V 71 -V CPS ), so the gate-to-source voltage V31 GS The normally-on transistor 31 is turned on to make the cascode structure 30 conductive and turn on the power switch 20 .

[0030] As an example, Figure 1A The schematic diagram shows that the gate driver 70 receives a switch control signal, which is a sequence of voltage pulses 75, which causes the gate driver 70 to generate a corresponding output sequence, also called "on" pulses 76. The voltage pulses have a positive amplitude V relative to G2. 76 , and generates a gate-to-source voltage pulse V31 GS =(V 76 -V CPS ). According to an embodiment, V 76 The amplitude makes (V 76 -V CPS )≥V31 th , and each pulse 76 turns on the normally-on transistor 31 for a period of time that is substantially equal to V 76 ≥(V31 th +V CPS Since the enhancement mode transistor 32 is on, the switch control pulse 75 operates to turn on and off the power switch 20 and supply power from the load power supply LPS to the load 40 at a repetition frequency and duty cycle determined by the frequency and pulse width of the switch control signal pulse.

[0031] Note that for the power switch 20, the voltage pulse V 76 Reference ground G2, and with respect to G2 having a voltage equal to V CPS Relative to ground G1, ground G2 establishes a voltage equal to (V N33 -V CPS ) operating reference voltage, where V N33 is the voltage at the common source and common gate node N33. Because the enhancement transistor 32 is turned on, the common source and common gate node N33 is electrically connected to the ground G1 via the turned-on enhancement transistor 32. Therefore, V N33The voltage at is approximately equal to the voltage of G1 plus the voltage drop V32 across the enhancement transistor 32. ds , and the operating reference voltage of ground G2 is approximately equal to the voltage (G1+V32 ds )-V CPS In an embodiment, the safety diode 50 is configured to have a voltage drop greater than the expected voltage drop V32 when the power switch 20 is turned on. ds The forward voltage V f Therefore, the voltage pulse 76 does not exceed the forward voltage V of the safety diode 50 relative to the ground G1 to which the safety diode 50 is directly connected. f As a result, the voltage pulse is not shunted to the ground G1 by the safety diode, and the voltage V31 that turns on the transistor 31 and turns on the power switch 20 is prevented from being generated. GS .

[0032] Figure 1B 1 shows a graph 100 schematically illustrating the time development and relative timing of voltages associated with the operation of the power switch 20 along time lines 101, 102, 103 and 104 according to an embodiment of the present disclosure. Along time line 101, a voltage V generated by the controller power supply CPS at the output terminal 61 of the controller relative to ground G2 is shown. CPS Timeline 102 schematically illustrates the time period when the controller power supply 60 provides a voltage V to the DC isolator. CPS When the DC isolator 62 ( Figure 1A ) The gate voltage V32 applied to the gate G32 GS , the gate voltage V32 GS The timeline 103 schematically shows the time when the controller power supply provides a voltage V CPS The switch control pulse 75 controls the gate driver 70 to generate a gate driver output pulse 76 ( Figure 1A ), the gate driver output pulse 76 conducts the normally-on transistor 31 and turns on the power switch 20. Time line 104 schematically shows the voltage of the output pulse 76 and the threshold voltage V31 of the normally-on transistor 31 relative to the ground G2 and the ground G1. th As described above, when the controller power supply CPS is turned on and provides the voltage V to the power controller 60, CPS When the voltage of ground G2 is lower than that of ground G1 by a voltage V CPS , the source S31 is electrically connected to the ground G1 through the turned-on enhancement mode transistor 32. When the voltage of the gate driver pulse 76 rises above G2 to a value greater than (G1-|V31 th |) voltage (assuming V31 this negative), the normally-on transistor 31 is turned on and the power switch 20 is turned on. The gate driver pulse 76 rises to a value higher than (G1-|V31 th |) and turns on the power switch 20 is indicated by the pulse area lacking hatching.

[0033] However, as long as the controller 60 is connected to the cascode structure 30 and appropriately controls the transistors 31 and 32 to keep the normally-on transistor 31 off and the enhancement mode transistor 32 on when the power switch 20 is intended to be turned off, the controller 60 operates as described above and prevents the occurrence of potentially large and destructive transient currents. However, if the load power supply LPS is connected to the power switch 20, the normally-on transistor 31 is turned on and the enhancement mode transistor is turned off, then a large and destructive transient current may be generated, for example, due to the controller 60 malfunctioning or not being properly connected to the cascode structure 30. In this abnormal situation, the voltage of the drain D31, gate G31 and source S31 of the normally-on transistor 31 is toward the voltage V of the load power supply. LPS The voltage at the gate G31 rises and operates to conduct the normally-on transistor and enables the generation of a destructive transient current. According to an embodiment of the present disclosure, the safety diode 50 operates to prevent the normally-on transistor from conducting. When the voltage at the gate G31 rises to a voltage exceeding the forward voltage threshold V of the safety diode 50, the voltage at the gate G31 rises and operates to conduct the normally-on transistor and enables the generation of a destructive transient current. f When the diode is turned on, the voltage of the gate G31 relative to the ground G1 is limited to the forward diode voltage threshold, and a negative gate-to-source voltage V31 is generated. GS , the negative gate-to-source voltage V31 GS Normally-on transistor 31 is turned off and the generation and / or persistence of large transients that could damage power switch 20 and circuits connected to the power switch are limited.

[0034] Figure 2 A power switch 220 according to an embodiment of the present disclosure is schematically illustrated. The power switch 220 is similar to the power switch 20, but includes a controller 260 with an additional safety diode 250 that operates to block a parasitic current path from the cascode node N33 from flowing to the controller.

[0035] Figure 3A A power switch 320 according to an embodiment of the present disclosure is schematically shown. The power switch 320 is similar to the power switch 220, but includes a controller 360 having a comparator 362, which is optionally a Schmidt trigger, having an input 364 connected to the output 61 of the controller power supply CPS and an output 366 connected to the DC isolator 62 and the gate driver 70. According to an embodiment, if the controller power supply CPS does not provide an absolute value greater than the threshold voltage |V31 of the normally-on transistor 31th |The voltage V CPS , or does not provide sufficient voltage to enable the controller to operate normally, the comparator 362 inhibits the operation of the DC isolator 62 and the gate driver 70. If the power supply CPS does provide sufficient voltage, the comparator 362 generates an enable signal at the output 366, which enables the operation of the DC isolator 62 and the gate driver 70. As described above, preventing the DC isolator 62 and the gate driver 70 from operating causes the safety diode 50 to turn off the normally-on transistor 31 and turn off the power switch 320.

[0036] Although in the above description, the power switch is described as including a safety diode 50 that operates to turn off the normally-on transistor and protect the power switch from damage caused by large transient currents, the practice of the disclosed embodiments is not limited to the safety diode. For example, a normally-on switch that is turned off when the normally-off transistor 32 is turned on can be used to protect the power switch from damaging transients. Figure 3B The power switch 321 according to the embodiment is schematically shown. The power switch 321 is similar to Figure 3A The power switch 320 shown in FIG. 1 is shown in FIG. 1 , but with a normally-on switch 150 instead of a diode 50 ( Figure 3A Normally-on switch 150 is optionally enabled by an enable signal provided by comparator 362 at output 366 or by a voltage (eg, V32) generated by gate driver 62. GS ) is turned off.

[0037] Figure 4A Schematically illustrates details of a circuit configuration 62-1 for a DC isolator 62 that connects a controller power supply CPS to an enhancement mode transistor 32 to generate a DC gate to source voltage V32 that turns on the enhancement mode transistor according to an embodiment of the present disclosure. GS .

[0038] Circuit configuration 62-1 optionally includes an inverting operational amplifier 500 coupled to a resistor R1 and a capacitor C1, which are connected in series to ground G1. Rails 501 and 502 of amplifier 500 are connected to output terminal 61 of controller power supply CPS and ground G2, respectively. Resistor R1 is connected between output terminal 505 and input terminal 506 of inverting amplifier 500. As a result, in response to a DC voltage V provided by controller power supply CPS, CPS , the inverting amplifier 500 generates an oscillating voltage and current. The oscillating current is rectified by the resistor R2, the capacitors C2 and C3, and the diodes D1 and D2 to provide a gate-to-source DC voltage V32 that turns on the enhancement mode transistor 32 GSCapacitors C2 and C3 isolate the controller power supply CPS from the enhancement transistor 32DC. Resistor R3 is a bleeder resistor.

[0039] Figure 4B Schematically illustrates details of another circuit configuration 62-2 for a DC isolator 62 that connects a controller power supply CPS to an enhancement mode transistor 32 to generate a DC gate-to-source voltage V32 that turns on the enhancement mode transistor according to an embodiment of the present disclosure. GS .

[0040] Circuit configuration 62-2 is similar to circuit configuration 62-1, but in configuration 62-2, the input is configured to receive a sequence of input pulses 601 from an external driver (not shown) at input terminal 506, rather than generating an oscillating current by coupling output terminal 505 of inverting operational amplifier 500 to input terminal 506 of the amplifier, in accordance with an embodiment of the present disclosure. In response to input pulse 601, amplifier 500 generates a sequence of output pulses 602 that are rectified to provide a gate-to-source DC voltage V32 that turns on enhancement mode transistor 32. GS .

[0041] In the description and claims of this application, each of the verbs "comprise," "include," and "have" and their variations is used to indicate an object or objects of the verb that is not necessarily a complete list of components, elements or parts of the subject or subjects of the verb.

[0042] The description of the embodiments of the present invention in this application is provided by way of example and is not intended to limit the scope of the present invention. The described embodiments include different features, not all of which are required in all embodiments of the present invention. Some embodiments utilize only some features or possible combinations of features. Those skilled in the art will appreciate variations of the described embodiments of the present invention and embodiments of the present invention that include different combinations of the features mentioned in the described embodiments. The scope of the present invention is limited only by the claims.

Claims

1. A power switch (20), include: A cascode structure (30) having a normally-on transistor (31) connected in series with a normally-off transistor (32) at a cascode node (33); A first diode (50) connected between the gate (G31) of the normally-on transistor and a first ground (G 1 ), the first ground is shared by the common-source common-gate structure and the first diode; as well as A controller, the controller comprising: a gate driver (70) having a gate driver output (71) connected to the gate of the normally-on transistor; a controller power supply (CPS) having a positive output terminal and a negative output terminal for providing a positive rail voltage and a negative rail voltage to the gate driver, respectively, and wherein the positive output terminal of the controller power supply is connected to the common source and common gate node, and the negative output terminal of the controller power supply is connected to a second ground (G 2 ), the second ground floats relative to the first ground; and a DC isolator having a positive isolator input and a negative isolator input connected to the positive output and negative output of the controller power supply, respectively, and having a first isolator output connected to the gate of the normally-off transistor and a second isolator output connected to the first ground, and wherein, when the controller power supply is turned on, the DC isolator generates a DC voltage at a first voltage output, the DC voltage turning on the normally-off transistor and keeping the normally-off transistor turned on. 2 . The power switch of claim 1 , comprising a second diode having an anode connected to the positive output terminal of the controller power supply and a cathode connected to the cascode node.

3. The power switch according to claim 1 or claim 2, in, DC isolation is capacitive.

4. The power switch according to claim 1 or claim 2, in, When the normally-off transistor is turned on and the maximum output pulse of the gate driver is less than the voltage between the positive output terminal and the negative output terminal of the controller power supply, the forward voltage V f is greater than the drain-source voltage V across the normally-off transistor ds drop.

5. The power switch according to claim 3, in, When the normally-off transistor is turned on and the maximum output pulse of the gate driver is less than the voltage between the positive output terminal and the negative output terminal of the controller power supply, the forward voltage V f is greater than the drain-source voltage V across the normally-off transistor ds drop.

6. A power switch, include: a cascode structure having a normally-on transistor connected in series with a normally-off transistor at a cascode node; a normally-on switch, the normally-on switch being connected between a gate of the normally-on transistor and a first ground, wherein the first ground is shared by the cascode structure and the normally-on switch; as well as A controller, the controller comprising: a gate driver having a gate driver output connected to a gate of the normally-on transistor; a controller power supply having a positive output terminal and a negative output terminal for providing a positive rail voltage and a negative rail voltage to the gate driver, respectively, and wherein the positive output terminal of the controller power supply is connected to the cascode node and the negative output terminal of the controller power supply is connected to a second ground floating relative to the first ground; and A DC isolator having: a positive isolator input terminal and a negative isolator input terminal respectively connected to the positive output terminal and the negative output terminal of the controller power supply, and a first isolator output terminal connected to the gate of the normally-off transistor and a second isolator output terminal connected to the first ground, and wherein when the controller power supply is turned on, the DC isolator generates a DC voltage at the first voltage output terminal, the DC voltage turns on the normally-off transistor, and keeps the normally-off transistor turned on.

7. The power switch of claim 6 including a diode connecting the output of the controller power supply to the cascode node.

8. The power switch according to claim 6 or claim 7, in, When the controller power supply is turned on, the controller simultaneously generates a signal to turn off the normally-on switch.

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