output detection circuit
By combining a positive and negative mirror FET with an operational amplifier in the current detection circuit, the problems of power loss and low efficiency of negative voltage power supply in load current detection are solved, and efficient detection of current in both positive and negative directions is achieved.
Patent Information
- Application Number
- CN202211607770.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-14
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2042-12-14
AI Technical Summary
In load current detection, existing technologies suffer from power loss and low efficiency of negative voltage power supplies, especially when the current direction is both positive and negative, making it difficult to detect the current efficiently.
A current detection circuit using a positive and negative mirror FET combined with an operational amplifier is used to detect the positive and negative currents respectively, and the feedback voltage of the operational amplifier is converted into current to achieve current detection.
It enables efficient detection of positive and negative currents without the need for a negative power supply, reducing power loss and improving the efficiency and accuracy of current detection.
Smart Images
Figure CN118191391B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a current detection circuit for an output FET (Field Effect Transistor) that outputs current in both positive and negative directions. BACKGROUND
[0002] Previously, in the case of PWM (Pulse Width Modulation) control of a load, the driving current to the load is detected in order to perform current control of the load. A current detection resistor is provided in parallel with the load, and the voltage drop caused by the current detection resistor is measured, whereby current detection is performed. However, in this case, the power consumption caused by the detection resistor becomes a loss of power.
[0003] It is also known to use the on-resistance of an output transistor that controls the power supply to a load to detect current. By this means, the unnecessary loss of power can be eliminated. Here, since the on-resistance of the output transistor has a large temperature dependence, another reference transistor is used to compensate for the temperature dependence.
[0004] Here, in the case where the current flowing to the load is not in one direction but in both positive and negative directions, a power supply of negative voltage is required in order to detect the current in the negative direction. However, a power supply of negative voltage is not provided in a general circuit, and therefore it is inefficient to provide a power supply of negative voltage in order to perform current detection. SUMMARY
[0005] The output current detection circuit of the present application is an output current detection circuit for an output FET that outputs current in both positive and negative directions, and comprises:
[0006] a positive mirror FET that flows a positive mirror current proportional to the current in the positive direction among the positive and negative direction currents of the output FET;
[0007] a first operational amplifier that receives a constant voltage at one end and receives the upstream side voltage in the positive mirror current of the positive mirror FET at the other end, and outputs a voltage corresponding to the upstream side voltage in the positive mirror current of the positive mirror FET by converting the output voltage to a current and feeding it back to the other end;
[0008] a negative mirror FET that flows a negative mirror current proportional to the current in the negative direction among the positive and negative direction currents of the output FET; and
[0009] a second operational amplifier that receives a constant voltage at one end and receives the upstream side voltage in the negative mirror current of the negative mirror FET at the other end, and outputs a voltage corresponding to the upstream side voltage in the negative mirror current of the negative mirror FET by converting the output voltage to a current and feeding it back to the other end.
[0010] The detection value is outputted in accordance with an output current obtained by adding a positive output current corresponding to the output of the first operational amplifier and a negative output current corresponding to the output of the second operational amplifier.
[0011] The output current detection circuit according to the present application can detect the output current in both positive and negative directions without using a negative power supply. BRIEF DESCRIPTION OF DRAWINGS
[0012] Figure 1 is a circuit diagram showing an output detection circuit of an embodiment.
[0013] Figure 2 is a graph showing an output current io of a current output terminal Iout of an output detection circuit from an embodiment.
[0014] Figure 3 is a circuit diagram showing a variation of the configuration of the output detection circuit of the embodiment.
[0015] Figure 4 is a circuit diagram showing a configuration for improving linearity around a connection point of the currents ip0 and in0 of the output detection circuit of the embodiment.
[0016] Figure 5 is a graph showing a state around 0 points of the currents ip0 and in0. DETAILED DESCRIPTION
[0017] Hereinafter, an embodiment of the present application will be described with reference to the accompanying drawings. Note that the present application is not limited to the following embodiment, and configurations in which a plurality of examples are selectively combined are also included in the present application.
[0018] "Overall Configuration"
[0019] Figure 1 is a graph showing a circuit of an output detection circuit of an embodiment. Here, in the circuit of the embodiment, a transistor and a MOSFET (metal-oxide-semiconductor field-effect transistor) are used.
[0020] The drain of the N-type transistor M1 is connected to the input terminal IN, the source is connected to the ground gnd, and a signal LS_gate is supplied to the gate. A load to be driven is connected to the input terminal IN, and a current iin flowing through the load is supplied to the input terminal IN. Therefore, the current iin flows from the input terminal IN to the ground gnd via the transistor M1. The transistor M1 is referred to as an output FET.
[0021] This current iin is an output current of the detection object, and changes from a positive direction current to a negative direction current. Further, the resistance of the transistor Ml when turned on, that is, the on-resistance, is denoted by Ron. Therefore, the voltage vin of the input terminal IN is denoted by vin = Ron*iin.
[0022] The gate of the N-type transistor M2 is commonly connected to the gate of the transistor Ml. The drain of the transistor M2 is connected to the input terminal IN. The current source gm3 is connected to the source of the transistor M2. This current source gm3 flows a current to the input terminal IN. Therefore, the transistor M2 flows a current from the source to the drain. The current source gm3 can be constituted by a transistor which flows a current from a power source. The transistor M2 flows a mirror current corresponding to the negative direction current of the transistor Ml, and this transistor M2 is called a negative mirror FET.
[0023] The connection point of the source of the transistor M2 and the current source gm3 is connected to the positive input terminal of the operational amplifier op2. That is, the upstream side voltage of the transistor M2 is supplied to the positive input terminal of the operational amplifier op2. The negative input terminal of this operational amplifier op2 is connected to the ground. That is, the source side voltage of the transistor Ml is supplied to the negative input terminal of the operational amplifier op2. The output terminal of the operational amplifier op2 is connected to the control terminal of the current source gm3. The output voltage of the operational amplifier op2 is converted to a current by the current source gm3. The operational amplifier op2 is called a second operational amplifier.
[0024] The operational amplifier op2 operates in such a manner that the source of the transistor M2 becomes the ground gnd. Therefore, the transistor M2 flows a current of the same current density as the transistor Ml (a current corresponding to the area ratio of the transistor Ml ). If the on-resistance of the transistor M2 is set to r1, and the current flowing through M2 is set to ino, then the voltage vin of the input terminal IN is denoted by vin = r1*ino.
[0025] The gate of the N-type transistor M3 is commonly connected to the gate of the transistor Ml. The current source gm1 is connected to the drain of the transistor M3. The source of the transistor M3 is connected to the ground gnd. The current source gm1 flows a current to the ground gnd. Therefore, the transistor M3 flows a current from the drain to the source. The current source gm1 can be constituted by a transistor which flows a current from a power source. The transistor M3 flows a mirror current corresponding to the positive direction current of the transistor Ml, and this transistor M3 is called a positive mirror FET.
[0026] The drain of the transistor M3 is connected to the positive input terminal of the operational amplifier ol. That is, the upstream side voltage of the transistor M3 is supplied to the positive input terminal of the operational amplifier ol. The negative input terminal of the operational amplifier ol is connected to the input terminal IN via the N-type transistor M4. That is, the drain side voltage of the transistor Ml is supplied to the negative input terminal of the operational amplifier ol. Further, the gate of the transistor M4 is commonly connected to the gates of the transistors Ml, M2, and M3. The operational amplifier ol is referred to as a first operational amplifier.
[0027] Further, the output terminal of the operational amplifier ol is connected to the control terminal of the current source gm 1.
[0028] Here, the current source gm 1 flows a current to the ground gnd. In the case where the current iin of the input terminal IN flows to the load side from the input terminal IN in the negative direction, no current flows through the transistor M3. As with the gate of the transistor Ml, the gate of the transistor M4 is connected to LS_gate, and is turned on when the transistor Ml is turned on, and is turned off when the transistor Ml is turned off. In the case where the operational amplifier ol is an ideal circuit, the transistor M4 is not needed. However, in the case where the transistor Ml is turned off, the voltage vin can be high, and in this case, the transistor M4 is turned off, thereby preventing the input of the operational amplifier ol from being high, and preventing the operational amplifier ol from being destroyed.
[0029] In the case where the current iin of the input terminal IN flows to the load side from the input terminal IN in the positive direction, the operational amplifier ol operates in such a manner that the positive input terminal has the same voltage as the input terminal IN. A current having the same current density as the transistor Ml (a current corresponding to the area ratio of the transistor Ml) flows through the transistor M3.
[0030] If the on resistance of the transistor M3 is set to r 1, and the current flowing through M3 is set to ip0, the voltage of the positive input terminal of the operational amplifier ol is expressed as r 1 * ip0, and the operational amplifier ol operates in such a manner that the voltage vin of the input terminal IN becomes r 1 * ip0.
[0031] Thus, a current proportional to the negative current iin flowing through the transistor Ml flows through the transistor M2, and a current proportional to the positive current iin flowing through the transistor Ml flows through the transistor M3.
[0032] The control terminal of the current source gm 3 and the control terminal of the current source gm 4 are connected to the output terminal of the operational amplifier ol. The current source gm 4 flows a current having the same magnitude as the current source gm 3 but in the opposite direction. For example, the current source gm 4 is formed of the same transistor as the current source gm 3, the current source gm 4 is caused to generate a current having the same magnitude as the current source gm 3, and an inverter circuit is used to reverse the direction of the generated current. The inverter circuit can be various circuits.
[0033] The control terminal of the current source gm1 and the control terminal of the current source gm2 are connected to the output terminal of the operational amplifier op1. The current source gm2 flows the same current as the current source gm1. For example, the current source gm1 and the current source gm2 can be constituted by a current mirror. The output voltage of the operational amplifier op2 is converted into a current by the current sources gm1 and gm2.
[0034] The connection point of the current source gm2 and the current source gm4 becomes the current output terminal iout. As described above, the current source gm2 flows the positive output current ip0 and the current source gm4 flows the negative output current ino, and therefore the current ip0 flows out from the current output terminal iout and the current ino flows into the current output terminal.
[0035] The negative input terminal of the operational amplifier op3 is connected to the current output terminal iout. The reference voltage vref0 is supplied to the positive input terminal of the operational amplifier op3, and the output terminal of the operational amplifier op3 is connected to the output terminal sout and fed back to the negative input terminal via the resistor Rl. Therefore, the output terminal sout becomes a voltage which fluctuates up and down by the voltage of io*Rl with the reference voltage vref0 as a reference. Therefore, an output proportional to the current iin in both positive and negative directions is obtained as a detection value. The operational amplifier op3 is called a third operational amplifier.
[0036] Figure 2 is a graph showing the output current io from the current output terminal iout. In this way, the current ip0 becomes 0 when the current iin is negative and becomes larger in correspondence with the current iin when the current iin is positive. The current ino becomes larger in the negative direction as the negative current becomes larger when the current iin is negative and becomes 0 when the current iin is positive. Therefore, the output current io outputs the current ino when the current iin is negative and outputs the current ip0 when the current iin is positive. Therefore, the output current io changes in correspondence with the current iin when the current iin is positive and negative.
[0037] "Constitution of a variation example"
[0038] Figure 3 is a circuit diagram showing the constitution of a variation example, and the operational amplifier op3 in Figure 1 is omitted, and the output terminal sout is directly connected to the current output terminal iout and connected to the reference voltage source of the output reference voltage vref0 via the resistor Rl. By making the resistor Rl a relatively large resistor, the current flowing therethrough becomes small, and the center voltage of the output terminal sout can be set to the reference voltage vref0. That is, the output terminal sout outputs the current io with the reference voltage vref0 as a center.
[0039] Figure 4 shows a constitution for improving the linearity in the vicinity of the connection point of the currents ip0 and ino.Figure 5 is a graph showing the state around 0 point of the currents ip0, in0.
[0040] In the above example, the current source gm2 is constituted by the transistor Mp3, and the current source gm4 is constituted by the transistor Mn4. In this case, in the graph, a leakage current indicated by IMp3, IMn4 is generated at the transistors Mp3, Mn4. That is, the transistors cannot be completely turned off, and even if turned off, a slight current flows.
[0041] Figure 4 In the example of FIG. 8, the transistor Mp4 is disposed between the transistor Mp3 and the current output terminal iout, and the transistor Mn3 is disposed between the transistor Mn4 and the current output terminal iout.
[0042] Further, the help circuit HP is interposed between the operational amplifier op1 and the operational amplifier op2 and the current sources gm2, gm4.
[0043] The gate of the P-type transistor Mp1 is connected to the gate of the P-type transistor Mp3. The source of the transistor Mp1 can be connected to the same power supply (high voltage) as the transistor Mp3. The drain of the transistor Mp1 is connected to the source of the P-type transistor Mp2, and the drain of the transistor Mp2 is connected to the connection point of the transistors Mn3 and Mn4.
[0044] The gate of the N-type transistor Mn2 is connected to the gate of the N-type transistor Mn4. The source of the transistor Mn2 can be connected to the same power supply (low voltage) as the transistor Mn4. The drain of the transistor Mn2 is connected to the source of the transistor Mn1, and the drain of the transistor Mn2 is connected to the connection point of the transistors Mp3 and Mp4.
[0045] In this configuration, when the current iin is positive, the amount of the leakage current of the transistor Mn4 is supplied via the transistors Mp1, Mp2. On the other hand, when the current iin is negative, the leakage current of the transistor Mp3 leaks via the transistors Mn1, Mn2.
[0046] Further, the gates of the transistors Mp2 and Mp4 are connected to the power supply vbp and are turned on when the current iin is positive. The gates of the transistors Mn1 and Mn3 are connected to the power supply vbn and are turned on when the current iin is negative.
[0047] By the circuit of FIG. 7, the leakage currents of the transistors Mp3, Mn4 are compensated for to improve the linearity of the output current. Figure 4 By the circuit of FIG. 7, the leakage currents of the transistors Mp3, Mn4 are compensated for to improve the linearity of the output current.
Claims
1. An output current detection circuit, for an output FET that outputs current in the positive and negative directions, comprising: A positive mirror FET, wherein a positive mirror current flows in proportion to the positive current of the positive and negative currents of the output FET; The first operational amplifier is electrically connected to the drain of the output FET at the negative input terminal and receives the upstream voltage in the positive mirror current of the positive mirror FET at the positive input terminal. By converting the output voltage into current and feeding it back to the positive input terminal, it outputs a voltage corresponding to the upstream voltage in the positive mirror current of the positive mirror FET. A negative mirror FET, which has a negative mirror current that is proportional to the negative current of the positive and negative currents of the output FET; and The second operational amplifier is grounded at its negative input terminal and electrically connected to the source of the output FET. It receives the upstream voltage in the negative mirror current of the negative mirror FET at its positive input terminal. By converting the output voltage into current and feeding it back to the positive input terminal, it outputs a voltage corresponding to the upstream voltage in the negative mirror current of the negative mirror FET. A first FET, the gate of which is commonly connected to the gate of the output FET, the gate of the positive mirror FET, and the gate of the negative mirror FET, wherein the negative input terminal of the first operational amplifier is electrically connected to the drain of the output FET via the first FET, and The detection value is output based on the output current obtained by adding the positive output current corresponding to the output of the first operational amplifier and the negative output current corresponding to the output of the second operational amplifier.
2. The output current detection circuit according to claim 1, comprising a third operational amplifier that converts the output current into a voltage centered on a reference voltage, and outputting a detection value from the third operational amplifier.
Citation Information
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