An LCD screen circuit and a control circuit of a mini PC

Abstract

An embodiment of the present application discloses an LCD screen circuit and a control circuit of a mini PC, which are used to switch the theme images of the LCD screen. The embodiment of the present application includes: a control module, a receiving module, a storage module, and a display module; the receiving module is used to receive an external input signal; the storage module is used to store a plurality of theme image data; the display module is used to display target theme image data; the control module is respectively connected to the receiving module, the storage module, and the display module, and is used to control the storage module to send the target theme image data among the plurality of theme image data to the control module according to the external input signal sent by the receiving module, and control the display module to display a theme image corresponding to the target theme image data according to the target theme image data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of LCD screens, and in particular, to an LCD screen circuit and a control circuit of a mini PC. Background Art

[0002] With the continuous development of technology, the production and living standards of people have been continuously improved. Among them, the emergence of mini PC devices has brought great convenience to people. In order to meet the growing needs of people, the functions of mini PCs have been continuously increased, making the application of the LCD screen function of mini PCs more and more extensive.

[0003] In the existing solutions, the LCD screen of the mini PC can only view relevant parameters, ignoring people's pursuit of the beauty of the LCD screen, and unable to meet people's need to switch to the theme image that suits their preferences, which brings certain inconvenience to users. Summary of the Invention

[0004] The embodiments of the present application provide an LCD screen circuit and a control circuit of a mini PC for switching the theme image of the LCD screen.

[0005] In the first aspect of the embodiments of the present application, an LCD screen circuit is provided, including: a control module, a receiving module, a storage module, and a display module;

[0006] The receiving module is configured to receive an external input signal;

[0007] The storage module is configured to store a plurality of theme image data;

[0008] The display module is configured to display the target theme image data;

[0009] The control module is respectively connected to the receiving module, the storage module, and the display module, and is configured to control the storage module to send the target theme image data among the plurality of theme image data to the control module according to the external input signal sent by the receiving module, and control the display module to display the theme image corresponding to the target theme image data according to the target theme image data.

[0010] Optionally, the control module includes: a first chip, a first crystal oscillator, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor;

[0011] The first pin to the tenth pin of the first chip are connected to the display module, the eleventh pin and the twelfth pin of the first chip are connected to the receiving module, the thirteenth pin of the first chip is connected to the second end of the second capacitor, the first end of the second capacitor is grounded, one end of the third capacitor is connected to the fourteenth pin of the first chip and the V3P3A terminal, the other end of the third capacitor is grounded, the fifteenth pin of the first chip is grounded, the sixteenth pin of the first chip is respectively connected to the fourth test terminal, one end of the fourth resistor and one end of the seventh capacitor, the other end of the fourth resistor is connected to the V3P3A terminal, the other end of the seventh capacitor is grounded, the seventeenth pin of the first chip is respectively connected to one end of the second resistor, one end of the third resistor and one end of the fourth capacitor, the other end of the second resistor is connected to the VCC_5V terminal, the other end of the third resistor is connected to the V3P3A terminal, the other end of the fourth capacitor is grounded, the eighteenth pin of the first chip is respectively connected to the first end of the first crystal oscillator and one end of the fifth capacitor, the nineteenth pin of the first chip is respectively connected to the second end of the first crystal oscillator and one end of the sixth capacitor, the other ends of the fifth capacitor and the sixth capacitor are both grounded, and the twenty-fourth pin of the first chip is connected to the display module;

[0012] The twenty-fifth pin, the twenty-seventh pin, the twenty-eighth pin, the thirty-first pin, the thirty-second pin, the thirty-third pin and the thirty-fourth pin of the first chip are all connected to the display module, the twenty-sixth pin of the first chip is connected to one end of the first resistor, the other end of the first resistor is connected to the V3P3A terminal, the twenty-ninth pin of the first chip is connected to the third test terminal, the thirtieth pin of the first chip is connected to the second test terminal, the thirty-fifth pin of the first chip is connected to the V3P3A terminal, the thirty-sixth pin of the first chip is grounded, the thirty-seventh pin to the forty-second pin of the first chip are connected to the storage module, the forty-seventh pin of the first chip is respectively connected to the second end of the first capacitor and the V3P3A terminal, the forty-eighth pin of the first chip is respectively grounded and the first end of the first capacitor, the first test terminal is connected to the V3P3A terminal, and the fifth test terminal is grounded.

[0013] Optionally, the receiving module includes: a first connector, a second chip, a fifth resistor, a sixth resistor, a seventh resistor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor;

[0014] The first pins of the first connector are respectively connected to the VCC_5V terminal, one end of the eighth capacitor, and the VIN pin of the second chip. The other end of the eighth capacitor is grounded. One end of the fifth resistor is connected to the second pin of the first connector, and the other end is respectively connected to one end of the eleventh capacitor and the eleventh pin of the first chip. One end of the sixth resistor is connected to the third pin of the first connector, and the other end is respectively connected to one end of the tenth capacitor and the twelfth pin of the first chip. The other ends of the tenth capacitor and the eleventh capacitor are grounded. One end of the seventh resistor is connected to the VCC_5V terminal, and the other end is connected to the V3P3A terminal. The fourth, fifth, and sixth pins of the first connector are all grounded. The GND pin of the second chip is grounded. The OUT terminal and the OUT1 terminal of the second chip are respectively connected to the V3P3A terminal and one end of the ninth capacitor. The other end of the ninth capacitor is grounded.

[0015] Optionally, the storage module includes: a third chip, a twelfth capacitor, and a thirteenth capacitor;

[0016] The first pin of the third chip is connected to the thirty-seventh pin of the first chip. The second pin of the third chip is connected to the fortieth pin of the first chip. The third pin of the third chip is connected to the forty-first pin of the first chip. The fourth pin of the third chip is grounded. The fifth pin of the third chip is connected to the thirty-ninth pin of the first chip. The sixth pin of the third chip is connected to the thirty-eighth pin of the first chip. The seventh pin of the third chip is connected to the forty-second pin of the first chip. The eighth pin of the third chip is respectively connected to one end of the twelfth capacitor, one end of the thirteenth capacitor, and the V3P3A terminal. The other ends of the twelfth capacitor and the thirteenth capacitor are both grounded.

[0017] Optionally, the display module includes: a second connector, a first switching transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;

[0018] The first, sixth, thirtieth, thirty-first, and thirty-second pins of the second connector are all grounded. One end of the eighth resistor is respectively connected to the seventh, eighth, ninth, and tenth pins of the first chip, and the other end is grounded. The eleventh pin of the second connector is connected to the third end of the first switching transistor. The second end of the first switching transistor is respectively connected to one end of the tenth resistor and the V3P3A terminal. The first end of the first switching transistor is respectively connected to the other end of the tenth resistor and the first end of the ninth resistor. The second end of the ninth resistor is connected to the twenty-fifth pin of the first chip;

[0019] The twelfth pin of the second connector is connected to the twenty-fourth pin of the first chip, the thirteenth pin of the second connector is connected to the eighth pin of the first chip, the fourteenth pin of the second connector is connected to the seventh pin of the first chip, the fifteenth pin of the second connector is connected to the sixth pin of the first chip, the sixteenth pin of the second connector is connected to the fifth pin of the first chip, the seventeenth pin of the second connector is connected to the fourth pin of the first chip, the eighteenth pin of the second connector is connected to the third pin of the first chip, the nineteenth pin of the second connector is connected to the second pin of the first chip, the twentieth pin of the second connector is connected to the first pin of the first chip, the twenty-first pin of the second connector is connected to the twenty-seventh pin of the first chip, the twenty-second pin of the second connector is connected to the twenty-eighth pin of the first chip, the twenty-third pin of the second connector is connected to the thirty-first pin of the first chip, the twenty-fourth pin of the second connector is connected to the thirty-second pin of the first chip, the twenty-fifth pin of the second connector is connected to the thirty-third pin of the first chip, the twenty-sixth pin of the second connector is connected to the thirty-fourth pin of the first chip, the twenty-seventh pin of the second connector is respectively connected to one end of the eleventh resistor and the ninth pin of the first chip, the twenty-eighth pin of the second connector is respectively connected to one end of the twelfth resistor and the tenth pin of the first chip, the other ends of the eleventh resistor and the twelfth resistor are grounded, and the twenty-ninth pin of the second connector is connected to the V3P3A terminal.

[0020] Optionally, the first crystal oscillator is a crystal oscillator of the SSPT7 model.

[0021] Optionally, the third chip is a chip of the GD25Q32 model.

[0022] Optionally, the first switching transistor is a Pmos transistor.

[0023] Optionally, the first switching transistor is a switching transistor of the MI3401A model.

[0024] In the second aspect of the embodiments of the present application, a control circuit of a miniPC is provided, including the LCD screen circuit as described above, and further including: a main control circuit;

[0025] The main control circuit is connected to the LCD screen circuit and is used to send a control signal to control the operation of the LCD screen circuit to switch the theme image.

[0026] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0027] The control module can control the storage module to send the target theme image data back to the control module according to an external input signal. Then, the control module controls the display module to display the corresponding theme image based on the target theme image data, completing the switching. Through the LCD screen circuit disclosed in this application, multiple theme images are stored, and the theme image of the LCD screen can be freely switched, bringing a better experience to the user. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of an embodiment of an LCD screen circuit disclosed in this application;

[0029] Figure 2 It is a schematic diagram of another embodiment of an LCD screen circuit disclosed in this application;

[0030] Figure 3 It is a schematic diagram of an embodiment of a control circuit of a mini PC disclosed in this application. Detailed Description of the Embodiment

[0031] The following further describes this application in detail with reference to the accompanying drawings.

[0032] The embodiment of this application provides an LCD screen circuit and a control circuit of a mini PC for switching the theme image of the LCD screen.

[0033] In the existing solution, the theme image of the LCD screen of the mini PC is single and cannot be switched, which cannot meet the user's pursuit of beauty. To solve the above problems, this application discloses an LCD screen circuit and a control circuit of a mini PC, so that the user can freely switch the theme image of the LCD screen, bringing a better experience to the user.

[0034] To enable those skilled in the art to better understand the solution of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only a part of the embodiments of this invention, rather than all of the embodiments. Based on the embodiments of this invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of this invention.

[0035] In the description, claims and the above drawings of the present invention, the terms "first", "second", "third", "fourth", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order different from that shown or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] A description of an LCD screen circuit of the present application will be given below. Please refer to Figure 1 , an embodiment of an LCD screen circuit of the present application includes: a control module 101, a receiving module 102, a storage module 103, and a display module 104;

[0037] The receiving module 102 is used to receive an external input signal;

[0038] The storage module 103 is used to store multiple theme image data;

[0039] The display module 104 is used to display the target theme image data;

[0040] The control module 101 is respectively connected to the receiving module 102, the storage module 103, and the display module 104, and is used to control the storage module 103 to send the target theme image data among the multiple theme image data to the control module 101 according to the external input signal sent by the receiving module 102, and control the display module 104 to display the theme image corresponding to the target theme image data according to the target theme image data.

[0041] Specifically, when the user wants to switch the theme image of the LCD screen, an external input signal is input into the receiving module 102. The receiving module 102 will inform the control module 101 which theme image needs to be selected to control the storage module 103 to return the target theme image. Among them, the storage module 103 pre-stores multiple theme images, and the user can select the required target theme image from the multiple theme images. Then the control module 101 controls the display module 104 to display the target theme image to meet the user's needs.

[0042] In the embodiment of the present application, the control module 101 can control the storage module 103 to send the target theme image data back to the control module 101 according to an external input signal. Then, the control module 101 controls the display module 104 to display the corresponding theme image based on the target theme image data, completing the switching. The LCD screen circuit disclosed in the present application stores multiple theme images and can freely switch the theme images of the LCD screen, bringing a better experience to users.

[0043] Please refer to Figure 2 , another embodiment of an LCD screen circuit of the present application includes: a control module, a receiving module, a storage module, and a display module;

[0044] Among them, the control module includes: a first chip U1, a first crystal oscillator Y1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a seventh capacitor C7;

[0045] The first pin to the tenth pin of the first chip U1 are connected to the display module. The eleventh pin and the twelfth pin of the first chip U1 are connected to the receiving module. The thirteenth pin of the first chip U1 is connected to the second end of the second capacitor C2, and the first end of the second capacitor C2 is grounded. One end of the third capacitor C3 is connected to the fourteenth pin of the first chip U1 and the V3P3A terminal, and the other end of the third capacitor C3 is grounded. The fifteenth pin of the first chip U1 is grounded. The sixteenth pin of the first chip U1 is respectively connected to the fourth test terminal, one end of the fourth resistor R4, and one end of the seventh capacitor C7. The other end of the fourth resistor R4 is connected to the V3P3A terminal, and the other end of the seventh capacitor C7 is grounded. The seventeenth pin of the first chip U1 is respectively connected to one end of the second resistor R2, one end of the third resistor R3, and one end of the fourth capacitor C4. The other end of the second resistor R2 is connected to the VCC_5V terminal. The other end of the third resistor R3 is connected to the V3P3A terminal. The other end of the fourth capacitor C4 is grounded. The eighteenth pin of the first chip U1 is respectively connected to the first end of the first crystal oscillator Y1 and one end of the fifth capacitor C5. The nineteenth pin of the first chip U1 is respectively connected to the second end of the first crystal oscillator Y1 and one end of the sixth capacitor C6. The other ends of the fifth capacitor C5 and the sixth capacitor C6 are both grounded. The twenty-fourth pin of the first chip U1 is connected to the display module;

[0046] The twenty-fifth, twenty-seventh, twenty-eighth, thirty-first, thirty-second, thirty-third, and thirty-fourth pins of the first chip U1 are all connected to the display module. The twenty-sixth pin of the first chip U1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the V3P3A terminal. The twenty-ninth pin of the first chip U1 is connected to the third test terminal, the thirtieth pin of the first chip U1 is connected to the second test terminal, the thirty-fifth pin of the first chip U1 is connected to the V3P3A terminal, the thirty-sixth pin of the first chip U1 is grounded, the thirty-seventh to forty-second pins of the first chip U1 are connected to the storage module, the forty-seventh pin of the first chip U1 is connected to the second end of the first capacitor C1 and the V3P3A terminal respectively, the forty-eighth pin of the first chip U1 is grounded and connected to the first end of the first capacitor C1 respectively, the first test terminal is connected to the V3P3A terminal, and the fifth test terminal is grounded;

[0047] Specifically, the receiving module includes: a first connector CN1, a second chip U2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and an eleventh capacitor C11;

[0048] The first pin of the first connector CN1 is connected to the VCC_5V terminal, one end of the eighth capacitor C8, and the VIN pin of the second chip U2 respectively. The other end of the eighth capacitor C8 is grounded. One end of the fifth resistor R5 is connected to the second pin of the first connector CN1, and the other end is connected to one end of the eleventh capacitor C11 and the eleventh pin of the first chip U1 respectively. One end of the sixth resistor R6 is connected to the third pin of the first connector CN1, and the other end is connected to one end of the tenth capacitor C10 and the twelfth pin of the first chip U1 respectively. The other ends of the tenth capacitor C10 and the eleventh capacitor C11 are grounded. One end of the seventh resistor R7 is connected to the VCC_5V terminal, and the other end is connected to the V3P3A terminal. The fourth, fifth, and sixth pins of the first connector CN1 are all grounded. The GND pin of the second chip U2 is grounded. The OUT terminal and the OUT1 terminal of the second chip U2 are connected to the V3P3A terminal and one end of the ninth capacitor C9 respectively. The other end of the ninth capacitor C9 is grounded;

[0049] Specifically, the storage module includes: a third chip U3, a twelfth capacitor C12, and a thirteenth capacitor C13;

[0050] The first pin of the third chip U3 is connected to the thirty-seventh pin of the first chip U1, the second pin of the third chip U3 is connected to the fortieth pin of the first chip U1, the third pin of the third chip U3 is connected to the forty-first pin of the first chip U1, the fourth pin of the third chip U3 is grounded, the fifth pin of the third chip U3 is connected to the thirty-ninth pin of the first chip U1, the sixth pin of the third chip U3 is connected to the thirty-eighth pin of the first chip U1, the seventh pin of the third chip U3 is connected to the forty-second pin of the first chip U1, the eighth pin of the third chip U3 is respectively connected to one end of the twelfth capacitor C12, one end of the thirteenth capacitor C13 and the V3P3A terminal, and the other ends of the twelfth capacitor C12 and the thirteenth capacitor C13 are both grounded;

[0051] Specifically, the display module includes: a second connector CN2, a first switching transistor Q1, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12;

[0052] The first pin, the sixth pin, the thirtieth pin, the thirty-first pin and the thirty-second pin of the second connector CN2 are all grounded. One end of the eighth resistor R8 is respectively connected to the seventh pin, the eighth pin, the ninth pin and the tenth pin of the first chip U1, and the other end is grounded. The eleventh pin of the second connector CN2 is connected to the third end of the first switching transistor Q1. The second end of the first switching transistor Q1 is respectively connected to one end of the tenth resistor R10 and the V3P3A terminal. The first end of the first switching transistor Q1 is respectively connected to the other end of the tenth resistor R10 and the first end of the ninth resistor R9. The second end of the ninth resistor R9 is connected to the twenty-fifth pin of the first chip U1;

[0053] The twelfth pin of the second connector CN2 is connected to the twenty-fourth pin of the first chip U1, the thirteenth pin of the second connector CN2 is connected to the eighth pin of the first chip U1, the fourteenth pin of the second connector CN2 is connected to the seventh pin of the first chip U1, the fifteenth pin of the second connector CN2 is connected to the sixth pin of the first chip U1, the sixteenth pin of the second connector CN2 is connected to the fifth pin of the first chip U1, the seventeenth pin of the second connector CN2 is connected to the fourth pin of the first chip U1, the eighteenth pin of the second connector CN2 is connected to the third pin of the first chip U1, the nineteenth pin of the second connector CN2 is connected to the second pin of the first chip U1, the twentieth pin of the second connector CN2 is connected to the first pin of the first chip U1, the twenty-first pin of the second connector CN2 is connected to the twenty-seventh pin of the first chip U1, the twenty-second pin of the second connector CN2 is connected to the twenty-eighth pin of the first chip U1, the twenty-third pin of the second connector CN2 is connected to the thirty-first pin of the first chip U1, the twenty-fourth pin of the second connector CN2 is connected to the thirty-second pin of the first chip U1, the twenty-fifth pin of the second connector CN2 is connected to the thirty-third pin of the first chip U1, the twenty-sixth pin of the second connector CN2 is connected to the thirty-fourth pin of the first chip U1, one end of the eleventh resistor R11 and the ninth pin of the first chip U1 are respectively connected to the twenty-seventh pin of the second connector CN2, one end of the twelfth resistor R12 and the tenth pin of the first chip U1 are respectively connected to the twenty-eighth pin of the second connector CN2, the other ends of the eleventh resistor R11 and the twelfth resistor R12 are grounded, and the twenty-ninth pin of the second connector CN2 is connected to the V3P3A terminal.

[0054] Among them, the first crystal oscillator Y1 is a crystal oscillator of the SSPT7 model, or it can be of other models, and specific details are not limited here. The third chip U3 is a chip of the GD25Q32 model, or it can be of other models, and specific details are not limited here. The first switching transistor Q1 is a Pmos transistor, which can be a switching transistor of the MI3401A model, or it can be of other types, and specific details are not limited here.

[0055] The external input signal is converted into a differential signal flowing through the fifth resistor R5 and the sixth resistor R6 and sent to the first chip U1. The first chip U1 then finds the required target theme image data from the third chip U3, and finally controls the second connector CN2 according to the target theme image data so that the LCD screen displays the corresponding target theme image.

[0056] In this embodiment, the first chip U1 controls each part to extract and convert relevant data in the third chip U3 and send it to the second connector CN2 to complete the display of the corresponding theme image, which is convenient for users. In addition, the first chip U1 and the second connector CN2 can be custom-designed and adjusted according to actual needs. When the miniPC is shut down, the LCD screen can still display the time and calendar, and when it is turned on, the current parameters such as CPU usage, CPU power, or fan speed can be viewed at any time. The theme image of the LCD screen can also be customized, bringing a good experience to users.

[0057] Please refer to Figure 3 , an embodiment of a control circuit of a miniPC disclosed in this application includes: the LCD screen circuit 302 as described in the previous two embodiments, and further includes: a main control circuit 301;

[0058] The main control circuit 301 is connected to the LCD screen circuit 302 and is used to send a control signal to control the operation of the LCD screen circuit 302 to switch the theme image.

[0059] The relevant content of the LCD screen circuit 302 in this embodiment is similar to that in the foregoing Figures 1 to 2 and will not be elaborated here.

[0060] The user operates the main control circuit 301 to send a control signal to the LCD screen circuit 302 to control the LCD screen circuit 302 to switch the theme image, which can meet the user's aesthetic pursuit of the LCD screen of the miniPC and improve the user experience.

[0061] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the circuits disclosed in the embodiments, for the reason of not elaborating, some content is described relatively simply, and the relevant parts can be referred to the relevant descriptions.

[0062] The above has introduced the LCD screen circuit and the control circuit of the miniPC provided by this application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An LCD screen circuit, characterized in that, Including: A control module, a receiving module, a storage module, and a display module; The receiving module is configured to receive an external input signal; The storage module is configured to store multiple theme image data; The display module is configured to display target theme image data; The control module is respectively connected to the receiving module, the storage module, and the display module, and is configured to control the storage module to send the target theme image data among the multiple theme image data to the control module according to the external input signal sent by the receiving module, and control the display module to display a theme image corresponding to the target theme image data according to the target theme image data; Wherein, the control module includes: a first chip, a first crystal oscillator, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a seventh capacitor; A first pin to a tenth pin of the first chip are connected to the display module, an eleventh pin and a twelfth pin of the first chip are connected to the receiving module, a thirteenth pin of the first chip is connected to a second end of the second capacitor, a first end of the second capacitor is grounded, one end of the third capacitor is connected to a fourteenth pin of the first chip and a V3P3A terminal, the other end of the third capacitor is grounded, a fifteenth pin of the first chip is grounded, a sixteenth pin of the first chip is respectively connected to a fourth test terminal, one end of the fourth resistor, and one end of the seventh capacitor, the other end of the fourth resistor is connected to the V3P3A terminal, the other end of the seventh capacitor is grounded, a seventeenth pin of the first chip is respectively connected to one end of the second resistor, one end of the third resistor, and one end of the fourth capacitor, the other end of the second resistor is connected to a VCC_5V terminal, the other end of the third resistor is connected to the V3P3A terminal, the other end of the fourth capacitor is grounded, an eighteenth pin of the first chip is respectively connected to a first end of the first crystal oscillator and one end of the fifth capacitor, a nineteenth pin of the first chip is respectively connected to a second end of the first crystal oscillator and one end of the sixth capacitor, the other ends of the fifth capacitor and the sixth capacitor are both grounded, and a twenty-fourth pin of the first chip is connected to the display module; The twenty-fifth, twenty-seventh, twenty-eighth, thirty-first, thirty-second, thirty-third, and thirty-fourth pins of the first chip are all connected to the display module. The twenty-sixth pin of the first chip is connected to one end of the first resistor, and the other end of the first resistor is connected to the V3P3A terminal. The twenty-ninth pin of the first chip is connected to the third test terminal. The thirtieth pin of the first chip is connected to the second test terminal. The thirty-fifth pin of the first chip is connected to the V3P3A terminal. The thirty-sixth pin of the first chip is grounded. The thirty-seventh to forty-second pins of the first chip are connected to the storage module. The forty-seventh pin of the first chip is respectively connected to the second end of the first capacitor and the V3P3A terminal. The forty-eighth pin of the first chip is respectively grounded and connected to the first end of the first capacitor. The first test terminal is connected to the V3P3A terminal, and the fifth test terminal is grounded; The receiving module includes: a first connector, a second chip, a fifth resistor, a sixth resistor, a seventh resistor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an eleventh capacitor; The first pin of the first connector is respectively connected to the VCC_5V terminal, one end of the eighth capacitor, and the VIN pin of the second chip. The other end of the eighth capacitor is grounded. One end of the fifth resistor is connected to the second pin of the first connector, and the other end is respectively connected to one end of the eleventh capacitor and the eleventh pin of the first chip. One end of the sixth resistor is connected to the third pin of the first connector, and the other end is respectively connected to one end of the tenth capacitor and the twelfth pin of the first chip. The other ends of the tenth capacitor and the eleventh capacitor are grounded. One end of the seventh resistor is connected to the VCC_5V terminal, and the other end is connected to the V3P3A terminal. The fourth, fifth, and sixth pins of the first connector are all grounded. The GND pin of the second chip is grounded. The OUT pin and the OUT1 pin of the second chip are respectively connected to the V3P3A terminal and one end of the ninth capacitor, and the other end of the ninth capacitor is grounded.

2. The LCD screen circuit according to claim 1, wherein The storage module includes: a third chip, a twelfth capacitor, and a thirteenth capacitor; The first pin of the third chip is connected to the thirty-seventh pin of the first chip. The second pin of the third chip is connected to the fortieth pin of the first chip. The third pin of the third chip is connected to the forty-first pin of the first chip. The fourth pin of the third chip is grounded. The fifth pin of the third chip is connected to the thirty-ninth pin of the first chip. The sixth pin of the third chip is connected to the thirty-eighth pin of the first chip. The seventh pin of the third chip is connected to the forty-second pin of the first chip. The eighth pin of the third chip is respectively connected to one end of the twelfth capacitor, one end of the thirteenth capacitor, and the V3P3A terminal. The other ends of the twelfth capacitor and the thirteenth capacitor are both grounded.

3. The LCD screen circuit according to claim 1, wherein The display module includes: a second connector, a first switching tube, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; The first pin, the sixth pin, the thirtieth pin, the thirty-first pin, and the thirty-second pin of the second connector are all grounded. One end of the eighth resistor is connected to the seventh pin, the eighth pin, the ninth pin, and the tenth pin of the first chip respectively, and the other end is grounded. The eleventh pin of the second connector is connected to the third end of the first switching transistor. The second end of the first switching transistor is connected to one end of the tenth resistor and the V3P3A terminal respectively. The first end of the first switching transistor is connected to the other end of the tenth resistor and the first end of the ninth resistor respectively. The second end of the ninth resistor is connected to the twenty-fifth pin of the first chip; The twelfth pin of the second connector is connected to the twenty-fourth pin of the first chip. The thirteenth pin of the second connector is connected to the eighth pin of the first chip. The fourteenth pin of the second connector is connected to the seventh pin of the first chip. The fifteenth pin of the second connector is connected to the sixth pin of the first chip. The sixteenth pin of the second connector is connected to the fifth pin of the first chip. The seventeenth pin of the second connector is connected to the fourth pin of the first chip. The eighteenth pin of the second connector is connected to the third pin of the first chip. The nineteenth pin of the second connector is connected to the second pin of the first chip. The twentieth pin of the second connector is connected to the first pin of the first chip. The twenty-first pin of the second connector is connected to the twenty-seventh pin of the first chip. The twenty-second pin of the second connector is connected to the twenty-eighth pin of the first chip. The twenty-third pin of the second connector is connected to the thirty-first pin of the first chip. The twenty-fourth pin of the second connector is connected to the thirty-second pin of the first chip. The twenty-fifth pin of the second connector is connected to the thirty-third pin of the first chip. The twenty-sixth pin of the second connector is connected to the thirty-fourth pin of the first chip. The twenty-seventh pin of the second connector is connected to one end of the eleventh resistor and the ninth pin of the first chip respectively. The twenty-eighth pin of the second connector is connected to one end of the twelfth resistor and the tenth pin of the first chip respectively. The other end of the eleventh resistor and the other end of the twelfth resistor are grounded. The twenty-ninth pin of the second connector is connected to the V3P3A terminal.

4. The LCD screen circuit according to claim 1, wherein The first crystal oscillator is a crystal oscillator of model SSPT7.

5. The LCD screen circuit according to claim 2, wherein The third chip is a chip of model GD25Q32.

6. The LCD screen circuit according to claim 3, wherein The first switching transistor is a Pmos transistor.

7. The LCD screen circuit according to claim 3, wherein The first switching transistor is a switching transistor of model MI3401A.

8. A control circuit of a mini PC, characterized in that, Comprising the LCD screen circuit according to any one of claims 1 to 7, further comprising: a main control circuit; The main control circuit is connected to the LCD screen circuit and is used for sending a control signal to control the operation of the LCD screen circuit to switch the theme image.

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