Solar cell and method for manufacturing the same

Abstract

The present invention relates to a solar cell and a preparation method thereof. The solar cell comprises: a single crystal silicon substrate; a first intrinsic amorphous silicon layer, an N-type doped silicon material layer, a first transparent conductive layer and a first electrode arranged in sequence on a first side of the single crystal silicon substrate; a second intrinsic amorphous silicon layer, a P-type doped silicon material layer, a second transparent conductive layer and a second electrode arranged in sequence on a second side of the single crystal silicon substrate, wherein the base material of the P-type doped silicon material layer comprises nanocrystalline silicon and / or microcrystalline silicon. A P-type doped amorphous silicon layer is arranged between the P-type doped silicon material layer and the second transparent conductive layer, and when the second transparent conductive layer is formed on the P-type doped amorphous silicon layer, it has a higher carrier mobility, so that the carrier transmission effect in the lateral direction is better. In the area corresponding to the position of the second electrode, a notch is formed in the P-type doped amorphous silicon layer, which is conducive to the transmission of carriers to the second electrode, and the P-type doped silicon material layer effectively plays a role in improving the photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Heterojunction cells (HJT cells) have many advantages, such as simple process flow, high efficiency, low temperature coefficient, energy saving due to low-temperature process throughout the process, no light-induced degradation (LID) and thermally-assisted light-induced degradation (LeTID) problems, natural bifacial cells suitable for thin-film formation, and good weak light response.

[0003] A heterojunction cell usually includes a single crystal silicon wafer; a first intrinsic amorphous silicon layer, a first doped silicon material layer, a first transparent conductive layer and a first electrode arranged on one side of the single crystal silicon wafer; and a second intrinsic amorphous silicon layer, a second doped silicon material layer, a second transparent conductive layer and a second electrode arranged on the other side of the single crystal silicon wafer. Among them, the base material of the doped silicon material layer in traditional cells is amorphous silicon, and with the development of nanocrystalline silicon and microcrystalline silicon technology, the use of nanocrystalline silicon and microcrystalline silicon instead of amorphous silicon as the base material of the doped silicon material layer can greatly improve the photoelectric conversion efficiency of heterojunction cells.

[0004] Since the optical parasitic absorption of intrinsic amorphous silicon and doped silicon material layers is relatively serious, the thickness cannot be too thick, which results in insufficient ability to transport carriers laterally. It is necessary to match a transparent conductive film layer (TCO) that is both light-transmitting and conductive to assist in the transport of carriers. However, studies have found that transparent conductive layers of materials such as ITO (tin-doped indium oxide) are very different when grown on doped amorphous silicon and when grown on doped nanocrystalline silicon and doped microcrystalline silicon. Since doped nanocrystalline silicon and doped microcrystalline silicon have higher surface root mean square roughness (rms roughness) than doped amorphous silicon, the conductive material initially grown on them has smaller grains and fractured growth, which reduces the grain size L and increases the grain barrier defect state density D. t .

[0005] The carrier mobility μ of the material eff It can be calculated by formula (1).

[0006] Formula (I)

[0007] In formula (1), m* is the effective mass of the electron, E b is the energy barrier height, T is the sample temperature, e is the charge, and k is Planck's constant.

[0008] From formula (1), we can see that the reduction of grain size L will reduce the carrier mobility μ eff , which is due to the fact that the reduction of grain size L increases the grain boundary phonon scattering, which makes the carrier mobility μeff reduce.

[0009] Energy barrier height E b It can be calculated by formula (2).

[0010] Formula (II)

[0011] From formula (2), we can see that the trapped state density D t The increase in barrier height E b This is also the reason why the carrier mobility μ eff Another reason for the decline.

[0012] Therefore, compared with deposition on doped amorphous silicon, when the transparent conductive layer is deposited on doped nanocrystalline silicon or doped microcrystalline silicon, the carrier mobility will be significantly reduced, the square resistance will increase, the electrical performance will be reduced, and the efficiency of the heterojunction battery will be negatively affected. Summary of the invention

[0013] Based on this, it is necessary to provide a solar cell and a method for preparing the same to solve the problem of electrical performance degradation when a transparent conductive layer is deposited on doped nanocrystalline silicon or doped microcrystalline silicon.

[0014] One of the objects of the present invention is to provide a solar cell, the scheme is as follows:

[0015] A solar cell, comprising:

[0016] Single crystal silicon substrate;

[0017] A first intrinsic amorphous silicon layer, an N-type doped silicon material layer, a first transparent conductive layer and a first electrode are sequentially arranged on a first side of the single crystal silicon substrate, wherein a base material of the N-type doped silicon material layer comprises at least one of nanocrystalline silicon, microcrystalline silicon and amorphous silicon;

[0018] A second intrinsic amorphous silicon layer, a P-type doped silicon material layer, a second transparent conductive layer and a second electrode are sequentially arranged on the second side of the single crystal silicon substrate, wherein the base material of the P-type doped silicon material layer comprises nanocrystalline silicon and / or microcrystalline silicon; and

[0019] The P-type doped amorphous silicon layer is disposed between the P-type doped silicon material layer and the second transparent conductive layer, and a notch is formed in the P-type doped amorphous silicon layer in a region corresponding to the position of the second electrode.

[0020] In one of the embodiments, the gap is filled with the P-type doped silicon material layer.

[0021] In one embodiment, the gap is filled by the second transparent conductive layer.

[0022] In one embodiment, the gap is filled by the P-type doped silicon material layer and the second transparent conductive layer.

[0023] In one of the embodiments, the orthographic projection of the second electrode on the single crystal silicon substrate is located within the orthographic projection of the notch on the single crystal silicon substrate.

[0024] In one embodiment, the width of the notch is greater than the width of the second electrode at the corresponding position.

[0025] In one embodiment, the width of the notch is 0-20 μm greater than the width of the second electrode at the corresponding position.

[0026] In one embodiment, the second electrode is a strip-shaped structure.

[0027] In one embodiment, the materials of the first transparent conductive layer and the second transparent conductive layer are independently selected from ITO, VTTO, SCOT, IWO, ICO, AZO, IMO, IHO, GZO, GAZO and SnO 2 At least one of .

[0028] In one of the embodiments, the thickness of the P-type doped amorphous silicon layer is 1 nm to 5 nm.

[0029] Another object of the present invention is to provide a method for preparing the solar cell described in any of the above embodiments, the scheme is as follows:

[0030] A method for preparing a solar cell comprises the following steps:

[0031] forming the first intrinsic amorphous silicon layer, the N-type doped silicon material layer, the first transparent conductive layer and the first electrode in sequence on the first side of the single crystal silicon substrate;

[0032] The second intrinsic amorphous silicon layer, the P-type doped silicon material layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer and the second electrode are sequentially formed on the second side of the single crystal silicon substrate.

[0033] In one embodiment, the step of forming the P-type doped amorphous silicon layer comprises:

[0034] forming a doped amorphous silicon material layer on the entire surface of the P-type doped silicon material layer;

[0035] The doped amorphous silicon material layer is etched to form the notch, thereby obtaining the P-type doped amorphous silicon layer.

[0036] Compared with the traditional solution, the above solar cell and its preparation method have the following beneficial effects:

[0037] The above-mentioned solar cell and its preparation method are provided with a P-type doped silicon material layer between the second intrinsic amorphous silicon layer and the second transparent conductive layer. The base material of the P-type doped silicon material layer includes nanocrystalline silicon and / or microcrystalline silicon. Compared with the traditional use of amorphous silicon alone, the photoelectric conversion efficiency of the solar cell can be greatly improved. On this basis, a P-type doped amorphous silicon layer is provided between the P-type doped silicon material layer and the second transparent conductive layer. When the second transparent conductive layer is formed on the P-type doped amorphous silicon layer, it has a higher carrier mobility, so that the carrier transmission effect in the lateral direction is better. In addition, in the area corresponding to the position of the second electrode, a gap is formed in the P-type doped amorphous silicon layer, which is conducive to the transmission of carriers to the second electrode, and the P-type doped silicon material layer effectively plays a role in improving the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural diagram of a solar cell according to an embodiment;

[0039] Figure 2 FIG. 4 is a schematic structural diagram of a solar cell according to another embodiment.

[0040] Description of reference numerals:

[0041] 10. Solar cell; 100. Single crystal silicon substrate; 210. First intrinsic amorphous silicon layer; 220. N-type doped silicon material layer; 230. First transparent conductive layer; 240. First electrode; 310. Second intrinsic amorphous silicon layer; 320. P-type doped silicon material layer; 330. P-type doped amorphous silicon layer; 331. Notch; 340. Second transparent conductive layer; 350. Second electrode. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0043] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0044] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number or order of the indicated technical features.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] Please refer to Figure 1 As shown, a solar cell 10 according to an embodiment of the present invention includes a single crystal silicon substrate 100, a first intrinsic amorphous silicon layer 210, an N-type doped silicon material layer 220, a first transparent conductive layer 230, a first electrode 240, a second intrinsic amorphous silicon layer 310, a P-type doped silicon material layer 320, a P-type doped amorphous silicon layer 330, a second transparent conductive layer 340 and a second electrode 350.

[0047] The single crystal silicon substrate 100 has a first side surface and a second side surface that are opposite to each other. The single crystal silicon substrate 100 is N-type doped.

[0048] The first intrinsic amorphous silicon layer 210, the N-type doped silicon material layer 220, the first transparent conductive layer 230 and the first electrode 240 are sequentially arranged on the first side of the single crystal silicon substrate 100. More specifically, the first intrinsic amorphous silicon layer 210 is arranged on the first side, the N-type doped silicon material layer 220 is arranged on the side of the first intrinsic amorphous silicon layer 210 away from the single crystal silicon substrate 100, and the first transparent conductive layer 230 is arranged on the side of the N-type doped silicon material layer 220 away from the single crystal silicon substrate 100. The base material of the N-type doped silicon material layer 220 includes at least one of nanocrystalline silicon, microcrystalline silicon and amorphous silicon.

[0049] The second intrinsic amorphous silicon layer 310, the P-type doped silicon material layer 320, the second transparent conductive layer 340 and the second electrode 350 are sequentially arranged on the second side of the single crystal silicon substrate 100. More specifically, the second intrinsic amorphous silicon layer 310 is arranged on the second side, the P-type doped silicon material layer 320 is arranged on the side of the second intrinsic amorphous silicon layer 310 away from the single crystal silicon substrate 100, and the second transparent conductive layer 340 is arranged on the side of the P-type doped silicon material layer 320 away from the single crystal silicon substrate 100. The base material of the P-type doped silicon material layer 320 includes nanocrystalline silicon and / or microcrystalline silicon.

[0050] The P-type doped amorphous silicon layer 330 is disposed between the P-type doped silicon material layer 320 and the second transparent conductive layer 340 , and a notch 331 is formed in the P-type doped amorphous silicon layer 330 in a region corresponding to the position of the second electrode 350 .

[0051] Among them, the single crystal silicon substrate 100 is used to absorb photons to generate electron-hole pairs. The electrons pass through the first intrinsic amorphous silicon layer 210 and the N-type doped silicon material layer 220 to enter the first electrode 240 to achieve electron collection, and the holes pass through the second intrinsic amorphous silicon layer 310 and the P-type doped silicon material layer 320 to enter the second electrode 350 to achieve hole collection, thereby forming a photocurrent.

[0052] The solar cell 10 described above is provided with a P-type doped silicon material layer 320 between the second intrinsic amorphous silicon layer 310 and the second transparent conductive layer 340. The base material of the P-type doped silicon material layer 320 includes nanocrystalline silicon and / or microcrystalline silicon. Compared with the conventional use of amorphous silicon alone, the photoelectric conversion efficiency of the solar cell 10 can be greatly improved. On this basis, a P-type doped amorphous silicon layer 330 is provided between the P-type doped silicon material layer 320 and the second transparent conductive layer 340. When the second transparent conductive layer 340 is formed on the P-type doped amorphous silicon layer 330, it has a higher carrier mobility, so that the carrier transmission effect in the lateral direction is better. In addition, in the area corresponding to the position of the second electrode 350, the P-type doped amorphous silicon layer 330 is formed with a notch 331, which is conducive to the transmission of carriers to the second electrode 350, and effectively plays the role of the P-type doped silicon material layer 320 in improving the photoelectric conversion efficiency.

[0053] The first side surface and the second side surface of the single crystal silicon substrate 100 can be set to a pyramid texture structure, which can achieve an anti-reflection effect. The pyramid texture structure can be formed by a cleaning and texture making process.

[0054] In one example, the thickness of the single crystal silicon substrate 100 is 60 μm to 180 μm, for example, 80 μm, 100 μm, 120 μm, 140 μm, etc.

[0055] In one example, the resistivity of the single crystal silicon substrate 100 is 0.2 Ω•cm to 5 Ω•cm, for example, 1 Ω•cm, 2 Ω•cm, 3 Ω•cm, 4 Ω•cm, etc.

[0056] In one example, the square resistance of the single crystal silicon substrate 100 is 20Ω / □ to 40Ω / □, for example, 25Ω / □, 30Ω / □, 35Ω / □, 40Ω / □, etc.

[0057] In one example, the thickness of the first intrinsic amorphous silicon layer 210 is 2 nm to 10 nm, for example, 3 nm, 5 nm, 7 nm, 9 nm, etc.

[0058] In one example, the thickness of the second intrinsic amorphous silicon layer 310 is 2 nm to 10 nm, for example, 3 nm, 5 nm, 7 nm, 9 nm, etc.

[0059] Since the optical parasitic absorption of N-type doped amorphous silicon is relatively serious, placing it on the front side is not conducive to the utilization of light, but will reduce the efficiency of the battery. Therefore, the base material of the N-type doped silicon material layer 220 is preferably nanocrystalline silicon and / or microcrystalline silicon. In one example, the base material of the N-type doped silicon material layer 220 includes nanocrystalline silicon. In one example, the base material of the N-type doped silicon material layer 220 includes microcrystalline silicon.

[0060] In one example, the thickness of the N-type doped silicon material layer 220 is 5 nm to 20 nm, specifically 7 nm, 11 nm, 15 nm, 19 nm, etc.

[0061] The base material of the P-type doped silicon material layer 320 includes nanocrystalline silicon and / or microcrystalline silicon. In one example, the base material of the P-type doped silicon material layer 320 includes nanocrystalline silicon. In one example, the base material of the P-type doped silicon material layer 320 includes microcrystalline silicon.

[0062] In one example, the thickness of the P-type doped silicon material layer 320 is 5 nm to 20 nm, specifically 7 nm, 11 nm, 15 nm, 19 nm, etc.

[0063] In one example, the thickness of the P-type doped amorphous silicon layer 330 is 1 nm to 5 nm, for example, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0064] In one example, the second electrode 350 is configured as a strip-shaped structure. The notch 331 formed by the P-type doped amorphous silicon layer 330 is also configured as a strip-shaped structure accordingly. In other examples, the second electrode 350 and the notch 331 are not limited to being strip-shaped structures.

[0065] In one example, the orthographic projection of the second electrode 350 on the single crystal silicon substrate 100 is located within the orthographic projection of the notch 331 on the single crystal silicon substrate 100. In this example, the width of the notch 331 is not less than the width of the second electrode 350 at the corresponding position, which is conducive to the transmission of carriers to the second electrode 350.

[0066] In one example, the width of the notch 331 is greater than the width of the second electrode 350 at the corresponding position. For example, the width of the notch 331 is 0-20 μm greater than the width of the second electrode 350 at the corresponding position. Further, the width of the notch 331 is 1 μm-20 μm greater than the width of the second electrode 350 at the corresponding position. Further, the width of the notch 331 is 5 μm-15 μm greater than the width of the second electrode 350 at the corresponding position. In some specific examples, the width of the notch 331 is 0.5 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 14 μm, 18 μm, etc. greater than the width of the second electrode 350 at the corresponding position.

[0067] In other examples, the width of the notch 331 may also be smaller than the width of the second electrode 350 at the corresponding position.

[0068] In one example, the width of the second electrode 350 is 20 μm to 40 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, etc.

[0069] In one example, the width of the notch 331 is 30 μm to 50 μm, for example, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.

[0070] Optionally, the gap 331 of the P-type doped amorphous silicon layer 330 is filled with at least one of the P-type doped silicon material layer 320 and the second transparent conductive layer 340 .

[0071] exist Figure 1 In the specific example shown, the gap 331 is filled with the second transparent conductive layer 340 .

[0072] exist Figure 2 In the specific example shown, the gap 331 is filled with the P-type doped silicon material layer 320. In this example, the P-type doped silicon material layer 320 has a greater thickness in the region corresponding to the second electrode 350, which is more conducive to the transmission of carriers to the second electrode 350.

[0073] It can be understood that in other examples, the gap 331 can also be filled by the P-type doped silicon material layer 320 and the second transparent conductive layer 340 .

[0074] Optionally, the materials of the first transparent conductive layer 230 and the second transparent conductive layer 340 may be, but are not limited to, ITO (tin-doped indium oxide), VTTO, SCOT (indium oxide doped with zirconium, titanium, and calcium), IWO (tungsten-doped indium oxide), ICO (cerium-doped indium oxide), AZO (aluminum-doped zinc oxide), IMO (molybdenum-doped indium oxide), IHO (hydrogenated indium oxide), GZO (gallium-doped zinc oxide), GAZO (aluminum-gallium co-doped zinc oxide), SnO 2(tin oxide-one or more. The materials of the first transparent conductive layer 230 and the second transparent conductive layer 340 can be the same or different. In one example, the materials of the first transparent conductive layer 230 and the second transparent conductive layer 340 both include ITO. Further, In in ITO 2 O 3 The mass fraction of SnO is 90%~99%, 2 The mass fraction is 1%~10%.

[0075] In one example, the thickness of the first transparent conductive layer 230 is 50 nm to 100 nm, for example, 60 nm, 70 nm, 80 nm, 90 nm, etc.

[0076] In one example, the thickness of the second transparent conductive layer 340 is 80 nm to 150 nm, for example, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0077] Furthermore, the present invention also provides a method for preparing any of the above-mentioned solar cells 10, comprising the following steps:

[0078] A first intrinsic amorphous silicon layer 210, an N-type doped silicon material layer 220, a first transparent conductive layer 230 and a first electrode 240 are sequentially formed on a first side of a single crystal silicon substrate 100;

[0079] A second intrinsic amorphous silicon layer 310 , a P-type doped silicon material layer 320 , a P-type doped amorphous silicon layer 330 , a P-type doped amorphous silicon layer 330 , and a second electrode 350 are sequentially formed on the second side of the single crystal silicon substrate 100 .

[0080] Before forming the first intrinsic amorphous silicon layer 210 and the second intrinsic amorphous silicon layer 310, the single crystal silicon substrate 100 is preferably subjected to a gettering process to remove metal ion impurities inside the single crystal silicon substrate 100 and improve the substrate quality. The gettering process can be performed using a high-temperature tubular phosphorus diffusion process or a chain gettering device. Preferably, the sheet resistance of the single crystal silicon substrate 100 after the gettering process is 20Ω / □ to 40Ω / □.

[0081] Before forming the first intrinsic amorphous silicon layer 210 and the second intrinsic amorphous silicon layer 310, the single crystal silicon substrate 100 is preferably cleaned and texturized. Before the cleaning and texturizing treatment, an acidic solution may be used to remove the doped silicon oxide layer (such as a PSG layer) formed on the surface of the silicon wafer after the impurities are absorbed. The cleaning and texturizing treatment uses an alkaline cleaning solution to clean the second side and / or the first side of the single crystal silicon substrate 100, and can be further cleaned using an RCA cleaning process, and then hydrofluoric acid is used to remove the surface oxide layer, and then deionized water is used to clean the surface residual reagent.

[0082] The preparation process of the first intrinsic amorphous silicon layer 210 and the second intrinsic amorphous silicon layer 310 can be, but is not limited to, a CVD (chemical vapor deposition) process, such as LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), etc. In one example, the first intrinsic amorphous silicon layer 210 and the second intrinsic amorphous silicon layer 310 are prepared by RF-PECVD (radio frequency plasma enhanced chemical vapor deposition) process. The RF power supply of the PECVD equipment power supply is 10MHz~40MHz, such as 13.56MHz, 26MHz, 40MHz, etc., preferably 13.56MHz. The process gas contains SiH 4 , and can further include H 2 , CO 2 , CH 4 、N 2 O, etc. The deposition process temperature is, for example, 160° C. to 220° C. The deposition process pressure is, for example, 0.2 mbar to 2 mbar.

[0083] The preparation process of the N-type doped silicon material layer 220 and the P-type doped silicon material layer 320 can be, but is not limited to, a CVD process, such as LPCVD, PECVD, etc. In one example, the N-type doped silicon material layer 220 and the P-type doped silicon material layer 320 are prepared by RF-PECVD or VHF-CVD (very high frequency plasma enhanced chemical vapor deposition) process. The RF power supply of the PECVD equipment power supply is 10MHz~40MHz, such as 13.56MHz, 26MHz, 40MHz, etc., preferably 13.56MHz. The VHF-CVD equipment frequency preferably uses 40MHz.

[0084] When preparing the N-type doped silicon material layer 220, the process gas includes SiH 4 and PH 3 N-type doping sources such as H 2 , CO 2 , CH 4 、N 2 O. The deposition process temperature is, for example, 160° C. to 200° C. The deposition process pressure is, for example, 0.5 mbar to 5 mbar. When preparing the P-type doped silicon material layer 320, the process gas includes SiH 4 and TMB (trimethyl boron) and other P-type doping sources, and may further include H 2 , CO 2 , CH 4 、N 2 O.B 2 H 6The deposition process temperature is, for example, 160° C. to 200° C. The deposition process pressure is, for example, 0.5 mbar to 5 mbar.

[0085] The preparation process of the P-type doped amorphous silicon layer 330 may be, but is not limited to, a CVD process, such as LPCVD, PECVD, etc. In one example, the second intrinsic amorphous silicon layer 310 is prepared by an RF-PECVD process. The RF power supply of the PECVD equipment is 10MHz~40MHz, such as 13.56MHz, 26MHz, 40MHz, etc., preferably 13.56MHz. The process gas contains SiH 4 , and can further include H 2 , CO 2 , CH 4 、N 2 O. The deposition process temperature is, for example, 160° C. to 200° C. The deposition process pressure is, for example, 0.5 mbar to 5 mbar.

[0086] In one example, the step of forming the P-type doped amorphous silicon layer 330 includes:

[0087] forming a doped amorphous silicon material layer on the entire surface of the P-type doped silicon material layer 320;

[0088] The doped amorphous silicon material layer is etched to form a notch 331 , thereby obtaining a P-type doped amorphous silicon layer 330 .

[0089] for Figure 2 In the specific example of the solar cell 10 shown, after forming a P-type doped silicon material layer 320 on the entire surface, the non-electrode area of ​​the P-type doped silicon material layer 320 is thinned, and then a doped amorphous silicon material layer is formed on the entire surface of the P-type doped silicon material layer 320, and then the electrode area of ​​the doped amorphous silicon material layer is etched to form a notch 331, thereby obtaining a P-type doped amorphous silicon layer 330.

[0090] Optionally, the etching treatment may be, but is not limited to, laser etching, alkaline solution etching, etc. When thinning the non-electrode region of the P-type doped silicon material layer 320 , laser etching, alkaline solution etching, etc. may also be used.

[0091] The laser etching may be performed using a pulsed laser, such as a green laser or a violet laser with a pulse width of less than 100 picoseconds. In one example, the laser etching is performed using a green laser with a pulse width of less than 20 nanoseconds (laser wavelength is, for example, 532nm). In order to reduce or avoid laser damage that may lead to a decrease in battery efficiency, it is preferred to use a discontinuous point laser for etching.

[0092] When etching with an alkaline solution, a mask layer can be first covered on the non-electrode area of ​​the doped amorphous silicon material layer. The material of the mask layer is, for example, photosensitive ink. The mask layer forms an etching window that exposes the area to be etched of the doped amorphous silicon material layer. Then an alkaline solution is applied, and the alkaline solution etches through the etching window.

[0093] The preparation process of the first transparent conductive layer 230 and the second transparent conductive layer 340 can be but is not limited to a PVD (physical vapor deposition) process, such as a magnetron sputtering process, an evaporation process, etc. In one example, the first transparent conductive layer 230 and the second transparent conductive layer 340 are prepared by a magnetron sputtering process. The sputtering target is selected according to the needs, and the process gas includes Ar and O 2 , and can further include H 2 , H 2 O, etc. The power density of the magnetron sputtering process is, for example, 2KW / m 2 ~8KW / m 2 The deposition process temperature is, for example, 0° C. to 200° C. The deposition process pressure is, for example, 0.3 Pa to 0.8 Pa.

[0094] The first electrode 240 and the second electrode 350 can be prepared by printing, laser transfer or electroplating. Among them, the printing process and the laser transfer process can use low-temperature silver paste, low-temperature copper paste, silver-coated copper paste, etc. The electroplating process can use an electroplating solution containing one or more ions of aluminum (Al), titanium (Ti), nickel (Ni), cobalt (Co), silver (Ag), copper (Cu), and tin (Sn).

[0095] The above-mentioned solar cell 10 and its preparation method are provided with a P-type doped silicon material layer 320 between the second intrinsic amorphous silicon layer 310 and the second transparent conductive layer 340. The base material of the P-type doped silicon material layer 320 includes nanocrystalline silicon and / or microcrystalline silicon. Compared with the conventional method of simply using amorphous silicon, the photoelectric conversion efficiency of the solar cell 10 can be greatly improved. On this basis, a P-type doped amorphous silicon layer 330 is provided between the P-type doped silicon material layer 320 and the second transparent conductive layer 340. When the second transparent conductive layer 340 is formed on the P-type doped amorphous silicon layer 330, it has a higher carrier mobility, so that the carrier transmission effect in the lateral direction is better. In addition, in the area corresponding to the position of the second electrode 350, the P-type doped amorphous silicon layer 330 is formed with a notch 331, which is conducive to the transmission of carriers to the second electrode 350, and effectively plays the role of the P-type doped silicon material layer 320 in improving the photoelectric conversion efficiency.

[0096] The present invention is further described below in conjunction with specific embodiments and comparative examples, but the present invention is not limited to the following specific embodiments.

[0097] Example 1

[0098] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0099] Step 1, provide an N-type single crystal silicon wafer, use a high-temperature tubular phosphorus diffusion process to perform doping treatment on the single crystal silicon wafer, then use an acidic solution to remove the PSG layer formed on the surface of the single crystal silicon wafer after doping, and then use an alkaline cleaning solution to clean and texturize both sides of the single crystal silicon wafer, and then use RCA cleaning, hydrofluoric acid cleaning, and then deionized water cleaning to use as a single crystal silicon substrate.

[0100] Step 2: using RF-PECVD process to deposit a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on both sides of the single crystal silicon substrate.

[0101] Step 3: Using RF-PECVD process to deposit an N-type doped silicon material layer on the first intrinsic amorphous silicon layer.

[0102] Step 4: deposit a P-type doped silicon material layer on the second intrinsic amorphous silicon layer using an RF-PECVD process.

[0103] Step 5: Using RF-PECVD process to deposit a P-type doped amorphous silicon layer on the P-type doped silicon material layer.

[0104] Step 6: Use a green laser with a pulse width of less than 20 nanoseconds and a wavelength of 532 nm to etch the P-type doped silicon material layer to remove the portion corresponding to the electrode area to form a gap.

[0105] Step 7, using a magnetron sputtering process to deposit ITO on the entire front surface to form a first transparent conductive layer.

[0106] Step 8, depositing ITO on the entire back surface using a magnetron sputtering process to form a second transparent conductive layer.

[0107] Step 9: Form a first electrode on the first transparent conductive layer by using a screen printing process.

[0108] Step 10: Form a second electrode on the second transparent conductive layer by screen printing, wherein the width of the second electrode is 10 μm smaller than the width of the gap.

[0109] Example 2

[0110] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0111] This embodiment provides a method for preparing a solar cell, comprising the following steps:

[0112] Step 1, provide an N-type single crystal silicon wafer, use a high-temperature tubular phosphorus diffusion process to perform doping treatment on the single crystal silicon wafer, then use an acidic solution to remove the PSG layer formed on the surface of the single crystal silicon wafer after doping, and then use an alkaline cleaning solution to clean and texturize both sides of the single crystal silicon wafer, and then use RCA cleaning, hydrofluoric acid cleaning, and then deionized water cleaning to use as a single crystal silicon substrate.

[0113] Step 2: using RF-PECVD process to deposit a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on both sides of the single crystal silicon substrate.

[0114] Step 3: Using RF-PECVD process to deposit an N-type doped silicon material layer on the first intrinsic amorphous silicon layer.

[0115] Step 4: deposit a P-type doped silicon material layer on the second intrinsic amorphous silicon layer using an RF-PECVD process.

[0116] Step 5: Cover the electrode area of ​​the P-type doped silicon material layer with photosensitive ink, and thin the non-electrode area with an alkaline solution.

[0117] Step 6: Using RF-PECVD process to deposit a P-type doped amorphous silicon layer on the P-type doped silicon material layer. The gas contains SiH 4 , H 2 , CO 2 , CH 4 、N 2 O, etc.

[0118] Step 7: Use a green laser with a pulse width of less than 20 nanoseconds and a wavelength of 532 nm to etch the P-type doped silicon material layer to remove the portion corresponding to the electrode area to form a gap.

[0119] Step 8, depositing ITO on the entire front surface using a magnetron sputtering process to form a first transparent conductive layer.

[0120] Step 9, depositing ITO on the entire back surface using a magnetron sputtering process to form a second transparent conductive layer.

[0121] Step 10: Form a first electrode on the first transparent conductive layer by using a screen printing process.

[0122] Step 11: Form a second electrode on the second transparent conductive layer by screen printing, wherein the width of the second electrode is 10 μm smaller than the width of the gap.

[0123] Comparative Example 1

[0124] The difference between this comparative example and Example 1 is that no P-type doped amorphous silicon layer is formed, that is, step 5 and step 6 in Example 1 are not performed.

[0125] Comparative Example 2

[0126] The difference between this comparative example and Example 2 is that the P-type doped amorphous silicon layer is not formed, that is, Steps 5 to 7 in Example 2 are not performed.

[0127] The solar cells prepared in the above-mentioned Examples 1-2 and Comparative Examples 1-2 were subjected to performance tests, and the test results are shown in Table 1.

[0128] Table 1 Performance test results of solar cells prepared in Examples and Comparative Examples

[0129]

[0130] Compared with comparative example 1, in embodiment 1 and in embodiment 2, a P-type doped amorphous silicon layer is provided between the P-type doped silicon material layer and the second transparent conductive layer. When the second transparent conductive layer is formed on the P-type doped amorphous silicon layer, it has a higher carrier mobility, so that the carrier transmission effect in the lateral direction is better. In addition, a gap is formed in the P-type doped amorphous silicon layer in the area corresponding to the position of the second electrode, which is conducive to the transmission of carriers to the second electrode. As can be seen from the results in Table 1, the conversion efficiency of embodiments 1 and 2 has been significantly improved.

[0131] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: Single crystal silicon substrate; A first intrinsic amorphous silicon layer, an N-type doped silicon material layer, a first transparent conductive layer and a first electrode are sequentially arranged on a first side of the single crystal silicon substrate, wherein a base material of the N-type doped silicon material layer comprises at least one of nanocrystalline silicon, microcrystalline silicon and amorphous silicon; A second intrinsic amorphous silicon layer, a P-type doped silicon material layer, a second transparent conductive layer and a second electrode are sequentially arranged on the second side of the single crystal silicon substrate, wherein the base material of the P-type doped silicon material layer comprises nanocrystalline silicon and / or microcrystalline silicon; as well as The P-type doped amorphous silicon layer is disposed between the P-type doped silicon material layer and the second transparent conductive layer, and a notch is formed in the P-type doped amorphous silicon layer in a region corresponding to the position of the second electrode.

2. The solar cell according to claim 1, wherein: The gap is filled with the P-type doped silicon material layer; or, The gap is filled by the second transparent conductive layer; or, The gap is filled by the P-type doped silicon material layer and the second transparent conductive layer.

3. The solar cell according to claim 1, wherein: The orthographic projection of the second electrode on the single crystal silicon substrate is located within the orthographic projection of the notch on the single crystal silicon substrate.

4. The solar cell according to claim 3, characterized in that The width of the notch is greater than the width of the second electrode at the corresponding position.

5. The solar cell according to claim 4, characterized in that The width of the notch is 0-20 μm greater than the width of the second electrode at the corresponding position.

6. The solar cell according to any one of claims 1 to 5, characterized in that The second electrode is a strip-shaped structure.

7. The solar cell according to any one of claims 1 to 5, characterized in that Materials of the first transparent conductive layer and the second transparent conductive layer are independently selected from at least one of ITO, VTTO, SCOT, IWO, ICO, AZO, IMO, IHO, GZO, GAZO and SnO2.

8. The solar cell according to any one of claims 1 to 5, characterized in that The thickness of the P-type doped amorphous silicon layer is 1 nm to 5 nm.

9. A method for preparing a solar cell according to any one of claims 1 to 8, characterized in that: The following steps are involved: forming the first intrinsic amorphous silicon layer, the N-type doped silicon material layer, the first transparent conductive layer and the first electrode in sequence on the first side of the single crystal silicon substrate; The second intrinsic amorphous silicon layer, the P-type doped silicon material layer, the P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer and the second electrode are sequentially formed on the second side of the single crystal silicon substrate.

10. The preparation method according to claim 9, characterized in that: The step of forming the P-type doped amorphous silicon layer comprises: forming a doped amorphous silicon material layer on the entire surface of the P-type doped silicon material layer; The doped amorphous silicon material layer is etched to form the notch, thereby obtaining the P-type doped amorphous silicon layer.

Images